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Merging r322319: ------------------------------------------------------------------------ r322319 | matze | 2018-01-11 14:30:43 -0800 (Thu, 11 Jan 2018) | 7 lines PeepholeOptimizer: Fix for vregs without defs The PeepholeOptimizer would fail for vregs without a definition. If this was caused by an undef operand abort to keep the code simple (so we don't need to add logic everywhere to replicate the undef flag). Differential Revision: https://reviews.llvm.org/D40763 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@329619 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 9 months ago
5 changed file(s) with 74 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
420420 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
421421 /// and \p DefIdx.
422422 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
423 /// the list is modeled as .
423 /// the list is modeled as . Operands with the undef
424 /// flag are not added to this list.
424425 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
425426 /// two elements:
426427 /// - %1:sub1, sub0
445446 /// - %1:sub1, sub0
446447 ///
447448 /// \returns true if it is possible to build such an input sequence
448 /// with the pair \p MI, \p DefIdx. False otherwise.
449 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
450 /// False otherwise.
449451 ///
450452 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
451453 ///
464466 /// - InsertedReg: %1:sub1, sub3
465467 ///
466468 /// \returns true if it is possible to build such an input sequence
467 /// with the pair \p MI, \p DefIdx. False otherwise.
469 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
470 /// False otherwise.
468471 ///
469472 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
470473 ///
18811881 return ValueTrackerResult();
18821882 // Otherwise, we want the whole source.
18831883 const MachineOperand &Src = Def->getOperand(1);
1884 if (Src.isUndef())
1885 return ValueTrackerResult();
18841886 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
18851887 }
18861888
19241926 }
19251927
19261928 const MachineOperand &Src = Def->getOperand(SrcIdx);
1929 if (Src.isUndef())
1930 return ValueTrackerResult();
19271931 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
19281932 }
19291933
20922096 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
20932097 auto &MO = Def->getOperand(i);
20942098 assert(MO.isReg() && "Invalid PHI instruction");
2099 // We have no code to deal with undef operands. They shouldn't happen in
2100 // normal programs anyway.
2101 if (MO.isUndef())
2102 return ValueTrackerResult();
20952103 Res.addSource(MO.getReg(), MO.getSubReg());
20962104 }
20972105
21482156 // If we can still move up in the use-def chain, move to the next
21492157 // definition.
21502158 if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
2151 Def = MRI.getVRegDef(Reg);
2152 DefIdx = MRI.def_begin(Reg).getOperandNo();
2153 DefSubReg = Res.getSrcSubReg(0);
2159 MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
2160 if (DI != MRI.def_end()) {
2161 Def = DI->getParent();
2162 DefIdx = DI.getOperandNo();
2163 DefSubReg = Res.getSrcSubReg(0);
2164 } else {
2165 Def = nullptr;
2166 }
21542167 return Res;
21552168 }
21562169 }
11501150 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
11511151 OpIdx += 2) {
11521152 const MachineOperand &MOReg = MI.getOperand(OpIdx);
1153 if (MOReg.isUndef())
1154 continue;
11531155 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
11541156 assert(MOSubIdx.isImm() &&
11551157 "One of the subindex of the reg_sequence is not an immediate");
11731175 // Def = EXTRACT_SUBREG v0.sub1, sub0.
11741176 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
11751177 const MachineOperand &MOReg = MI.getOperand(1);
1178 if (MOReg.isUndef())
1179 return false;
11761180 const MachineOperand &MOSubIdx = MI.getOperand(2);
11771181 assert(MOSubIdx.isImm() &&
11781182 "The subindex of the extract_subreg is not an immediate");
11971201 assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
11981202 const MachineOperand &MOBaseReg = MI.getOperand(1);
11991203 const MachineOperand &MOInsertedReg = MI.getOperand(2);
1204 if (MOInsertedReg.isUndef())
1205 return false;
12001206 const MachineOperand &MOSubIdx = MI.getOperand(3);
12011207 assert(MOSubIdx.isImm() &&
12021208 "One of the subindex of the reg_sequence is not an immediate");
48634863 // Populate the InputRegs accordingly.
48644864 // rY
48654865 const MachineOperand *MOReg = &MI.getOperand(1);
4866 InputRegs.push_back(
4867 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4866 if (!MOReg->isUndef())
4867 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
4868 MOReg->getSubReg(), ARM::ssub_0));
48684869 // rZ
48694870 MOReg = &MI.getOperand(2);
4870 InputRegs.push_back(
4871 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4871 if (!MOReg->isUndef())
4872 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
4873 MOReg->getSubReg(), ARM::ssub_1));
48724874 return true;
48734875 }
48744876 llvm_unreachable("Target dependent opcode missing");
48874889 // rX = EXTRACT_SUBREG dZ, ssub_0
48884890 // rY = EXTRACT_SUBREG dZ, ssub_1
48894891 const MachineOperand &MOReg = MI.getOperand(2);
4892 if (MOReg.isUndef())
4893 return false;
48904894 InputReg.Reg = MOReg.getReg();
48914895 InputReg.SubReg = MOReg.getSubReg();
48924896 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
49064910 // dX = VSETLNi32 dY, rZ, imm
49074911 const MachineOperand &MOBaseReg = MI.getOperand(1);
49084912 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4913 if (MOInsertedReg.isUndef())
4914 return false;
49094915 const MachineOperand &MOIndex = MI.getOperand(3);
49104916 BaseReg.Reg = MOBaseReg.getReg();
49114917 BaseReg.SubReg = MOBaseReg.getSubReg();
6464 %4:gpr = PHI %0, %bb.1, %2, %bb.2
6565 %5:spr = VMOVSR %4, 14, %noreg
6666 ...
67
68 # The current implementation doesn't perform any transformations if undef
69 # operands are involved.
70 # CHECK-LABEL: name: func-undefops
71 # CHECK: body: |
72 # CHECK: bb.0:
73 # CHECK: Bcc %bb.2, 1, undef %cpsr
74 #
75 # CHECK: bb.1:
76 # CHECK: %0:gpr = VMOVRS undef %1:spr, 14, %noreg
77 # CHECK: B %bb.3
78 #
79 # CHECK: bb.2:
80 # CHECK: %2:gpr = VMOVRS undef %3:spr, 14, %noreg
81 #
82 # CHECK: bb.3:
83 # CHECK: %4:gpr = PHI %0, %bb.1, %2, %bb.2
84 # CHECK: %5:spr = VMOVSR %4, 14, %noreg
85 ---
86 name: func-undefops
87 tracksRegLiveness: true
88 body: |
89 bb.0:
90 Bcc %bb.2, 1, undef %cpsr
91
92 bb.1:
93 %0:gpr = VMOVRS undef %1:spr, 14, %noreg
94 B %bb.3
95
96 bb.2:
97 %2:gpr = VMOVRS undef %3:spr, 14, %noreg
98
99 bb.3:
100 %4:gpr = PHI %0, %bb.1, %2, %bb.2
101 %5:spr = VMOVSR %4, 14, %noreg
102 ...