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[SVE][Inline-Asm] Add constraints for SVE predicate registers Summary: Adds the following inline asm constraints for SVE: - Upl: One of the low eight SVE predicate registers, P0 to P7 inclusive - Upa: SVE predicate register with full range, P0 to P15 Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened, rengolin Reviewed By: rovka Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66524 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371967 91177308-0d34-0410-b5e6-96231b3b80d8 Kerry McLaughlin a month ago
6 changed file(s) with 81 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
38243824 - ``w``: A 32, 64, or 128-bit floating-point, SIMD or SVE vector register.
38253825 - ``x``: Like w, but restricted to registers 0 to 15 inclusive.
38263826 - ``y``: Like w, but restricted to SVE vector registers Z0 to Z7 inclusive.
3827 - ``Upl``: One of the low eight SVE predicate registers (P0 to P7)
3828 - ``Upa``: Any of the SVE predicate registers (P0 to P15)
38273829
38283830 AMDGPU:
38293831
180180 // FIXME: For now assuming these are 2-character constraints.
181181 pCodes->push_back(StringRef(I+1, 2));
182182 I += 3;
183 } else if (*I == '@') {
184 // Multi-letter constraint
185 ++I;
186 unsigned char C = static_cast(*I);
187 assert(isdigit(C) && "Expected a digit!");
188 int N = C - '0';
189 assert(N > 0 && "Found a zero letter constraint!");
190 ++I;
191 pCodes->push_back(StringRef(I, N));
192 I += N;
183193 } else {
184194 // Single letter constraint.
185195 pCodes->push_back(StringRef(I, 1));
617617 const TargetRegisterClass *RegClass;
618618 if (AArch64::ZPRRegClass.contains(Reg)) {
619619 RegClass = &AArch64::ZPRRegClass;
620 } else if (AArch64::PPRRegClass.contains(Reg)) {
621 RegClass = &AArch64::PPRRegClass;
620622 } else {
621623 RegClass = &AArch64::FPR128RegClass;
622624 AltName = AArch64::vreg;
58365836 return "r";
58375837 }
58385838
5839 enum PredicateConstraint {
5840 Upl,
5841 Upa,
5842 Invalid
5843 };
5844
5845 PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
5846 PredicateConstraint P = PredicateConstraint::Invalid;
5847 if (Constraint == "Upa")
5848 P = PredicateConstraint::Upa;
5849 if (Constraint == "Upl")
5850 P = PredicateConstraint::Upl;
5851 return P;
5852 }
5853
58395854 /// getConstraintType - Given a constraint letter, return the type of
58405855 /// constraint it is for this target.
58415856 AArch64TargetLowering::ConstraintType
58655880 case 'S': // A symbolic address
58665881 return C_Other;
58675882 }
5868 }
5883 } else if (parsePredicateConstraint(Constraint) !=
5884 PredicateConstraint::Invalid)
5885 return C_RegisterClass;
58695886 return TargetLowering::getConstraintType(Constraint);
58705887 }
58715888
58955912 break;
58965913 case 'z':
58975914 weight = CW_Constant;
5915 break;
5916 case 'U':
5917 if (parsePredicateConstraint(constraint) != PredicateConstraint::Invalid)
5918 weight = CW_Register;
58985919 break;
58995920 }
59005921 return weight;
59395960 if (VT.isScalableVector())
59405961 return std::make_pair(0U, &AArch64::ZPR_3bRegClass);
59415962 break;
5963 }
5964 } else {
5965 PredicateConstraint PC = parsePredicateConstraint(Constraint);
5966 if (PC != PredicateConstraint::Invalid) {
5967 assert(VT.isScalableVector());
5968 bool restricted = (PC == PredicateConstraint::Upl);
5969 return restricted ? std::make_pair(0U, &AArch64::PPR_3bRegClass)
5970 : std::make_pair(0U, &AArch64::PPRRegClass);
59425971 }
59435972 }
59445973 if (StringRef("{cc}").equals_lower(Constraint))
25032503 .addReg(SrcReg, getKillRegState(KillSrc));
25042504 }
25052505 }
2506 return;
2507 }
2508
2509 // Copy a Predicate register by ORRing with itself.
2510 if (AArch64::PPRRegClass.contains(DestReg) &&
2511 AArch64::PPRRegClass.contains(SrcReg)) {
2512 assert(Subtarget.hasSVE() && "Unexpected SVE register.");
2513 BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
2514 .addReg(SrcReg) // Pg
2515 .addReg(SrcReg)
2516 .addReg(SrcReg, getKillRegState(KillSrc));
25062517 return;
25072518 }
25082519
77 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
88 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
99 ; CHECK: [[ARG4:%[0-9]+]]:zpr_3b = COPY [[ARG1]]
10 ; CHECK: INLINEASM {{.*}} [[ARG4]]
1011 define @test_svadd_i8( %Zn, %Zm) {
1112 %1 = tail call asm "add $0.b, $1.b, $2.b", "=w,w,y"( %Zn, %Zm)
1213 ret %1
1718 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
1819 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
1920 ; CHECK: [[ARG4:%[0-9]+]]:zpr_4b = COPY [[ARG1]]
21 ; CHECK: INLINEASM {{.*}} [[ARG4]]
2022 define @test_svsub_i64( %Zn, %Zm) {
2123 %1 = tail call asm "sub $0.d, $1.d, $2.d", "=w,w,x"( %Zn, %Zm)
2224 ret %1
2729 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
2830 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
2931 ; CHECK: [[ARG4:%[0-9]+]]:zpr_3b = COPY [[ARG1]]
32 ; CHECK: INLINEASM {{.*}} [[ARG4]]
3033 define @test_svfmul_f16( %Zn, %Zm) {
3134 %1 = tail call asm "fmul $0.h, $1.h, $2.h", "=w,w,y"( %Zn, %Zm)
3235 ret %1
3740 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
3841 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
3942 ; CHECK: [[ARG4:%[0-9]+]]:zpr_4b = COPY [[ARG1]]
43 ; CHECK: INLINEASM {{.*}} [[ARG4]]
4044 define @test_svfmul_f( %Zn, %Zm) {
4145 %1 = tail call asm "fmul $0.s, $1.s, $2.s", "=w,w,x"( %Zn, %Zm)
4246 ret %1
4347 }
48
49 ; Function Attrs: nounwind readnone
50 ; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
51 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
52 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
53 ; CHECK: [[ARG4:%[0-9]+]]:ppr_3b = COPY [[ARG3]]
54 ; CHECK: INLINEASM {{.*}} [[ARG4]]
55 define @test_svfadd_f16( %Pg, %Zn, %Zm) {
56 %1 = tail call asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"( %Pg, %Zn, %Zm)
57 ret %1
58 }
59
60 ; Function Attrs: nounwind readnone
61 ; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z0
62 ; CHECK: [[ARG2:%[0-9]+]]:ppr = COPY $p0
63 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY [[ARG2]]
64 ; CHECK: [[ARG4:%[0-9]+]]:zpr = COPY [[ARG1]]
65 ; CHECK: INLINEASM {{.*}} [[ARG3]]
66 define @test_incp( %Pg, %Zn) {
67 %1 = tail call asm "incp $0.s, $1", "=w,@3Upa,0"( %Pg, %Zn)
68 ret %1
69 }