llvm.org GIT mirror llvm / 48c1bc2
Handle some 64-bit atomics on x86-32, some of the time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8 Dale Johannesen 12 years ago
7 changed file(s) with 1318 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
62116211 break;
62126212 }
62136213
6214 // FIXME: should the LOAD_BIN and SWAP atomics get here too? Probably.
6215 case ISD::ATOMIC_CMP_SWAP_8:
6216 case ISD::ATOMIC_CMP_SWAP_16:
6217 case ISD::ATOMIC_CMP_SWAP_32:
6214 case ISD::ATOMIC_LOAD_ADD_64:
6215 case ISD::ATOMIC_LOAD_SUB_64:
6216 case ISD::ATOMIC_LOAD_AND_64:
6217 case ISD::ATOMIC_LOAD_OR_64:
6218 case ISD::ATOMIC_LOAD_XOR_64:
6219 case ISD::ATOMIC_LOAD_NAND_64:
6220 case ISD::ATOMIC_SWAP_64:
62186221 case ISD::ATOMIC_CMP_SWAP_64: {
6219 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6220 assert(Tmp.getNode() && "Node must be custom expanded!");
6221 ExpandOp(Tmp.getValue(0), Lo, Hi);
6222 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6223 LegalizeOp(Tmp.getValue(1)));
6224 break;
6225 }
6226
6227
6222 SDValue In2Lo, In2Hi, In2;
6223 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6224 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6225 SDValue Result = TLI.LowerOperation(
6226 DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), Op.getOperand(1), In2),
6227 DAG);
6228 ExpandOp(Result.getValue(0), Lo, Hi);
6229 // Remember that we legalized the chain.
6230 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6231 break;
6232 }
62286233
62296234 // These operators cannot be expanded directly, emit them as calls to
62306235 // library functions.
159159
160160 private:
161161 SDNode *Select(SDValue N);
162 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
162163
163164 bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
164165 bool isRoot = true, unsigned Depth = 0);
12041205 MVT::i8, N0, SRIdx, N0.getValue(1));
12051206 }
12061207
1208 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1209 SDValue Chain = Node->getOperand(0);
1210 SDValue In1 = Node->getOperand(1);
1211 SDValue In2L = Node->getOperand(2);
1212 SDValue In2H = Node->getOperand(3);
1213 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1214 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
1215 return NULL;
1216 AddToISelQueue(Tmp0);
1217 AddToISelQueue(Tmp1);
1218 AddToISelQueue(Tmp2);
1219 AddToISelQueue(Tmp3);
1220 AddToISelQueue(In2L);
1221 AddToISelQueue(In2H);
1222 AddToISelQueue(Chain);
1223 SDValue LSI = CurDAG->getMemOperand(cast(In1)->getMemOperand());
1224 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
1225 return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8);
1226 }
12071227
12081228 SDNode *X86DAGToDAGISel::Select(SDValue N) {
12091229 SDNode *Node = N.getNode();
12751295 // Other cases are handled by auto-generated code.
12761296 break;
12771297 }
1298
1299 case X86ISD::ATOMOR64_DAG:
1300 return SelectAtomic64(Node, X86::ATOMOR6432);
1301 case X86ISD::ATOMXOR64_DAG:
1302 return SelectAtomic64(Node, X86::ATOMXOR6432);
1303 case X86ISD::ATOMADD64_DAG:
1304 return SelectAtomic64(Node, X86::ATOMADD6432);
1305 case X86ISD::ATOMSUB64_DAG:
1306 return SelectAtomic64(Node, X86::ATOMSUB6432);
1307 case X86ISD::ATOMNAND64_DAG:
1308 return SelectAtomic64(Node, X86::ATOMNAND6432);
1309 case X86ISD::ATOMAND64_DAG:
1310 return SelectAtomic64(Node, X86::ATOMAND6432);
12781311
12791312 case ISD::SMUL_LOHI:
12801313 case ISD::UMUL_LOHI: {
300300 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Custom);
301301 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Custom);
302302 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
303
304 if (!Subtarget->is64Bit()) {
305 setOperationAction(ISD::ATOMIC_LOAD_ADD_64, MVT::i64, Custom);
306 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
307 setOperationAction(ISD::ATOMIC_LOAD_AND_64, MVT::i64, Custom);
308 setOperationAction(ISD::ATOMIC_LOAD_OR_64, MVT::i64, Custom);
309 setOperationAction(ISD::ATOMIC_LOAD_XOR_64, MVT::i64, Custom);
310 setOperationAction(ISD::ATOMIC_LOAD_NAND_64, MVT::i64, Custom);
311 setOperationAction(ISD::ATOMIC_SWAP_64, MVT::i64, Custom);
312 }
303313
304314 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
305315 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
60036013 return DAG.getMergeValues(Vals, 2).getNode();
60046014 }
60056015
6016 SDValue X86TargetLowering::LowerATOMIC_BINARY_64(SDValue Op,
6017 SelectionDAG &DAG,
6018 unsigned NewOp) {
6019 SDNode *Node = Op.getNode();
6020 MVT T = Node->getValueType(0);
6021 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6022
6023 SDValue Chain = Node->getOperand(0);
6024 SDValue In1 = Node->getOperand(1);
6025 assert(Node->getOperand(2).getNode()->getOpcode()==ISD::BUILD_PAIR);
6026 SDValue In2L = Node->getOperand(2).getNode()->getOperand(0);
6027 SDValue In2H = Node->getOperand(2).getNode()->getOperand(1);
6028 SDValue Ops[] = { Chain, In1, In2L, In2H };
6029 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6030 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 4);
6031 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6032 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
6033 SDValue Vals[2] = { ResultVal, Result.getValue(2) };
6034 return SDValue(DAG.getMergeValues(Vals, 2).getNode(), 0);
6035 }
6036
60066037 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
60076038 SDNode *Node = Op.getNode();
60086039 MVT T = Node->getValueType(0);
60266057 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
60276058 switch (Op.getOpcode()) {
60286059 default: assert(0 && "Should not custom lower this!");
6029 case ISD::ATOMIC_CMP_SWAP_8: return LowerCMP_SWAP(Op,DAG);
6030 case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
6031 case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
6060 case ISD::ATOMIC_CMP_SWAP_8:
6061 case ISD::ATOMIC_CMP_SWAP_16:
6062 case ISD::ATOMIC_CMP_SWAP_32:
60326063 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
6033 case ISD::ATOMIC_LOAD_SUB_8: return LowerLOAD_SUB(Op,DAG);
6034 case ISD::ATOMIC_LOAD_SUB_16: return LowerLOAD_SUB(Op,DAG);
6064 case ISD::ATOMIC_LOAD_SUB_8:
6065 case ISD::ATOMIC_LOAD_SUB_16:
60356066 case ISD::ATOMIC_LOAD_SUB_32: return LowerLOAD_SUB(Op,DAG);
6036 case ISD::ATOMIC_LOAD_SUB_64: return LowerLOAD_SUB(Op,DAG);
6067 case ISD::ATOMIC_LOAD_SUB_64: return (Subtarget->is64Bit()) ?
6068 LowerLOAD_SUB(Op,DAG) :
6069 LowerATOMIC_BINARY_64(Op,DAG,
6070 X86ISD::ATOMSUB64_DAG);
6071 case ISD::ATOMIC_LOAD_AND_64: return LowerATOMIC_BINARY_64(Op,DAG,
6072 X86ISD::ATOMAND64_DAG);
6073 case ISD::ATOMIC_LOAD_OR_64: return LowerATOMIC_BINARY_64(Op, DAG,
6074 X86ISD::ATOMOR64_DAG);
6075 case ISD::ATOMIC_LOAD_XOR_64: return LowerATOMIC_BINARY_64(Op,DAG,
6076 X86ISD::ATOMXOR64_DAG);
6077 case ISD::ATOMIC_LOAD_NAND_64: return LowerATOMIC_BINARY_64(Op,DAG,
6078 X86ISD::ATOMNAND64_DAG);
6079 case ISD::ATOMIC_LOAD_ADD_64: return LowerATOMIC_BINARY_64(Op,DAG,
6080 X86ISD::ATOMADD64_DAG);
60376081 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
60386082 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
60396083 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
61396183 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
61406184 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
61416185 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6186 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6187 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6188 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6189 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6190 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6191 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
61426192 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
61436193 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
61446194 case X86ISD::VSHL: return "X86ISD::VSHL";
63566406
63576407 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
63586408 MIB.addReg(EAXreg);
6409
6410 // insert branch
6411 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6412
6413 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6414 return nextMBB;
6415 }
6416
6417 // private utility function
6418 MachineBasicBlock *
6419 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6420 MachineBasicBlock *MBB,
6421 unsigned regOpcL,
6422 unsigned regOpcH,
6423 unsigned immOpcL,
6424 unsigned immOpcH,
6425 bool invSrc) {
6426 // For the atomic bitwise operator, we generate
6427 // thisMBB (instructions are in pairs, except cmpxchg8b)
6428 // ld t1,t2 = [bitinstr.addr]
6429 // newMBB:
6430 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6431 // op t5, t6 <- out1, out2, [bitinstr.val]
6432 // mov ECX, EBX <- t5, t6
6433 // mov EAX, EDX <- t1, t2
6434 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6435 // mov t3, t4 <- EAX, EDX
6436 // bz newMBB
6437 // result in out1, out2
6438 // fallthrough -->nextMBB
6439
6440 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6441 const unsigned LoadOpc = X86::MOV32rm;
6442 const unsigned copyOpc = X86::MOV32rr;
6443 const unsigned NotOpc = X86::NOT32r;
6444 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6445 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6446 MachineFunction::iterator MBBIter = MBB;
6447 ++MBBIter;
6448
6449 /// First build the CFG
6450 MachineFunction *F = MBB->getParent();
6451 MachineBasicBlock *thisMBB = MBB;
6452 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6453 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6454 F->insert(MBBIter, newMBB);
6455 F->insert(MBBIter, nextMBB);
6456
6457 // Move all successors to thisMBB to nextMBB
6458 nextMBB->transferSuccessors(thisMBB);
6459
6460 // Update thisMBB to fall through to newMBB
6461 thisMBB->addSuccessor(newMBB);
6462
6463 // newMBB jumps to itself and fall through to nextMBB
6464 newMBB->addSuccessor(nextMBB);
6465 newMBB->addSuccessor(newMBB);
6466
6467 // Insert instructions into newMBB based on incoming instruction
6468 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6469 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6470 MachineOperand& dest1Oper = bInstr->getOperand(0);
6471 MachineOperand& dest2Oper = bInstr->getOperand(1);
6472 MachineOperand* argOpers[6];
6473 for (int i=0; i < 6; ++i)
6474 argOpers[i] = &bInstr->getOperand(i+2);
6475
6476 // x86 address has 4 operands: base, index, scale, and displacement
6477 int lastAddrIndx = 3; // [0,3]
6478
6479 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6480 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6481 for (int i=0; i <= lastAddrIndx; ++i)
6482 (*MIB).addOperand(*argOpers[i]);
6483 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6484 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6485 // add 4 to displacement. getImm verifies it's immediate.
6486 for (int i=0; i <= lastAddrIndx-1; ++i)
6487 (*MIB).addOperand(*argOpers[i]);
6488 MachineOperand newOp3 = MachineOperand::CreateImm(argOpers[3]->getImm()+4);
6489 (*MIB).addOperand(newOp3);
6490
6491 // t3/4 are defined later, at the bottom of the loop
6492 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6493 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6494 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6495 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6496 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6497 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6498
6499 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6500 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6501 if (invSrc) {
6502 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6503 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
6504 } else {
6505 tt1 = t1;
6506 tt2 = t2;
6507 }
6508
6509 assert((argOpers[4]->isRegister() || argOpers[4]->isImmediate()) &&
6510 "invalid operand");
6511 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
6512 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6513 if (argOpers[4]->isRegister())
6514 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
6515 else
6516 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6517 MIB.addReg(tt1);
6518 (*MIB).addOperand(*argOpers[4]);
6519 assert(argOpers[5]->isRegister() == argOpers[4]->isRegister());
6520 assert(argOpers[5]->isImmediate() == argOpers[4]->isImmediate());
6521 if (argOpers[5]->isRegister())
6522 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
6523 else
6524 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6525 MIB.addReg(tt2);
6526 (*MIB).addOperand(*argOpers[5]);
6527
6528 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
6529 MIB.addReg(t1);
6530 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
6531 MIB.addReg(t2);
6532
6533 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
6534 MIB.addReg(t5);
6535 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
6536 MIB.addReg(t6);
6537
6538 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
6539 for (int i=0; i <= lastAddrIndx; ++i)
6540 (*MIB).addOperand(*argOpers[i]);
6541
6542 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6543 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6544
6545 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
6546 MIB.addReg(X86::EAX);
6547 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
6548 MIB.addReg(X86::EDX);
63596549
63606550 // insert branch
63616551 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
66946884 X86::NOT8r, X86::AL,
66956885 X86::GR8RegisterClass, true);
66966886 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
6887 // This group is for 64-bit host.
66976888 case X86::ATOMAND64:
66986889 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
66996890 X86::AND64ri32, X86::MOV64rm,
67266917 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
67276918 case X86::ATOMUMAX64:
67286919 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
6920
6921 // This group does 64-bit operations on a 32-bit host.
6922 case X86::ATOMAND6432:
6923 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6924 X86::AND32rr, X86::AND32rr,
6925 X86::AND32ri, X86::AND32ri,
6926 false);
6927 case X86::ATOMOR6432:
6928 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6929 X86::OR32rr, X86::OR32rr,
6930 X86::OR32ri, X86::OR32ri,
6931 false);
6932 case X86::ATOMXOR6432:
6933 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6934 X86::XOR32rr, X86::XOR32rr,
6935 X86::XOR32ri, X86::XOR32ri,
6936 false);
6937 case X86::ATOMNAND6432:
6938 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6939 X86::AND32rr, X86::AND32rr,
6940 X86::AND32ri, X86::AND32ri,
6941 true);
6942 // FIXME carry
6943 case X86::ATOMADD6432:
6944 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6945 X86::ADD32rr, X86::ADC32rr,
6946 X86::ADD32ri, X86::ADC32ri,
6947 false);
6948 // FIXME carry
6949 case X86::ATOMSUB6432:
6950 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6951 X86::SUB32rr, X86::SBB32rr,
6952 X86::SUB32ri, X86::SBB32ri,
6953 false);
67296954 }
67306955 }
67316956
197197 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
198198 LCMPXCHG_DAG,
199199 LCMPXCHG8_DAG,
200
201 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
202 // ATOMXOR64_DAG, ATOMNAND64_DAG - Atomic 64-bit binary operations.
203 ATOMADD64_DAG,
204 ATOMSUB64_DAG,
205 ATOMOR64_DAG,
206 ATOMXOR64_DAG,
207 ATOMAND64_DAG,
208 ATOMNAND64_DAG,
200209
201210 // FNSTCW16m - Store FP control world into i16 memory.
202211 FNSTCW16m,
569578 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
570579 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
571580 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
581 SDValue LowerATOMIC_BINARY_64(SDValue Op, SelectionDAG &DAG,
582 unsigned NewOp);
572583 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
573584 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
574585 SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
601612 unsigned EAXreg,
602613 TargetRegisterClass *RC,
603614 bool invSrc = false);
615
616 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
617 MachineInstr *BInstr,
618 MachineBasicBlock *BB,
619 unsigned regOpcL,
620 unsigned regOpcH,
621 unsigned immOpcL,
622 unsigned immOpcH,
623 bool invSrc = false);
604624
605625 /// Utility function to emit atomic min and max. It takes the min/max
606626 // instruction to expand, the associated basic block, and the associated
3838 SDTCisVT<2, i8>]>;
3939 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
4040
41 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
42 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
4143 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
4244
4345 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
7880 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
7981 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
8082 SDNPMayLoad]>;
81
83 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
84 [SDNPHasChain, SDNPMayStore,
85 SDNPMayLoad, SDNPMemOperand]>;
86 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
87 [SDNPHasChain, SDNPMayStore,
88 SDNPMayLoad, SDNPMemOperand]>;
89 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
90 [SDNPHasChain, SDNPMayStore,
91 SDNPMayLoad, SDNPMemOperand]>;
92 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
93 [SDNPHasChain, SDNPMayStore,
94 SDNPMayLoad, SDNPMemOperand]>;
95 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
96 [SDNPHasChain, SDNPMayStore,
97 SDNPMayLoad, SDNPMemOperand]>;
98 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
99 [SDNPHasChain, SDNPMayStore,
100 SDNPMayLoad, SDNPMemOperand]>;
82101 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
83102 [SDNPHasChain, SDNPOptInFlag]>;
84103
26292648 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
26302649 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
26312650 }
2632 let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2651 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
26332652 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
26342653 "lock\n\tcmpxchg8b\t$ptr",
26352654 [(X86cas8 addr:$ptr)]>, TB, LOCK;
27292748 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
27302749 }
27312750
2751 let Constraints = "$val1 = $dst1, $val2 = $dst2",
2752 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
2753 Uses = [EAX, EBX, ECX, EDX],
2754 usesCustomDAGSchedInserter = 1 in {
2755 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2756 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2757 "#ATOMAND6432 PSUEDO!", []>;
2758 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2759 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2760 "#ATOMOR6432 PSUEDO!", []>;
2761 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2762 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2763 "#ATOMXOR6432 PSUEDO!", []>;
2764 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2765 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2766 "#ATOMNAND6432 PSUEDO!", []>;
2767 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2768 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2769 "#ATOMADD6432 PSUEDO!", []>;
2770 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2771 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2772 "#ATOMSUB6432 PSUEDO!", []>;
2773 }
2774
27322775 //===----------------------------------------------------------------------===//
27332776 // Non-Instruction Patterns
27342777 //===----------------------------------------------------------------------===//
0 ; RUN: llvm-as < %s | llc -march=x86
1 ;; This version includes 64-bit version of binary operators (in 32-bit mode).
2 ;; Swap, cmp-and-swap not supported yet in this mode.
3 ; ModuleID = 'Atomics.c'
4 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
5 target triple = "i386-apple-darwin8"
6 @sc = common global i8 0 ; [#uses=52]
7 @uc = common global i8 0 ; [#uses=112]
8 @ss = common global i16 0 ; [#uses=15]
9 @us = common global i16 0 ; [#uses=15]
10 @si = common global i32 0 ; [#uses=15]
11 @ui = common global i32 0 ; [#uses=23]
12 @sl = common global i32 0 ; [#uses=15]
13 @ul = common global i32 0 ; [#uses=15]
14 @sll = common global i64 0, align 8 ; [#uses=13]
15 @ull = common global i64 0, align 8 ; [#uses=13]
16
17 define void @test_op_ignore() nounwind {
18 entry:
19 %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 1) ; [#uses=0]
20 %1 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 1) ; [#uses=0]
21 %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
22 %3 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %2, i16 1) ; [#uses=0]
23 %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
24 %5 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %4, i16 1) ; [#uses=0]
25 %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
26 %7 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %6, i32 1) ; [#uses=0]
27 %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
28 %9 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %8, i32 1) ; [#uses=0]
29 %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
30 %11 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %10, i32 1) ; [#uses=0]
31 %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
32 %13 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %12, i32 1) ; [#uses=0]
33 %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
34 %15 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %14, i64 1) ; [#uses=0]
35 %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
36 %17 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %16, i64 1) ; [#uses=0]
37 %18 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 1) ; [#uses=0]
38 %19 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 1) ; [#uses=0]
39 %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
40 %21 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %20, i16 1) ; [#uses=0]
41 %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
42 %23 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %22, i16 1) ; [#uses=0]
43 %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
44 %25 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %24, i32 1) ; [#uses=0]
45 %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
46 %27 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %26, i32 1) ; [#uses=0]
47 %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
48 %29 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %28, i32 1) ; [#uses=0]
49 %30 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
50 %31 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %30, i32 1) ; [#uses=0]
51 %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
52 %33 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %32, i64 1) ; [#uses=0]
53 %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
54 %35 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %34, i64 1) ; [#uses=0]
55 %36 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 1) ; [#uses=0]
56 %37 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 1) ; [#uses=0]
57 %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
58 %39 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %38, i16 1) ; [#uses=0]
59 %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
60 %41 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %40, i16 1) ; [#uses=0]
61 %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
62 %43 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %42, i32 1) ; [#uses=0]
63 %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
64 %45 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %44, i32 1) ; [#uses=0]
65 %46 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
66 %47 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %46, i32 1) ; [#uses=0]
67 %48 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
68 %49 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %48, i32 1) ; [#uses=0]
69 %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
70 %51 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %50, i64 1) ; [#uses=0]
71 %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
72 %53 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %52, i64 1) ; [#uses=0]
73 %54 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 1) ; [#uses=0]
74 %55 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 1) ; [#uses=0]
75 %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
76 %57 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %56, i16 1) ; [#uses=0]
77 %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
78 %59 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %58, i16 1) ; [#uses=0]
79 %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
80 %61 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %60, i32 1) ; [#uses=0]
81 %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
82 %63 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %62, i32 1) ; [#uses=0]
83 %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
84 %65 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %64, i32 1) ; [#uses=0]
85 %66 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
86 %67 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %66, i32 1) ; [#uses=0]
87 %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
88 %69 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %68, i64 1) ; [#uses=0]
89 %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
90 %71 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %70, i64 1) ; [#uses=0]
91 %72 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 1) ; [#uses=0]
92 %73 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 1) ; [#uses=0]
93 %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
94 %75 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %74, i16 1) ; [#uses=0]
95 %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
96 %77 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %76, i16 1) ; [#uses=0]
97 %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
98 %79 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %78, i32 1) ; [#uses=0]
99 %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
100 %81 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %80, i32 1) ; [#uses=0]
101 %82 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
102 %83 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %82, i32 1) ; [#uses=0]
103 %84 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
104 %85 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %84, i32 1) ; [#uses=0]
105 %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
106 %87 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %86, i64 1) ; [#uses=0]
107 %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
108 %89 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %88, i64 1) ; [#uses=0]
109 %90 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 1) ; [#uses=0]
110 %91 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 1) ; [#uses=0]
111 %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
112 %93 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %92, i16 1) ; [#uses=0]
113 %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
114 %95 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %94, i16 1) ; [#uses=0]
115 %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
116 %97 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %96, i32 1) ; [#uses=0]
117 %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
118 %99 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %98, i32 1) ; [#uses=0]
119 %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
120 %101 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %100, i32 1) ; [#uses=0]
121 %102 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
122 %103 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %102, i32 1) ; [#uses=0]
123 %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
124 %105 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %104, i64 1) ; [#uses=0]
125 %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
126 %107 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %106, i64 1) ; [#uses=0]
127 br label %return
128
129 return: ; preds = %entry
130 ret void
131 }
132
133 declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind
134
135 declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind
136
137 declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
138
139 declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind
140
141 declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind
142
143 declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind
144
145 declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
146
147 declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind
148
149 declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind
150
151 declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind
152
153 declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
154
155 declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind
156
157 declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind
158
159 declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind
160
161 declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
162
163 declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind
164
165 declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind
166
167 declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind
168
169 declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
170
171 declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind
172
173 declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind
174
175 declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind
176
177 declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind
178
179 declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind
180
181 define void @test_fetch_and_op() nounwind {
182 entry:
183 %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 11) ; [#uses=1]
184 store i8 %0, i8* @sc, align 1
185 %1 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 11) ; [#uses=1]
186 store i8 %1, i8* @uc, align 1
187 %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
188 %3 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %2, i16 11) ; [#uses=1]
189 store i16 %3, i16* @ss, align 2
190 %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
191 %5 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %4, i16 11) ; [#uses=1]
192 store i16 %5, i16* @us, align 2
193 %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
194 %7 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %6, i32 11) ; [#uses=1]
195 store i32 %7, i32* @si, align 4
196 %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
197 %9 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %8, i32 11) ; [#uses=1]
198 store i32 %9, i32* @ui, align 4
199 %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
200 %11 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %10, i32 11) ; [#uses=1]
201 store i32 %11, i32* @sl, align 4
202 %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
203 %13 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %12, i32 11) ; [#uses=1]
204 store i32 %13, i32* @ul, align 4
205 %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
206 %15 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %14, i64 11) ; [#uses=1]
207 store i64 %15, i64* @sll, align 8
208 %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
209 %17 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %16, i64 11) ; [#uses=1]
210 store i64 %17, i64* @ull, align 8
211 %18 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 11) ; [#uses=1]
212 store i8 %18, i8* @sc, align 1
213 %19 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 11) ; [#uses=1]
214 store i8 %19, i8* @uc, align 1
215 %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
216 %21 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %20, i16 11) ; [#uses=1]
217 store i16 %21, i16* @ss, align 2
218 %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
219 %23 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %22, i16 11) ; [#uses=1]
220 store i16 %23, i16* @us, align 2
221 %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
222 %25 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %24, i32 11) ; [#uses=1]
223 store i32 %25, i32* @si, align 4
224 %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
225 %27 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %26, i32 11) ; [#uses=1]
226 store i32 %27, i32* @ui, align 4
227 %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
228 %29 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %28, i32 11) ; [#uses=1]
229 store i32 %29, i32* @sl, align 4
230 %30 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
231 %31 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %30, i32 11) ; [#uses=1]
232 store i32 %31, i32* @ul, align 4
233 %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
234 %33 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %32, i64 11) ; [#uses=1]
235 store i64 %33, i64* @sll, align 8
236 %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
237 %35 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %34, i64 11) ; [#uses=1]
238 store i64 %35, i64* @ull, align 8
239 %36 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 11) ; [#uses=1]
240 store i8 %36, i8* @sc, align 1
241 %37 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 11) ; [#uses=1]
242 store i8 %37, i8* @uc, align 1
243 %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
244 %39 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %38, i16 11) ; [#uses=1]
245 store i16 %39, i16* @ss, align 2
246 %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
247 %41 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %40, i16 11) ; [#uses=1]
248 store i16 %41, i16* @us, align 2
249 %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
250 %43 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %42, i32 11) ; [#uses=1]
251 store i32 %43, i32* @si, align 4
252 %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
253 %45 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %44, i32 11) ; [#uses=1]
254 store i32 %45, i32* @ui, align 4
255 %46 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
256 %47 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %46, i32 11) ; [#uses=1]
257 store i32 %47, i32* @sl, align 4
258 %48 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
259 %49 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %48, i32 11) ; [#uses=1]
260 store i32 %49, i32* @ul, align 4
261 %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
262 %51 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %50, i64 11) ; [#uses=1]
263 store i64 %51, i64* @sll, align 8
264 %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
265 %53 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %52, i64 11) ; [#uses=1]
266 store i64 %53, i64* @ull, align 8
267 %54 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 11) ; [#uses=1]
268 store i8 %54, i8* @sc, align 1
269 %55 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 11) ; [#uses=1]
270 store i8 %55, i8* @uc, align 1
271 %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
272 %57 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %56, i16 11) ; [#uses=1]
273 store i16 %57, i16* @ss, align 2
274 %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
275 %59 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %58, i16 11) ; [#uses=1]
276 store i16 %59, i16* @us, align 2
277 %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
278 %61 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %60, i32 11) ; [#uses=1]
279 store i32 %61, i32* @si, align 4
280 %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
281 %63 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %62, i32 11) ; [#uses=1]
282 store i32 %63, i32* @ui, align 4
283 %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
284 %65 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %64, i32 11) ; [#uses=1]
285 store i32 %65, i32* @sl, align 4
286 %66 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
287 %67 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %66, i32 11) ; [#uses=1]
288 store i32 %67, i32* @ul, align 4
289 %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
290 %69 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %68, i64 11) ; [#uses=1]
291 store i64 %69, i64* @sll, align 8
292 %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
293 %71 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %70, i64 11) ; [#uses=1]
294 store i64 %71, i64* @ull, align 8
295 %72 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 11) ; [#uses=1]
296 store i8 %72, i8* @sc, align 1
297 %73 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 11) ; [#uses=1]
298 store i8 %73, i8* @uc, align 1
299 %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
300 %75 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %74, i16 11) ; [#uses=1]
301 store i16 %75, i16* @ss, align 2
302 %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
303 %77 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %76, i16 11) ; [#uses=1]
304 store i16 %77, i16* @us, align 2
305 %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
306 %79 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %78, i32 11) ; [#uses=1]
307 store i32 %79, i32* @si, align 4
308 %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
309 %81 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %80, i32 11) ; [#uses=1]
310 store i32 %81, i32* @ui, align 4
311 %82 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
312 %83 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %82, i32 11) ; [#uses=1]
313 store i32 %83, i32* @sl, align 4
314 %84 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
315 %85 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %84, i32 11) ; [#uses=1]
316 store i32 %85, i32* @ul, align 4
317 %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
318 %87 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %86, i64 11) ; [#uses=1]
319 store i64 %87, i64* @sll, align 8
320 %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
321 %89 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %88, i64 11) ; [#uses=1]
322 store i64 %89, i64* @ull, align 8
323 %90 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 11) ; [#uses=1]
324 store i8 %90, i8* @sc, align 1
325 %91 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 11) ; [#uses=1]
326 store i8 %91, i8* @uc, align 1
327 %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
328 %93 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %92, i16 11) ; [#uses=1]
329 store i16 %93, i16* @ss, align 2
330 %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
331 %95 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %94, i16 11) ; [#uses=1]
332 store i16 %95, i16* @us, align 2
333 %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
334 %97 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %96, i32 11) ; [#uses=1]
335 store i32 %97, i32* @si, align 4
336 %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
337 %99 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %98, i32 11) ; [#uses=1]
338 store i32 %99, i32* @ui, align 4
339 %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
340 %101 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %100, i32 11) ; [#uses=1]
341 store i32 %101, i32* @sl, align 4
342 %102 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
343 %103 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %102, i32 11) ; [#uses=1]
344 store i32 %103, i32* @ul, align 4
345 %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
346 %105 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %104, i64 11) ; [#uses=1]
347 store i64 %105, i64* @sll, align 8
348 %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
349 %107 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %106, i64 11) ; [#uses=1]
350 store i64 %107, i64* @ull, align 8
351 br label %return
352
353 return: ; preds = %entry
354 ret void
355 }
356
357 define void @test_op_and_fetch() nounwind {
358 entry:
359 %0 = load i8* @uc, align 1 ; [#uses=1]
360 %1 = zext i8 %0 to i32 ; [#uses=1]
361 %2 = trunc i32 %1 to i8 ; [#uses=2]
362 %3 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 %2) ; [#uses=1]
363 %4 = add i8 %3, %2 ; [#uses=1]
364 store i8 %4, i8* @sc, align 1
365 %5 = load i8* @uc, align 1 ; [#uses=1]
366 %6 = zext i8 %5 to i32 ; [#uses=1]
367 %7 = trunc i32 %6 to i8 ; [#uses=2]
368 %8 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 %7) ; [#uses=1]
369 %9 = add i8 %8, %7 ; [#uses=1]
370 store i8 %9, i8* @uc, align 1
371 %10 = load i8* @uc, align 1 ; [#uses=1]
372 %11 = zext i8 %10 to i32 ; [#uses=1]
373 %12 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
374 %13 = trunc i32 %11 to i16 ; [#uses=2]
375 %14 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %12, i16 %13) ; [#uses=1]
376 %15 = add i16 %14, %13 ; [#uses=1]
377 store i16 %15, i16* @ss, align 2
378 %16 = load i8* @uc, align 1 ; [#uses=1]
379 %17 = zext i8 %16 to i32 ; [#uses=1]
380 %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
381 %19 = trunc i32 %17 to i16 ; [#uses=2]
382 %20 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %18, i16 %19) ; [#uses=1]
383 %21 = add i16 %20, %19 ; [#uses=1]
384 store i16 %21, i16* @us, align 2
385 %22 = load i8* @uc, align 1 ; [#uses=1]
386 %23 = zext i8 %22 to i32 ; [#uses=2]
387 %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
388 %25 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %24, i32 %23) ; [#uses=1]
389 %26 = add i32 %25, %23 ; [#uses=1]
390 store i32 %26, i32* @si, align 4
391 %27 = load i8* @uc, align 1 ; [#uses=1]
392 %28 = zext i8 %27 to i32 ; [#uses=2]
393 %29 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
394 %30 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %29, i32 %28) ; [#uses=1]
395 %31 = add i32 %30, %28 ; [#uses=1]
396 store i32 %31, i32* @ui, align 4
397 %32 = load i8* @uc, align 1 ; [#uses=1]
398 %33 = zext i8 %32 to i32 ; [#uses=2]
399 %34 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
400 %35 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %34, i32 %33) ; [#uses=1]
401 %36 = add i32 %35, %33 ; [#uses=1]
402 store i32 %36, i32* @sl, align 4
403 %37 = load i8* @uc, align 1 ; [#uses=1]
404 %38 = zext i8 %37 to i32 ; [#uses=2]
405 %39 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
406 %40 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %39, i32 %38) ; [#uses=1]
407 %41 = add i32 %40, %38 ; [#uses=1]
408 store i32 %41, i32* @ul, align 4
409 %42 = load i8* @uc, align 1 ; [#uses=1]
410 %43 = zext i8 %42 to i64 ; [#uses=2]
411 %44 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
412 %45 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %44, i64 %43) ; [#uses=1]
413 %46 = add i64 %45, %43 ; [#uses=1]
414 store i64 %46, i64* @sll, align 8
415 %47 = load i8* @uc, align 1 ; [#uses=1]
416 %48 = zext i8 %47 to i64 ; [#uses=2]
417 %49 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
418 %50 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %49, i64 %48) ; [#uses=1]
419 %51 = add i64 %50, %48 ; [#uses=1]
420 store i64 %51, i64* @ull, align 8
421 %52 = load i8* @uc, align 1 ; [#uses=1]
422 %53 = zext i8 %52 to i32 ; [#uses=1]
423 %54 = trunc i32 %53 to i8 ; [#uses=2]
424 %55 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 %54) ; [#uses=1]
425 %56 = sub i8 %55, %54 ; [#uses=1]
426 store i8 %56, i8* @sc, align 1
427 %57 = load i8* @uc, align 1 ; [#uses=1]
428 %58 = zext i8 %57 to i32 ; [#uses=1]
429 %59 = trunc i32 %58 to i8 ; [#uses=2]
430 %60 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 %59) ; [#uses=1]
431 %61 = sub i8 %60, %59 ; [#uses=1]
432 store i8 %61, i8* @uc, align 1
433 %62 = load i8* @uc, align 1 ; [#uses=1]
434 %63 = zext i8 %62 to i32 ; [#uses=1]
435 %64 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
436 %65 = trunc i32 %63 to i16 ; [#uses=2]
437 %66 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %64, i16 %65) ; [#uses=1]
438 %67 = sub i16 %66, %65 ; [#uses=1]
439 store i16 %67, i16* @ss, align 2
440 %68 = load i8* @uc, align 1 ; [#uses=1]
441 %69 = zext i8 %68 to i32 ; [#uses=1]
442 %70 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
443 %71 = trunc i32 %69 to i16 ; [#uses=2]
444 %72 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %70, i16 %71) ; [#uses=1]
445 %73 = sub i16 %72, %71 ; [#uses=1]
446 store i16 %73, i16* @us, align 2
447 %74 = load i8* @uc, align 1 ; [#uses=1]
448 %75 = zext i8 %74 to i32 ; [#uses=2]
449 %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
450 %77 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %76, i32 %75) ; [#uses=1]
451 %78 = sub i32 %77, %75 ; [#uses=1]
452 store i32 %78, i32* @si, align 4
453 %79 = load i8* @uc, align 1 ; [#uses=1]
454 %80 = zext i8 %79 to i32 ; [#uses=2]
455 %81 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
456 %82 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %81, i32 %80) ; [#uses=1]
457 %83 = sub i32 %82, %80 ; [#uses=1]
458 store i32 %83, i32* @ui, align 4
459 %84 = load i8* @uc, align 1 ; [#uses=1]
460 %85 = zext i8 %84 to i32 ; [#uses=2]
461 %86 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
462 %87 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %86, i32 %85) ; [#uses=1]
463 %88 = sub i32 %87, %85 ; [#uses=1]
464 store i32 %88, i32* @sl, align 4
465 %89 = load i8* @uc, align 1 ; [#uses=1]
466 %90 = zext i8 %89 to i32 ; [#uses=2]
467 %91 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
468 %92 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %91, i32 %90) ; [#uses=1]
469 %93 = sub i32 %92, %90 ; [#uses=1]
470 store i32 %93, i32* @ul, align 4
471 %94 = load i8* @uc, align 1 ; [#uses=1]
472 %95 = zext i8 %94 to i64 ; [#uses=2]
473 %96 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
474 %97 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %96, i64 %95) ; [#uses=1]
475 %98 = sub i64 %97, %95 ; [#uses=1]
476 store i64 %98, i64* @sll, align 8
477 %99 = load i8* @uc, align 1 ; [#uses=1]
478 %100 = zext i8 %99 to i64 ; [#uses=2]
479 %101 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
480 %102 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %101, i64 %100) ; [#uses=1]
481 %103 = sub i64 %102, %100 ; [#uses=1]
482 store i64 %103, i64* @ull, align 8
483 %104 = load i8* @uc, align 1 ; [#uses=1]
484 %105 = zext i8 %104 to i32 ; [#uses=1]
485 %106 = trunc i32 %105 to i8 ; [#uses=2]
486 %107 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 %106) ; [#uses=1]
487 %108 = or i8 %107, %106 ; [#uses=1]
488 store i8 %108, i8* @sc, align 1
489 %109 = load i8* @uc, align 1 ; [#uses=1]
490 %110 = zext i8 %109 to i32 ; [#uses=1]
491 %111 = trunc i32 %110 to i8 ; [#uses=2]
492 %112 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 %111) ; [#uses=1]
493 %113 = or i8 %112, %111 ; [#uses=1]
494 store i8 %113, i8* @uc, align 1
495 %114 = load i8* @uc, align 1 ; [#uses=1]
496 %115 = zext i8 %114 to i32 ; [#uses=1]
497 %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
498 %117 = trunc i32 %115 to i16 ; [#uses=2]
499 %118 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %116, i16 %117) ; [#uses=1]
500 %119 = or i16 %118, %117 ; [#uses=1]
501 store i16 %119, i16* @ss, align 2
502 %120 = load i8* @uc, align 1 ; [#uses=1]
503 %121 = zext i8 %120 to i32 ; [#uses=1]
504 %122 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
505 %123 = trunc i32 %121 to i16 ; [#uses=2]
506 %124 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %122, i16 %123) ; [#uses=1]
507 %125 = or i16 %124, %123 ; [#uses=1]
508 store i16 %125, i16* @us, align 2
509 %126 = load i8* @uc, align 1 ; [#uses=1]
510 %127 = zext i8 %126 to i32 ; [#uses=2]
511 %128 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
512 %129 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %128, i32 %127) ; [#uses=1]
513 %130 = or i32 %129, %127 ; [#uses=1]
514 store i32 %130, i32* @si, align 4
515 %131 = load i8* @uc, align 1 ; [#uses=1]
516 %132 = zext i8 %131 to i32 ; [#uses=2]
517 %133 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
518 %134 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %133, i32 %132) ; [#uses=1]
519 %135 = or i32 %134, %132 ; [#uses=1]
520 store i32 %135, i32* @ui, align 4
521 %136 = load i8* @uc, align 1 ; [#uses=1]
522 %137 = zext i8 %136 to i32 ; [#uses=2]
523 %138 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
524 %139 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %138, i32 %137) ; [#uses=1]
525 %140 = or i32 %139, %137 ; [#uses=1]
526 store i32 %140, i32* @sl, align 4
527 %141 = load i8* @uc, align 1 ; [#uses=1]
528 %142 = zext i8 %141 to i32 ; [#uses=2]
529 %143 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
530 %144 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %143, i32 %142) ; [#uses=1]
531 %145 = or i32 %144, %142 ; [#uses=1]
532 store i32 %145, i32* @ul, align 4
533 %146 = load i8* @uc, align 1 ; [#uses=1]
534 %147 = zext i8 %146 to i64 ; [#uses=2]
535 %148 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
536 %149 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %148, i64 %147) ; [#uses=1]
537 %150 = or i64 %149, %147 ; [#uses=1]
538 store i64 %150, i64* @sll, align 8
539 %151 = load i8* @uc, align 1 ; [#uses=1]
540 %152 = zext i8 %151 to i64 ; [#uses=2]
541 %153 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
542 %154 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %153, i64 %152) ; [#uses=1]
543 %155 = or i64 %154, %152 ; [#uses=1]
544 store i64 %155, i64* @ull, align 8
545 %156 = load i8* @uc, align 1 ; [#uses=1]
546 %157 = zext i8 %156 to i32 ; [#uses=1]
547 %158 = trunc i32 %157 to i8 ; [#uses=2]
548 %159 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 %158) ; [#uses=1]
549 %160 = xor i8 %159, %158 ; [#uses=1]
550 store i8 %160, i8* @sc, align 1
551 %161 = load i8* @uc, align 1 ; [#uses=1]
552 %162 = zext i8 %161 to i32 ; [#uses=1]
553 %163 = trunc i32 %162 to i8 ; [#uses=2]
554 %164 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 %163) ; [#uses=1]
555 %165 = xor i8 %164, %163 ; [#uses=1]
556 store i8 %165, i8* @uc, align 1
557 %166 = load i8* @uc, align 1 ; [#uses=1]
558 %167 = zext i8 %166 to i32 ; [#uses=1]
559 %168 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
560 %169 = trunc i32 %167 to i16 ; [#uses=2]
561 %170 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %168, i16 %169) ; [#uses=1]
562 %171 = xor i16 %170, %169 ; [#uses=1]
563 store i16 %171, i16* @ss, align 2
564 %172 = load i8* @uc, align 1 ; [#uses=1]
565 %173 = zext i8 %172 to i32 ; [#uses=1]
566 %174 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
567 %175 = trunc i32 %173 to i16 ; [#uses=2]
568 %176 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %174, i16 %175) ; [#uses=1]
569 %177 = xor i16 %176, %175 ; [#uses=1]
570 store i16 %177, i16* @us, align 2
571 %178 = load i8* @uc, align 1 ; [#uses=1]
572 %179 = zext i8 %178 to i32 ; [#uses=2]
573 %180 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
574 %181 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %180, i32 %179) ; [#uses=1]
575 %182 = xor i32 %181, %179 ; [#uses=1]
576 store i32 %182, i32* @si, align 4
577 %183 = load i8* @uc, align 1 ; [#uses=1]
578 %184 = zext i8 %183 to i32 ; [#uses=2]
579 %185 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
580 %186 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %185, i32 %184) ; [#uses=1]
581 %187 = xor i32 %186, %184 ; [#uses=1]
582 store i32 %187, i32* @ui, align 4
583 %188 = load i8* @uc, align 1 ; [#uses=1]
584 %189 = zext i8 %188 to i32 ; [#uses=2]
585 %190 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
586 %191 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %190, i32 %189) ; [#uses=1]
587 %192 = xor i32 %191, %189 ; [#uses=1]
588 store i32 %192, i32* @sl, align 4
589 %193 = load i8* @uc, align 1 ; [#uses=1]
590 %194 = zext i8 %193 to i32 ; [#uses=2]
591 %195 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
592 %196 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %195, i32 %194) ; [#uses=1]
593 %197 = xor i32 %196, %194 ; [#uses=1]
594 store i32 %197, i32* @ul, align 4
595 %198 = load i8* @uc, align 1 ; [#uses=1]
596 %199 = zext i8 %198 to i64 ; [#uses=2]
597 %200 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
598 %201 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %200, i64 %199) ; [#uses=1]
599 %202 = xor i64 %201, %199 ; [#uses=1]
600 store i64 %202, i64* @sll, align 8
601 %203 = load i8* @uc, align 1 ; [#uses=1]
602 %204 = zext i8 %203 to i64 ; [#uses=2]
603 %205 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
604 %206 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %205, i64 %204) ; [#uses=1]
605 %207 = xor i64 %206, %204 ; [#uses=1]
606 store i64 %207, i64* @ull, align 8
607 %208 = load i8* @uc, align 1 ; [#uses=1]
608 %209 = zext i8 %208 to i32 ; [#uses=1]
609 %210 = trunc i32 %209 to i8 ; [#uses=2]
610 %211 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 %210) ; [#uses=1]
611 %212 = and i8 %211, %210 ; [#uses=1]
612 store i8 %212, i8* @sc, align 1
613 %213 = load i8* @uc, align 1 ; [#uses=1]
614 %214 = zext i8 %213 to i32 ; [#uses=1]
615 %215 = trunc i32 %214 to i8 ; [#uses=2]
616 %216 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 %215) ; [#uses=1]
617 %217 = and i8 %216, %215 ; [#uses=1]
618 store i8 %217, i8* @uc, align 1
619 %218 = load i8* @uc, align 1 ; [#uses=1]
620 %219 = zext i8 %218 to i32 ; [#uses=1]
621 %220 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
622 %221 = trunc i32 %219 to i16 ; [#uses=2]
623 %222 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %220, i16 %221) ; [#uses=1]
624 %223 = and i16 %222, %221 ; [#uses=1]
625 store i16 %223, i16* @ss, align 2
626 %224 = load i8* @uc, align 1 ; [#uses=1]
627 %225 = zext i8 %224 to i32 ; [#uses=1]
628 %226 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
629 %227 = trunc i32 %225 to i16 ; [#uses=2]
630 %228 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %226, i16 %227) ; [#uses=1]
631 %229 = and i16 %228, %227 ; [#uses=1]
632 store i16 %229, i16* @us, align 2
633 %230 = load i8* @uc, align 1 ; [#uses=1]
634 %231 = zext i8 %230 to i32 ; [#uses=2]
635 %232 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
636 %233 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %232, i32 %231) ; [#uses=1]
637 %234 = and i32 %233, %231 ; [#uses=1]
638 store i32 %234, i32* @si, align 4
639 %235 = load i8* @uc, align 1 ; [#uses=1]
640 %236 = zext i8 %235 to i32 ; [#uses=2]
641 %237 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
642 %238 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %237, i32 %236) ; [#uses=1]
643 %239 = and i32 %238, %236 ; [#uses=1]
644 store i32 %239, i32* @ui, align 4
645 %240 = load i8* @uc, align 1 ; [#uses=1]
646 %241 = zext i8 %240 to i32 ; [#uses=2]
647 %242 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
648 %243 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %242, i32 %241) ; [#uses=1]
649 %244 = and i32 %243, %241 ; [#uses=1]
650 store i32 %244, i32* @sl, align 4
651 %245 = load i8* @uc, align 1 ; [#uses=1]
652 %246 = zext i8 %245 to i32 ; [#uses=2]
653 %247 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
654 %248 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %247, i32 %246) ; [#uses=1]
655 %249 = and i32 %248, %246 ; [#uses=1]
656 store i32 %249, i32* @ul, align 4
657 %250 = load i8* @uc, align 1 ; [#uses=1]
658 %251 = zext i8 %250 to i64 ; [#uses=2]
659 %252 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
660 %253 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %252, i64 %251) ; [#uses=1]
661 %254 = and i64 %253, %251 ; [#uses=1]
662 store i64 %254, i64* @sll, align 8
663 %255 = load i8* @uc, align 1 ; [#uses=1]
664 %256 = zext i8 %255 to i64 ; [#uses=2]
665 %257 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
666 %258 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %257, i64 %256) ; [#uses=1]
667 %259 = and i64 %258, %256 ; [#uses=1]
668 store i64 %259, i64* @ull, align 8
669 %260 = load i8* @uc, align 1 ; [#uses=1]
670 %261 = zext i8 %260 to i32 ; [#uses=1]
671 %262 = trunc i32 %261 to i8 ; [#uses=2]
672 %263 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 %262) ; [#uses=1]
673 %264 = xor i8 %263, -1 ; [#uses=1]
674 %265 = and i8 %264, %262 ; [#uses=1]
675 store i8 %265, i8* @sc, align 1
676 %266 = load i8* @uc, align 1 ; [#uses=1]
677 %267 = zext i8 %266 to i32 ; [#uses=1]
678 %268 = trunc i32 %267 to i8 ; [#uses=2]
679 %269 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 %268) ; [#uses=1]
680 %270 = xor i8 %269, -1 ; [#uses=1]
681 %271 = and i8 %270, %268 ; [#uses=1]
682 store i8 %271, i8* @uc, align 1
683 %272 = load i8* @uc, align 1 ; [#uses=1]
684 %273 = zext i8 %272 to i32 ; [#uses=1]
685 %274 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
686 %275 = trunc i32 %273 to i16 ; [#uses=2]
687 %276 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %274, i16 %275) ; [#uses=1]
688 %277 = xor i16 %276, -1 ; [#uses=1]
689 %278 = and i16 %277, %275 ; [#uses=1]
690 store i16 %278, i16* @ss, align 2
691 %279 = load i8* @uc, align 1 ; [#uses=1]
692 %280 = zext i8 %279 to i32 ; [#uses=1]
693 %281 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
694 %282 = trunc i32 %280 to i16 ; [#uses=2]
695 %283 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %281, i16 %282) ; [#uses=1]
696 %284 = xor i16 %283, -1 ; [#uses=1]
697 %285 = and i16 %284, %282 ; [#uses=1]
698 store i16 %285, i16* @us, align 2
699 %286 = load i8* @uc, align 1 ; [#uses=1]
700 %287 = zext i8 %286 to i32 ; [#uses=2]
701 %288 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
702 %289 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %288, i32 %287) ; [#uses=1]
703 %290 = xor i32 %289, -1 ; [#uses=1]
704 %291 = and i32 %290, %287 ; [#uses=1]
705 store i32 %291, i32* @si, align 4
706 %292 = load i8* @uc, align 1 ; [#uses=1]
707 %293 = zext i8 %292 to i32 ; [#uses=2]
708 %294 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
709 %295 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %294, i32 %293) ; [#uses=1]
710 %296 = xor i32 %295, -1 ; [#uses=1]
711 %297 = and i32 %296, %293 ; [#uses=1]
712 store i32 %297, i32* @ui, align 4
713 %298 = load i8* @uc, align 1 ; [#uses=1]
714 %299 = zext i8 %298 to i32 ; [#uses=2]
715 %300 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
716 %301 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %300, i32 %299) ; [#uses=1]
717 %302 = xor i32 %301, -1 ; [#uses=1]
718 %303 = and i32 %302, %299 ; [#uses=1]
719 store i32 %303, i32* @sl, align 4
720 %304 = load i8* @uc, align 1 ; [#uses=1]
721 %305 = zext i8 %304 to i32 ; [#uses=2]
722 %306 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
723 %307 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %306, i32 %305) ; [#uses=1]
724 %308 = xor i32 %307, -1 ; [#uses=1]
725 %309 = and i32 %308, %305 ; [#uses=1]
726 store i32 %309, i32* @ul, align 4
727 %310 = load i8* @uc, align 1 ; [#uses=1]
728 %311 = zext i8 %310 to i64 ; [#uses=2]
729 %312 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
730 %313 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %312, i64 %311) ; [#uses=1]
731 %314 = xor i64 %313, -1 ; [#uses=1]
732 %315 = and i64 %314, %311 ; [#uses=1]
733 store i64 %315, i64* @sll, align 8
734 %316 = load i8* @uc, align 1 ; [#uses=1]
735 %317 = zext i8 %316 to i64 ; [#uses=2]
736 %318 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
737 %319 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %318, i64 %317) ; [#uses=1]
738 %320 = xor i64 %319, -1 ; [#uses=1]
739 %321 = and i64 %320, %317 ; [#uses=1]
740 store i64 %321, i64* @ull, align 8
741 br label %return
742
743 return: ; preds = %entry
744 ret void
745 }
746
747 define void @test_compare_and_swap() nounwind {
748 entry:
749 %0 = load i8* @sc, align 1 ; [#uses=1]
750 %1 = zext i8 %0 to i32 ; [#uses=1]
751 %2 = load i8* @uc, align 1 ; [#uses=1]
752 %3 = zext i8 %2 to i32 ; [#uses=1]
753 %4 = trunc i32 %3 to i8 ; [#uses=1]
754 %5 = trunc i32 %1 to i8 ; [#uses=1]
755 %6 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @sc, i8 %4, i8 %5) ; [#uses=1]
756 store i8 %6, i8* @sc, align 1
757 %7 = load i8* @sc, align 1 ; [#uses=1]
758 %8 = zext i8 %7 to i32 ; [#uses=1]
759 %9 = load i8* @uc, align 1 ; [#uses=1]
760 %10 = zext i8 %9 to i32 ; [#uses=1]
761 %11 = trunc i32 %10 to i8 ; [#uses=1]
762 %12 = trunc i32 %8 to i8 ; [#uses=1]
763 %13 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @uc, i8 %11, i8 %12) ; [#uses=1]
764 store i8 %13, i8* @uc, align 1
765 %14 = load i8* @sc, align 1 ; [#uses=1]
766 %15 = sext i8 %14 to i16 ; [#uses=1]
767 %16 = zext i16 %15 to i32 ; [#uses=1]
768 %17 = load i8* @uc, align 1 ; [#uses=1]
769 %18 = zext i8 %17 to i32 ; [#uses=1]
770 %19 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
771 %20 = trunc i32 %18 to i16 ; [#uses=1]
772 %21 = trunc i32 %16 to i16 ; [#uses=1]
773 %22 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %19, i16 %20, i16 %21) ; [#uses=1]
774 store i16 %22, i16* @ss, align 2
775 %23 = load i8* @sc, align 1 ; [#uses=1]
776 %24 = sext i8 %23 to i16 ; [#uses=1]
777 %25 = zext i16 %24 to i32 ; [#uses=1]
778 %26 = load i8* @uc, align 1 ; [#uses=1]
779 %27 = zext i8 %26 to i32 ; [#uses=1]
780 %28 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
781 %29 = trunc i32 %27 to i16 ; [#uses=1]
782 %30 = trunc i32 %25 to i16 ; [#uses=1]
783 %31 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %28, i16 %29, i16 %30) ; [#uses=1]
784 store i16 %31, i16* @us, align 2
785 %32 = load i8* @sc, align 1 ; [#uses=1]
786 %33 = sext i8 %32 to i32 ; [#uses=1]
787 %34 = load i8* @uc, align 1 ; [#uses=1]
788 %35 = zext i8 %34 to i32 ; [#uses=1]
789 %36 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
790 %37 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %36, i32 %35, i32 %33) ; [#uses=1]
791 store i32 %37, i32* @si, align 4
792 %38 = load i8* @sc, align 1 ; [#uses=1]
793 %39 = sext i8 %38 to i32 ; [#uses=1]
794 %40 = load i8* @uc, align 1 ; [#uses=1]
795 %41 = zext i8 %40 to i32 ; [#uses=1]
796 %42 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
797 %43 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %42, i32 %41, i32 %39) ; [#uses=1]
798 store i32 %43, i32* @ui, align 4
799 %44 = load i8* @sc, align 1 ; [#uses=1]
800 %45 = sext i8 %44 to i32 ; [#uses=1]
801 %46 = load i8* @uc, align 1 ; [#uses=1]
802 %47 = zext i8 %46 to i32 ; [#uses=1]
803 %48 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
804 %49 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %48, i32 %47, i32 %45) ; [#uses=1]
805 store i32 %49, i32* @sl, align 4
806 %50 = load i8* @sc, align 1 ; [#uses=1]
807 %51 = sext i8 %50 to i32 ; [#uses=1]
808 %52 = load i8* @uc, align 1 ; [#uses=1]
809 %53 = zext i8 %52 to i32 ; [#uses=1]
810 %54 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
811 %55 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %54, i32 %53, i32 %51) ; [#uses=1]
812 store i32 %55, i32* @ul, align 4
813 %56 = load i8* @sc, align 1 ; [#uses=1]
814 %57 = zext i8 %56 to i32 ; [#uses=1]
815 %58 = load i8* @uc, align 1 ; [#uses=1]
816 %59 = zext i8 %58 to i32 ; [#uses=1]
817 %60 = trunc i32 %59 to i8 ; [#uses=2]
818 %61 = trunc i32 %57 to i8 ; [#uses=1]
819 %62 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @sc, i8 %60, i8 %61) ; [#uses=1]
820 %63 = icmp eq i8 %62, %60 ; [#uses=1]
821 %64 = zext i1 %63 to i8 ; [#uses=1]
822 %65 = zext i8 %64 to i32 ; [#uses=1]
823 store i32 %65, i32* @ui, align 4
824 %66 = load i8* @sc, align 1 ; [#uses=1]
825 %67 = zext i8 %66 to i32 ; [#uses=1]
826 %68 = load i8* @uc, align 1 ; [#uses=1]
827 %69 = zext i8 %68 to i32 ; [#uses=1]
828 %70 = trunc i32 %69 to i8 ; [#uses=2]
829 %71 = trunc i32 %67 to i8 ; [#uses=1]
830 %72 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @uc, i8 %70, i8 %71) ; [#uses=1]
831 %73 = icmp eq i8 %72, %70 ; [#uses=1]
832 %74 = zext i1 %73 to i8 ; [#uses=1]
833 %75 = zext i8 %74 to i32 ; [#uses=1]
834 store i32 %75, i32* @ui, align 4
835 %76 = load i8* @sc, align 1 ; [#uses=1]
836 %77 = sext i8 %76 to i16 ; [#uses=1]
837 %78 = zext i16 %77 to i32 ; [#uses=1]
838 %79 = load i8* @uc, align 1 ; [#uses=1]
839 %80 = zext i8 %79 to i32 ; [#uses=1]
840 %81 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
841 %82 = trunc i32 %80 to i16 ; [#uses=2]
842 %83 = trunc i32 %78 to i16 ; [#uses=1]
843 %84 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %81, i16 %82, i16 %83) ; [#uses=1]
844 %85 = icmp eq i16 %84, %82 ; [#uses=1]
845 %86 = zext i1 %85 to i8 ; [#uses=1]
846 %87 = zext i8 %86 to i32 ; [#uses=1]
847 store i32 %87, i32* @ui, align 4
848 %88 = load i8* @sc, align 1 ; [#uses=1]
849 %89 = sext i8 %88 to i16 ; [#uses=1]
850 %90 = zext i16 %89 to i32 ; [#uses=1]
851 %91 = load i8* @uc, align 1 ; [#uses=1]
852 %92 = zext i8 %91 to i32 ; [#uses=1]
853 %93 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
854 %94 = trunc i32 %92 to i16 ; [#uses=2]
855 %95 = trunc i32 %90 to i16 ; [#uses=1]
856 %96 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %93, i16 %94, i16 %95) ; [#uses=1]
857 %97 = icmp eq i16 %96, %94 ; [#uses=1]
858 %98 = zext i1 %97 to i8 ; [#uses=1]
859 %99 = zext i8 %98 to i32 ; [#uses=1]
860 store i32 %99, i32* @ui, align 4
861 %100 = load i8* @sc, align 1 ; [#uses=1]
862 %101 = sext i8 %100 to i32 ; [#uses=1]
863 %102 = load i8* @uc, align 1 ; [#uses=1]
864 %103 = zext i8 %102 to i32 ; [#uses=2]
865 %104 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
866 %105 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %104, i32 %103, i32 %101) ; [#uses=1]
867 %106 = icmp eq i32 %105, %103 ; [#uses=1]
868 %107 = zext i1 %106 to i8 ; [#uses=1]
869 %108 = zext i8 %107 to i32 ; [#uses=1]
870 store i32 %108, i32* @ui, align 4
871 %109 = load i8* @sc, align 1 ; [#uses=1]
872 %110 = sext i8 %109 to i32 ; [#uses=1]
873 %111 = load i8* @uc, align 1 ; [#uses=1]
874 %112 = zext i8 %111 to i32 ; [#uses=2]
875 %113 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
876 %114 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %113, i32 %112, i32 %110) ; [#uses=1]
877 %115 = icmp eq i32 %114, %112 ; [#uses=1]
878 %116 = zext i1 %115 to i8 ; [#uses=1]
879 %117 = zext i8 %116 to i32 ; [#uses=1]
880 store i32 %117, i32* @ui, align 4
881 %118 = load i8* @sc, align 1 ; [#uses=1]
882 %119 = sext i8 %118 to i32 ; [#uses=1]
883 %120 = load i8* @uc, align 1 ; [#uses=1]
884 %121 = zext i8 %120 to i32 ; [#uses=2]
885 %122 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
886 %123 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %122, i32 %121, i32 %119) ; [#uses=1]
887 %124 = icmp eq i32 %123, %121 ; [#uses=1]
888 %125 = zext i1 %124 to i8 ; [#uses=1]
889 %126 = zext i8 %125 to i32 ; [#uses=1]
890 store i32 %126, i32* @ui, align 4
891 %127 = load i8* @sc, align 1 ; [#uses=1]
892 %128 = sext i8 %127 to i32 ; [#uses=1]
893 %129 = load i8* @uc, align 1 ; [#uses=1]
894 %130 = zext i8 %129 to i32 ; [#uses=2]
895 %131 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
896 %132 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %131, i32 %130, i32 %128) ; [#uses=1]
897 %133 = icmp eq i32 %132, %130 ; [#uses=1]
898 %134 = zext i1 %133 to i8 ; [#uses=1]
899 %135 = zext i8 %134 to i32 ; [#uses=1]
900 store i32 %135, i32* @ui, align 4
901 br label %return
902
903 return: ; preds = %entry
904 ret void
905 }
906
907 declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind
908
909 declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind
910
911 declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
912
913 define void @test_lock() nounwind {
914 entry:
915 %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @sc, i8 1) ; [#uses=1]
916 store i8 %0, i8* @sc, align 1
917 %1 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @uc, i8 1) ; [#uses=1]
918 store i8 %1, i8* @uc, align 1
919 %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
920 %3 = call i16 @llvm.atomic.swap.i16.p0i16(i16* %2, i16 1) ; [#uses=1]
921 store i16 %3, i16* @ss, align 2
922 %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
923 %5 = call i16 @llvm.atomic.swap.i16.p0i16(i16* %4, i16 1) ; [#uses=1]
924 store i16 %5, i16* @us, align 2
925 %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
926 %7 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %6, i32 1) ; [#uses=1]
927 store i32 %7, i32* @si, align 4
928 %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
929 %9 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %8, i32 1) ; [#uses=1]
930 store i32 %9, i32* @ui, align 4
931 %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
932 %11 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %10, i32 1) ; [#uses=1]
933 store i32 %11, i32* @sl, align 4
934 %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
935 %13 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %12, i32 1) ; [#uses=1]
936 store i32 %13, i32* @ul, align 4
937 call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
938 volatile store i8 0, i8* @sc, align 1
939 volatile store i8 0, i8* @uc, align 1
940 %14 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1]
941 volatile store i16 0, i16* %14, align 2
942 %15 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1]
943 volatile store i16 0, i16* %15, align 2
944 %16 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1]
945 volatile store i32 0, i32* %16, align 4
946 %17 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1]
947 volatile store i32 0, i32* %17, align 4
948 %18 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1]
949 volatile store i32 0, i32* %18, align 4
950 %19 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1]
951 volatile store i32 0, i32* %19, align 4
952 %20 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1]
953 volatile store i64 0, i64* %20, align 8
954 %21 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1]
955 volatile store i64 0, i64* %21, align 8
956 br label %return
957
958 return: ; preds = %entry
959 ret void
960 }
961
962 declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind
963
964 declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind
965
966 declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
967
968 declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
2020 // FIXME: Only supports TIED_TO for now.
2121 std::string::size_type pos = CStr.find_first_of('=');
2222 assert(pos != std::string::npos && "Unrecognized constraint");
23 std::string Name = CStr.substr(0, pos);
23 std::string::size_type start = CStr.find_first_not_of(" \t");
24 std::string Name = CStr.substr(start, pos);
2425
2526 // TIED_TO: $src1 = $dst
2627 std::string::size_type wpos = Name.find_first_of(" \t");