llvm.org GIT mirror llvm / 48a473e
[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247110 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 5 years ago
4 changed file(s) with 64 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
268268 OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
269269 }
270270
271 OS << '(' << OpcodeName(TII, MI);
272 for (const MachineOperand &MO : MI->uses())
273 switch (MO.getType()) {
274 default:
275 llvm_unreachable("unexpected machine operand type");
276 case MachineOperand::MO_Register: {
277 if (MO.isImplicit())
278 continue;
279 unsigned Reg = MO.getReg();
280 OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
281 } break;
282 case MachineOperand::MO_Immediate: {
283 OS << ' ' << MO.getImm();
284 } break;
285 case MachineOperand::MO_FPImmediate: {
286 OS << ' ' << toString(MO.getFPImm()->getValueAPF());
287 } break;
288 case MachineOperand::MO_GlobalAddress: {
289 OS << ' ' << toSymbol(MO.getGlobal()->getName());
290 } break;
291 }
292 OS << ')';
271 if (MI->getOpcode() == WebAssembly::COPY) {
272 OS << '@' << TargetRegisterInfo::virtReg2Index(MI->getOperand(1).getReg());
273 } else {
274 OS << '(' << OpcodeName(TII, MI);
275 for (const MachineOperand &MO : MI->uses())
276 switch (MO.getType()) {
277 default:
278 llvm_unreachable("unexpected machine operand type");
279 case MachineOperand::MO_Register: {
280 if (MO.isImplicit())
281 continue;
282 unsigned Reg = MO.getReg();
283 OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
284 } break;
285 case MachineOperand::MO_Immediate: {
286 OS << ' ' << MO.getImm();
287 } break;
288 case MachineOperand::MO_FPImmediate: {
289 OS << ' ' << toString(MO.getFPImm()->getValueAPF());
290 } break;
291 case MachineOperand::MO_GlobalAddress: {
292 OS << ' ' << toSymbol(MO.getGlobal()->getName());
293 } break;
294 }
295 OS << ')';
296 }
293297
294298 if (NumDefs != 0)
295299 OS << ')';
2828
2929 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
3030 : RI(STI.getTargetTriple()) {}
31
32 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator I,
34 DebugLoc DL, unsigned DestReg,
35 unsigned SrcReg, bool KillSrc) const {
36 BuildMI(MBB, I, DL, get(WebAssembly::COPY), DestReg)
37 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
38 }
3232 explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
3333
3434 const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
35
36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
37 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
38 bool KillSrc) const override;
3539 };
3640
3741 } // end namespace llvm
66
77 target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
88 target triple = "wasm32-unknown-unknown"
9
10 ; Basic phi triangle.
911
1012 ; CHECK-LABEL: test0
1113 ; CHECK: (setlocal [[REG:@.*]] (argument 0))
2224 %s = phi i32 [ %a, %true ], [ %p, %entry ]
2325 ret i32 %s
2426 }
27
28 ; Swap phis.
29
30 ; CHECK-LABEL: test1
31 ; CHECK: BB0_1:
32 ; CHECK: (setlocal [[REG0:@.*]] [[REG1:@.*]])
33 ; CHECK: (setlocal [[REG1]] [[REG2:@.*]])
34 ; CHECK: (setlocal [[REG2]] [[REG0]])
35 define i32 @test1(i32 %n) {
36 entry:
37 br label %loop
38
39 loop:
40 %a = phi i32 [ 0, %entry ], [ %b, %loop ]
41 %b = phi i32 [ 1, %entry ], [ %a, %loop ]
42 %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
43
44 %i.next = add i32 %i, 1
45 %t = icmp slt i32 %i.next, %n
46 br i1 %t, label %loop, label %exit
47
48 exit:
49 ret i32 %a
50 }