llvm.org GIT mirror llvm / 48872e0
Pass to verify generated machine code. The following is checked: * Operand counts: All explicit operands must be present. * Register classes: All physical and virtual register operands must be compatible with the register class required by the instruction descriptor. * Register live intervals: Registers must be defined only once, and must be defined before use. The machine code verifier is enabled with the command-line option '-verify-machineinstrs', or by defining the environment variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive all the verifier errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71918 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 11 years ago
4 changed file(s) with 711 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
195195 /// createStackProtectorPass - This pass adds stack protectors to functions.
196196 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
197197
198 /// createMachineVerifierPass - This pass verifies cenerated machine code
199 /// instructions for correctness.
200 ///
201 /// @param allowPhysDoubleDefs ignore double definitions of
202 /// registers. Useful before LiveVariables has run.
203 FunctionPass *createMachineVerifierPass(bool allowDoubleDefs);
204
198205 } // End llvm namespace
199206
200207 #endif
2525 MachinePassRegistry.cpp
2626 MachineRegisterInfo.cpp
2727 MachineSink.cpp
28 MachineVerifier.cpp
2829 OcamlGC.cpp
2930 PBQP.cpp
3031 PHIElimination.cpp
3636 cl::desc("Dump emitter generated instructions as assembly"));
3737 static cl::opt PrintGCInfo("print-gc", cl::Hidden,
3838 cl::desc("Dump garbage collector data"));
39 static cl::opt VerifyMachineCode("verify-machineinstrs", cl::Hidden,
40 cl::desc("Verify generated machine code"),
41 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
3942
4043 // When this works it will be on by default.
4144 static cl::opt
131134 return false; // success!
132135 }
133136
137 static void printAndVerify(PassManagerBase &PM,
138 bool allowDoubleDefs = false) {
139 if (PrintMachineCode)
140 PM.add(createMachineFunctionPrinterPass(cerr));
141
142 if (VerifyMachineCode)
143 PM.add(createMachineVerifierPass(allowDoubleDefs));
144 }
145
134146 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
135147 /// emitting to assembly files or machine code output.
136148 ///
175187 return true;
176188
177189 // Print the instruction selected machine code...
178 if (PrintMachineCode)
179 PM.add(createMachineFunctionPrinterPass(cerr));
190 printAndVerify(PM, /* allowDoubleDefs= */ true);
180191
181192 if (OptLevel != CodeGenOpt::None) {
182193 PM.add(createMachineLICMPass());
183194 PM.add(createMachineSinkingPass());
195 printAndVerify(PM, /* allowDoubleDefs= */ true);
184196 }
185197
186198 // Run pre-ra passes.
187 if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
188 PM.add(createMachineFunctionPrinterPass(cerr));
199 if (addPreRegAlloc(PM, OptLevel))
200 printAndVerify(PM);
189201
190202 // Perform register allocation.
191203 PM.add(createRegisterAllocator());
194206 if (OptLevel != CodeGenOpt::None)
195207 PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
196208
197 if (PrintMachineCode) // Print the register-allocated code
198 PM.add(createMachineFunctionPrinterPass(cerr));
209 printAndVerify(PM); // Print the register-allocated code
199210
200211 // Run post-ra passes.
201 if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
202 PM.add(createMachineFunctionPrinterPass(cerr));
203
204 if (PrintMachineCode)
205 PM.add(createMachineFunctionPrinterPass(cerr));
212 if (addPostRegAlloc(PM, OptLevel))
213 printAndVerify(PM);
206214
207215 PM.add(createLowerSubregsPass());
208
209 if (PrintMachineCode) // Print the subreg lowered code
210 PM.add(createMachineFunctionPrinterPass(cerr));
216 printAndVerify(PM);
211217
212218 // Insert prolog/epilog code. Eliminate abstract frame index references...
213219 PM.add(createPrologEpilogCodeInserter());
214
215 if (PrintMachineCode)
216 PM.add(createMachineFunctionPrinterPass(cerr));
220 printAndVerify(PM);
217221
218222 // Second pass scheduler.
219223 if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
220224 PM.add(createPostRAScheduler());
221
222 if (PrintMachineCode)
223 PM.add(createMachineFunctionPrinterPass(cerr));
225 printAndVerify(PM);
224226 }
225227
226228 // Branch folding must be run after regalloc and prolog/epilog insertion.
227 if (OptLevel != CodeGenOpt::None)
229 if (OptLevel != CodeGenOpt::None) {
228230 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
229
230 if (PrintMachineCode)
231 PM.add(createMachineFunctionPrinterPass(cerr));
231 printAndVerify(PM);
232 }
232233
233234 PM.add(createGCMachineCodeAnalysisPass());
234
235 if (PrintMachineCode)
236 PM.add(createMachineFunctionPrinterPass(cerr));
235 printAndVerify(PM);
237236
238237 if (PrintGCInfo)
239238 PM.add(createGCInfoPrinter(*cerr));
0 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20 // command-line option -verify-machineinstrs, or by defining the environment
21 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22 // the verifier errors.
23 //===----------------------------------------------------------------------===//
24
25 #include "llvm/ADT/DenseSet.h"
26 #include "llvm/ADT/SetOperations.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/Function.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include
39
40 using namespace llvm;
41
42 namespace {
43 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
44 static char ID; // Pass ID, replacement for typeid
45
46 MachineVerifier(bool allowDoubleDefs = false) :
47 MachineFunctionPass(&ID),
48 allowVirtDoubleDefs(allowDoubleDefs),
49 allowPhysDoubleDefs(allowDoubleDefs),
50 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
51 {}
52
53 void getAnalysisUsage(AnalysisUsage &AU) const {
54 AU.setPreservesAll();
55 }
56
57 bool runOnMachineFunction(MachineFunction &MF);
58
59 const bool allowVirtDoubleDefs;
60 const bool allowPhysDoubleDefs;
61
62 const char *const OutFileName;
63 std::ostream *OS;
64 const MachineFunction *MF;
65 const TargetMachine *TM;
66 const TargetRegisterInfo *TRI;
67 const MachineRegisterInfo *MRI;
68
69 unsigned foundErrors;
70
71 typedef SmallVector RegVector;
72 typedef DenseSet RegSet;
73 typedef DenseMap RegMap;
74
75 BitVector regsReserved;
76 RegSet regsLive;
77 RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
78
79 // Add Reg and any sub-registers to RV
80 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
81 RV.push_back(Reg);
82 if (TargetRegisterInfo::isPhysicalRegister(Reg))
83 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
84 RV.push_back(*R);
85 }
86
87 // Does RS contain any super-registers of Reg?
88 bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
89 for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
90 if (RS.count(*R))
91 return true;
92 return false;
93 }
94
95 struct BBInfo {
96 // Is this MBB reachable from the MF entry point?
97 bool reachable;
98
99 // Vregs that must be live in because they are used without being
100 // defined. Map value is the user.
101 RegMap vregsLiveIn;
102
103 // Vregs that must be dead in because they are defined without being
104 // killed first. Map value is the defining instruction.
105 RegMap vregsDeadIn;
106
107 // Regs killed in MBB. They may be defined again, and will then be in both
108 // regsKilled and regsLiveOut.
109 RegSet regsKilled;
110
111 // Regs defined in MBB and live out. Note that vregs passing through may
112 // be live out without being mentioned here.
113 RegSet regsLiveOut;
114
115 // Vregs that pass through MBB untouched. This set is disjoint from
116 // regsKilled and regsLiveOut.
117 RegSet vregsPassed;
118
119 BBInfo() : reachable(false) {}
120
121 // Add register to vregsPassed if it belongs there. Return true if
122 // anything changed.
123 bool addPassed(unsigned Reg) {
124 if (!TargetRegisterInfo::isVirtualRegister(Reg))
125 return false;
126 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
127 return false;
128 return vregsPassed.insert(Reg).second;
129 }
130
131 // Same for a full set.
132 bool addPassed(const RegSet &RS) {
133 bool changed = false;
134 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
135 if (addPassed(*I))
136 changed = true;
137 return changed;
138 }
139
140 // Live-out registers are either in regsLiveOut or vregsPassed.
141 bool isLiveOut(unsigned Reg) const {
142 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
143 }
144 };
145
146 // Extra register info per MBB.
147 DenseMap MBBInfoMap;
148
149 bool isReserved(unsigned Reg) {
150 return Reg < regsReserved.size() && regsReserved[Reg];
151 }
152
153 void visitMachineFunctionBefore();
154 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
155 void visitMachineInstrBefore(const MachineInstr *MI);
156 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
157 void visitMachineInstrAfter(const MachineInstr *MI);
158 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
159 void visitMachineFunctionAfter();
160
161 void report(const char *msg, const MachineFunction *MF);
162 void report(const char *msg, const MachineBasicBlock *MBB);
163 void report(const char *msg, const MachineInstr *MI);
164 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
165
166 void markReachable(const MachineBasicBlock *MBB);
167 void calcMaxRegsPassed();
168 void calcMinRegsPassed();
169 void checkPHIOps(const MachineBasicBlock *MBB);
170 };
171 }
172
173 char MachineVerifier::ID = 0;
174 static RegisterPass
175 MachineVer("verify-machineinstrs", "Verify generated machine code");
176 static const PassInfo *const MachineVerifyID = &MachineVer;
177
178 FunctionPass *
179 llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
180 {
181 return new MachineVerifier(allowPhysDoubleDefs);
182 }
183
184 bool
185 MachineVerifier::runOnMachineFunction(MachineFunction &MF)
186 {
187 std::ofstream OutFile;
188 if (OutFileName) {
189 OutFile.open(OutFileName, std::ios::out | std::ios::app);
190 OS = &OutFile;
191 } else {
192 OS = cerr.stream();
193 }
194
195 foundErrors = 0;
196
197 this->MF = &MF;
198 TM = &MF.getTarget();
199 TRI = TM->getRegisterInfo();
200 MRI = &MF.getRegInfo();
201
202 visitMachineFunctionBefore();
203 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
204 MFI!=MFE; ++MFI) {
205 visitMachineBasicBlockBefore(MFI);
206 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
207 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
208 visitMachineInstrBefore(MBBI);
209 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
210 visitMachineOperand(&MBBI->getOperand(I), I);
211 visitMachineInstrAfter(MBBI);
212 }
213 visitMachineBasicBlockAfter(MFI);
214 }
215 visitMachineFunctionAfter();
216
217 if (OutFileName)
218 OutFile.close();
219
220 if (foundErrors) {
221 cerr << "\nStopping with " << foundErrors << " machine code errors.\n";
222 exit(1);
223 }
224
225 return false; // no changes
226 }
227
228 void
229 MachineVerifier::report(const char *msg, const MachineFunction *MF)
230 {
231 assert(MF);
232 *OS << "\n";
233 if (!foundErrors++)
234 MF->print(OS);
235 *OS << "*** Bad machine code: " << msg << " ***\n"
236 << "- function: " << MF->getFunction()->getName() << "\n";
237 }
238
239 void
240 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
241 {
242 assert(MBB);
243 report(msg, MBB->getParent());
244 *OS << "- basic block: " << MBB->getBasicBlock()->getName()
245 << " " << (void*)MBB
246 << " (#" << MBB->getNumber() << ")\n";
247 }
248
249 void
250 MachineVerifier::report(const char *msg, const MachineInstr *MI)
251 {
252 assert(MI);
253 report(msg, MI->getParent());
254 *OS << "- instruction: ";
255 MI->print(OS, TM);
256 }
257
258 void
259 MachineVerifier::report(const char *msg,
260 const MachineOperand *MO, unsigned MONum)
261 {
262 assert(MO);
263 report(msg, MO->getParent());
264 *OS << "- operand " << MONum << ": ";
265 MO->print(*OS, TM);
266 *OS << "\n";
267 }
268
269 void
270 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
271 {
272 BBInfo &MInfo = MBBInfoMap[MBB];
273 if (!MInfo.reachable) {
274 MInfo.reachable = true;
275 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
276 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
277 markReachable(*SuI);
278 }
279 }
280
281 void
282 MachineVerifier::visitMachineFunctionBefore()
283 {
284 regsReserved = TRI->getReservedRegs(*MF);
285 markReachable(&MF->front());
286 }
287
288 void
289 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
290 {
291 regsLive.clear();
292 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
293 E = MBB->livein_end(); I != E; ++I) {
294 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
295 report("MBB live-in list contains non-physical register", MBB);
296 continue;
297 }
298 regsLive.insert(*I);
299 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
300 regsLive.insert(*R);
301 }
302 regsKilled.clear();
303 regsDefined.clear();
304 regsImpDefined.clear();
305 }
306
307 void
308 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
309 {
310 const TargetInstrDesc &TI = MI->getDesc();
311 if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
312 report("Too few operands", MI);
313 *OS << TI.getNumOperands() << " operands expected, but "
314 << MI->getNumExplicitOperands() << " given.\n";
315 }
316 if (!TI.isVariadic()) {
317 if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
318 report("Too many operands", MI);
319 *OS << TI.getNumOperands() << " operands expected, but "
320 << MI->getNumExplicitOperands() << " given.\n";
321 }
322 }
323 }
324
325 void
326 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
327 {
328 const MachineInstr *MI = MO->getParent();
329 switch (MO->getType()) {
330 case MachineOperand::MO_Register: {
331 const unsigned Reg = MO->getReg();
332 if (!Reg)
333 return;
334
335 // Check Live Variables.
336 if (MO->isUse()) {
337 if (MO->isKill()) {
338 addRegWithSubRegs(regsKilled, Reg);
339 } else {
340 // TwoAddress instr modyfying a reg is treated as kill+def.
341 unsigned defIdx;
342 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
343 MI->getOperand(defIdx).getReg() == Reg)
344 addRegWithSubRegs(regsKilled, Reg);
345 }
346 // Explicit use of a dead register.
347 if (!MO->isImplicit() && !regsLive.count(Reg))
348 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
349 // Reserved registers may be used even when 'dead'.
350 if (!isReserved(Reg))
351 report("Using an undefined physical register", MO, MONum);
352 } else {
353 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
354 // We don't know which virtual registers are live in, so only complain
355 // if vreg was killed in this MBB. Otherwise keep track of vregs that
356 // must be live in. PHI instructions are handled separately.
357 if (MInfo.regsKilled.count(Reg))
358 report("Using a killed virtual register", MO, MONum);
359 else if (MI->getOpcode() != TargetInstrInfo::PHI)
360 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
361 }
362 } else {
363 // Register defined.
364 // TODO: verify that earlyclobber ops are not used.
365 if (MO->isImplicit())
366 addRegWithSubRegs(regsImpDefined, Reg);
367 else
368 addRegWithSubRegs(regsDefined, Reg);
369
370 if (MO->isDead())
371 addRegWithSubRegs(regsDead, Reg);
372 }
373
374 // Check register classes.
375 const TargetInstrDesc &TI = MI->getDesc();
376 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
377 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
378 unsigned SubIdx = MO->getSubReg();
379
380 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
381 unsigned sr = Reg;
382 if (SubIdx) {
383 unsigned s = TRI->getSubReg(Reg, SubIdx);
384 if (!s) {
385 report("Invalid subregister index for physical register",
386 MO, MONum);
387 return;
388 }
389 sr = s;
390 }
391 if (TOI.RegClass) {
392 const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
393 if (!DRC->contains(sr)) {
394 report("Illegal physical register for instruction", MO, MONum);
395 *OS << TRI->getName(sr) << " is not a "
396 << DRC->getName() << " register.\n";
397 }
398 }
399 } else {
400 // Virtual register.
401 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
402 if (SubIdx) {
403 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
404 report("Invalid subregister index for virtual register", MO, MONum);
405 return;
406 }
407 RC = *(RC->subregclasses_begin()+SubIdx);
408 }
409 if (TOI.RegClass) {
410 const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
411 if (RC != DRC && !RC->hasSuperClass(DRC)) {
412 report("Illegal virtual register for instruction", MO, MONum);
413 *OS << "Expected a " << DRC->getName() << " register, but got a "
414 << RC->getName() << " register\n";
415 }
416 }
417 }
418 }
419 break;
420 }
421 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
422 // case MachineOperand::MO_MachineBasicBlock:
423 // if (MI->getOpcode() == TargetInstrInfo::PHI) {
424 // if (!MO->getMBB()->isSuccessor(MI->getParent()))
425 // report("PHI operand is not in the CFG", MO, MONum);
426 // }
427 // break;
428 default:
429 break;
430 }
431 }
432
433 void
434 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
435 {
436 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
437 set_union(MInfo.regsKilled, regsKilled);
438 set_subtract(regsLive, regsKilled);
439 regsKilled.clear();
440
441 for (RegVector::const_iterator I = regsDefined.begin(),
442 E = regsDefined.end(); I != E; ++I) {
443 if (regsLive.count(*I)) {
444 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
445 // We allow double defines to physical registers with live
446 // super-registers.
447 if (!allowPhysDoubleDefs && !anySuperRegisters(regsLive, *I)) {
448 report("Redefining a live physical register", MI);
449 *OS << "Register " << TRI->getName(*I)
450 << " was defined but already live.\n";
451 }
452 } else {
453 if (!allowVirtDoubleDefs) {
454 report("Redefining a live virtual register", MI);
455 *OS << "Virtual register %reg" << *I
456 << " was defined but already live.\n";
457 }
458 }
459 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
460 !MInfo.regsKilled.count(*I)) {
461 // Virtual register defined without being killed first must be dead on
462 // entry.
463 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
464 }
465 }
466
467 set_union(regsLive, regsDefined); regsDefined.clear();
468 set_union(regsLive, regsImpDefined); regsImpDefined.clear();
469 set_subtract(regsLive, regsDead); regsDead.clear();
470 }
471
472 void
473 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
474 {
475 MBBInfoMap[MBB].regsLiveOut = regsLive;
476 regsLive.clear();
477 }
478
479 // Calculate the largest possible vregsPassed sets. These are the registers that
480 // can pass through an MBB live, but may not be live every time. It is assumed
481 // that all vregsPassed sets are empty before the call.
482 void
483 MachineVerifier::calcMaxRegsPassed()
484 {
485 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
486 // have any vregsPassed.
487 DenseSet todo;
488 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
489 MFI != MFE; ++MFI) {
490 const MachineBasicBlock &MBB(*MFI);
491 BBInfo &MInfo = MBBInfoMap[&MBB];
492 if (!MInfo.reachable)
493 continue;
494 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
495 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
496 BBInfo &SInfo = MBBInfoMap[*SuI];
497 if (SInfo.addPassed(MInfo.regsLiveOut))
498 todo.insert(*SuI);
499 }
500 }
501
502 // Iteratively push vregsPassed to successors. This will converge to the same
503 // final state regardless of DenseSet iteration order.
504 while (!todo.empty()) {
505 const MachineBasicBlock *MBB = *todo.begin();
506 todo.erase(MBB);
507 BBInfo &MInfo = MBBInfoMap[MBB];
508 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
509 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
510 if (*SuI == MBB)
511 continue;
512 BBInfo &SInfo = MBBInfoMap[*SuI];
513 if (SInfo.addPassed(MInfo.vregsPassed))
514 todo.insert(*SuI);
515 }
516 }
517 }
518
519 // Calculate the minimum vregsPassed set. These are the registers that always
520 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
521 // been called earlier.
522 void
523 MachineVerifier::calcMinRegsPassed()
524 {
525 DenseSet todo;
526 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
527 MFI != MFE; ++MFI)
528 todo.insert(MFI);
529
530 while (!todo.empty()) {
531 const MachineBasicBlock *MBB = *todo.begin();
532 todo.erase(MBB);
533 BBInfo &MInfo = MBBInfoMap[MBB];
534
535 // Remove entries from vRegsPassed that are not live out from all
536 // reachable predecessors.
537 RegSet dead;
538 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
539 E = MInfo.vregsPassed.end(); I != E; ++I) {
540 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
541 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
542 BBInfo &PrInfo = MBBInfoMap[*PrI];
543 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
544 dead.insert(*I);
545 break;
546 }
547 }
548 }
549 // If any regs removed, we need to recheck successors.
550 if (!dead.empty()) {
551 set_subtract(MInfo.vregsPassed, dead);
552 todo.insert(MBB->succ_begin(), MBB->succ_end());
553 }
554 }
555 }
556
557 // Check PHI instructions at the beginning of MBB. It is assumed that
558 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
559 void
560 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
561 {
562 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
563 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
564 DenseSet seen;
565
566 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
567 unsigned Reg = BBI->getOperand(i).getReg();
568 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
569 if (!Pre->isSuccessor(MBB))
570 continue;
571 seen.insert(Pre);
572 BBInfo &PrInfo = MBBInfoMap[Pre];
573 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
574 report("PHI operand is not live-out from predecessor",
575 &BBI->getOperand(i), i);
576 }
577
578 // Did we see all predecessors?
579 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
580 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
581 if (!seen.count(*PrI)) {
582 report("Missing PHI operand", BBI);
583 *OS << "MBB #" << (*PrI)->getNumber()
584 << " is a predecessor according to the CFG.\n";
585 }
586 }
587 }
588 }
589
590 void
591 MachineVerifier::visitMachineFunctionAfter()
592 {
593 calcMaxRegsPassed();
594
595 // With the maximal set of vregsPassed we can verify dead-in registers.
596 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
597 MFI != MFE; ++MFI) {
598 BBInfo &MInfo = MBBInfoMap[MFI];
599
600 // Skip unreachable MBBs.
601 if (!MInfo.reachable)
602 continue;
603
604 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
605 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
606 BBInfo &PrInfo = MBBInfoMap[*PrI];
607 if (!PrInfo.reachable)
608 continue;
609
610 // Verify physical live-ins. EH landing pads have magic live-ins so we
611 // ignore them.
612 if (!MFI->isLandingPad()) {
613 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
614 E = MFI->livein_end(); I != E; ++I) {
615 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
616 !PrInfo.isLiveOut(*I)) {
617 report("Live-in physical register is not live-out from predecessor",
618 MFI);
619 *OS << "Register " << TRI->getName(*I)
620 << " is not live-out from MBB #" << (*PrI)->getNumber()
621 << ".\n";
622 }
623 }
624 }
625
626
627 // Verify dead-in virtual registers.
628 if (!allowVirtDoubleDefs) {
629 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
630 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
631 // DeadIn register must be in neither regsLiveOut or vregsPassed of
632 // any predecessor.
633 if (PrInfo.isLiveOut(I->first)) {
634 report("Live-in virtual register redefined", I->second);
635 *OS << "Register %reg" << I->first
636 << " was live-out from predecessor MBB #"
637 << (*PrI)->getNumber() << ".\n";
638 }
639 }
640 }
641 }
642 }
643
644 calcMinRegsPassed();
645
646 // With the minimal set of vregsPassed we can verify live-in virtual
647 // registers, including PHI instructions.
648 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
649 MFI != MFE; ++MFI) {
650 BBInfo &MInfo = MBBInfoMap[MFI];
651
652 // Skip unreachable MBBs.
653 if (!MInfo.reachable)
654 continue;
655
656 checkPHIOps(MFI);
657
658 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
659 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
660 BBInfo &PrInfo = MBBInfoMap[*PrI];
661 if (!PrInfo.reachable)
662 continue;
663
664 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
665 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
666 if (!PrInfo.isLiveOut(I->first)) {
667 report("Used virtual register is not live-in", I->second);
668 *OS << "Register %reg" << I->first
669 << " is not live-out from predecessor MBB #"
670 << (*PrI)->getNumber()
671 << ".\n";
672 }
673 }
674 }
675 }
676 }