llvm.org GIT mirror llvm / 485d211
[docs][mips] 7.0 Release notes Differential revision: https://reviews.llvm.org/D51355 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@341203 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Atanasyan 1 year, 1 month ago
1 changed file(s) with 39 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
186186 Changes to the MIPS Target
187187 --------------------------
188188
189 During this release ...
190
189 During this release the MIPS target has:
190
191 * Added support for Virtualization, Global INValidate ASE,
192 and CRC ASE instructions.
193
194 * Introduced definitions of ``[d]rem``, ``[d]remu``,
195 and microMIPSR6 ``ll/sc`` instructions.
196
197 * Shrink-wrapping is now supported and enabled by default (except for -O0).
198
199 * Extended size reduction pass by the LWP and SWP instructions.
200
201 * Gained initial support of GlobalISel instruction selection framework.
202
203 * Updated the P5600 scheduler model not to use instruction itineraries.
204
205 * Added disassembly support for comparison and fused (negative) multiply
206 ``add/sub`` instructions.
207
208 * Improved the selection of multiple instructions.
209
210 * Load/store lb, sb, ld, sd, lld, ... instructions
211 now support 32/64-bit offsets.
212
213 * Added support for ``y``, ``M``, and ``L`` inline assembler operand codes.
214
215 * Extended list of relocations supported by the ``.reloc`` directive
216
217 * Fixed using a wrong register class for creating an emergency
218 spill slot for mips3 / n64 abi.
219
220 * MIPS relocation types were generated for microMIPS code.
221
222 * Corrected definitions of multiple instructions (``lwp``, ``swp``, ``ctc2``,
223 ``cfc2``, ``sync``, ``synci``, ``cvt.d.w``, ...).
224
225 * Fixed atomic operations at O0 level.
226
227 * Fixed local dynamic TLS with Sym64
191228
192229 Changes to the PowerPC Target
193230 -----------------------------