llvm.org GIT mirror llvm / 4831923
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317647 91177308-0d34-0410-b5e6-96231b3b80d8 David Blaikie 1 year, 9 months ago
178 changed file(s) with 1906 addition(s) and 1906 deletion(s). Raw diff Collapse all Expand all
2121 #include "llvm/CodeGen/MachineInstrBuilder.h"
2222 #include "llvm/CodeGen/MachineOperand.h"
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetInstrInfo.h"
2425 #include "llvm/IR/Constants.h"
2526 #include "llvm/Support/Debug.h"
2627 #include "llvm/Support/ErrorHandling.h"
2728 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
2929 #include "llvm/Target/TargetOpcodes.h"
3030 #include "llvm/Target/TargetRegisterInfo.h"
3131 #include
1919 #include "llvm/CodeGen/DFAPacketizer.h"
2020 #include "llvm/CodeGen/ScheduleDAG.h"
2121 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
2223 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Target/TargetInstrInfo.h"
2424 #include "llvm/Target/TargetRegisterInfo.h"
2525
2626 namespace llvm {
1616
1717 #include "llvm/ADT/DenseMap.h"
1818 #include "llvm/ADT/DenseSet.h"
19 #include "llvm/ADT/STLExtras.h"
1920 #include "llvm/ADT/SetVector.h"
2021 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/STLExtras.h"
2222 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
2324 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
2525 #include "llvm/Target/TargetSubtargetInfo.h"
2626 #include
2727 #include
0 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
14 #define LLVM_TARGET_TARGETINSTRINFO_H
15
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineCombinerPattern.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/Support/BranchProbability.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include
32 #include
33 #include
34 #include
35 #include
36
37 namespace llvm {
38
39 class DFAPacketizer;
40 class InstrItineraryData;
41 class LiveVariables;
42 class MachineMemOperand;
43 class MachineRegisterInfo;
44 class MCAsmInfo;
45 class MCInst;
46 struct MCSchedModel;
47 class Module;
48 class ScheduleDAG;
49 class ScheduleHazardRecognizer;
50 class SDNode;
51 class SelectionDAG;
52 class RegScavenger;
53 class TargetRegisterClass;
54 class TargetRegisterInfo;
55 class TargetSchedModel;
56 class TargetSubtargetInfo;
57
58 template class SmallVectorImpl;
59
60 //---------------------------------------------------------------------------
61 ///
62 /// TargetInstrInfo - Interface to description of machine instruction set
63 ///
64 class TargetInstrInfo : public MCInstrInfo {
65 public:
66 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
67 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
68 : CallFrameSetupOpcode(CFSetupOpcode),
69 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
70 ReturnOpcode(ReturnOpcode) {}
71 TargetInstrInfo(const TargetInstrInfo &) = delete;
72 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
73 virtual ~TargetInstrInfo();
74
75 static bool isGenericOpcode(unsigned Opc) {
76 return Opc <= TargetOpcode::GENERIC_OP_END;
77 }
78
79 /// Given a machine instruction descriptor, returns the register
80 /// class constraint for OpNum, or NULL.
81 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
82 const TargetRegisterInfo *TRI,
83 const MachineFunction &MF) const;
84
85 /// Return true if the instruction is trivially rematerializable, meaning it
86 /// has no side effects and requires no operands that aren't always available.
87 /// This means the only allowed uses are constants and unallocatable physical
88 /// registers so that the instructions result is independent of the place
89 /// in the function.
90 bool isTriviallyReMaterializable(const MachineInstr &MI,
91 AliasAnalysis *AA = nullptr) const {
92 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
93 (MI.getDesc().isRematerializable() &&
94 (isReallyTriviallyReMaterializable(MI, AA) ||
95 isReallyTriviallyReMaterializableGeneric(MI, AA)));
96 }
97
98 protected:
99 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
100 /// set, this hook lets the target specify whether the instruction is actually
101 /// trivially rematerializable, taking into consideration its operands. This
102 /// predicate must return false if the instruction has any side effects other
103 /// than producing a value, or if it requres any address registers that are
104 /// not always available.
105 /// Requirements must be check as stated in isTriviallyReMaterializable() .
106 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
107 AliasAnalysis *AA) const {
108 return false;
109 }
110
111 /// This method commutes the operands of the given machine instruction MI.
112 /// The operands to be commuted are specified by their indices OpIdx1 and
113 /// OpIdx2.
114 ///
115 /// If a target has any instructions that are commutable but require
116 /// converting to different instructions or making non-trivial changes
117 /// to commute them, this method can be overloaded to do that.
118 /// The default implementation simply swaps the commutable operands.
119 ///
120 /// If NewMI is false, MI is modified in place and returned; otherwise, a
121 /// new machine instruction is created and returned.
122 ///
123 /// Do not call this method for a non-commutable instruction.
124 /// Even though the instruction is commutable, the method may still
125 /// fail to commute the operands, null pointer is returned in such cases.
126 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
127 unsigned OpIdx1,
128 unsigned OpIdx2) const;
129
130 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
131 /// operand indices to (ResultIdx1, ResultIdx2).
132 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
133 /// predefined to some indices or be undefined (designated by the special
134 /// value 'CommuteAnyOperandIndex').
135 /// The predefined result indices cannot be re-defined.
136 /// The function returns true iff after the result pair redefinition
137 /// the fixed result pair is equal to or equivalent to the source pair of
138 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
139 /// the pairs (x,y) and (y,x) are equivalent.
140 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
141 unsigned CommutableOpIdx1,
142 unsigned CommutableOpIdx2);
143
144 private:
145 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
146 /// set and the target hook isReallyTriviallyReMaterializable returns false,
147 /// this function does target-independent tests to determine if the
148 /// instruction is really trivially rematerializable.
149 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
150 AliasAnalysis *AA) const;
151
152 public:
153 /// These methods return the opcode of the frame setup/destroy instructions
154 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
155 /// order to abstract away the difference between operating with a frame
156 /// pointer and operating without, through the use of these two instructions.
157 ///
158 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
159 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
160
161 /// Returns true if the argument is a frame pseudo instruction.
162 bool isFrameInstr(const MachineInstr &I) const {
163 return I.getOpcode() == getCallFrameSetupOpcode() ||
164 I.getOpcode() == getCallFrameDestroyOpcode();
165 }
166
167 /// Returns true if the argument is a frame setup pseudo instruction.
168 bool isFrameSetup(const MachineInstr &I) const {
169 return I.getOpcode() == getCallFrameSetupOpcode();
170 }
171
172 /// Returns size of the frame associated with the given frame instruction.
173 /// For frame setup instruction this is frame that is set up space set up
174 /// after the instruction. For frame destroy instruction this is the frame
175 /// freed by the caller.
176 /// Note, in some cases a call frame (or a part of it) may be prepared prior
177 /// to the frame setup instruction. It occurs in the calls that involve
178 /// inalloca arguments. This function reports only the size of the frame part
179 /// that is set up between the frame setup and destroy pseudo instructions.
180 int64_t getFrameSize(const MachineInstr &I) const {
181 assert(isFrameInstr(I) && "Not a frame instruction");
182 assert(I.getOperand(0).getImm() >= 0);
183 return I.getOperand(0).getImm();
184 }
185
186 /// Returns the total frame size, which is made up of the space set up inside
187 /// the pair of frame start-stop instructions and the space that is set up
188 /// prior to the pair.
189 int64_t getFrameTotalSize(const MachineInstr &I) const {
190 if (isFrameSetup(I)) {
191 assert(I.getOperand(1).getImm() >= 0 &&
192 "Frame size must not be negative");
193 return getFrameSize(I) + I.getOperand(1).getImm();
194 }
195 return getFrameSize(I);
196 }
197
198 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
199 unsigned getReturnOpcode() const { return ReturnOpcode; }
200
201 /// Returns the actual stack pointer adjustment made by an instruction
202 /// as part of a call sequence. By default, only call frame setup/destroy
203 /// instructions adjust the stack, but targets may want to override this
204 /// to enable more fine-grained adjustment, or adjust by a different value.
205 virtual int getSPAdjust(const MachineInstr &MI) const;
206
207 /// Return true if the instruction is a "coalescable" extension instruction.
208 /// That is, it's like a copy where it's legal for the source to overlap the
209 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
210 /// expected the pre-extension value is available as a subreg of the result
211 /// register. This also returns the sub-register index in SubIdx.
212 virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
213 unsigned &DstReg, unsigned &SubIdx) const {
214 return false;
215 }
216
217 /// If the specified machine instruction is a direct
218 /// load from a stack slot, return the virtual or physical register number of
219 /// the destination along with the FrameIndex of the loaded stack slot. If
220 /// not, return 0. This predicate must return 0 if the instruction has
221 /// any side effects other than loading from the stack slot.
222 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
223 int &FrameIndex) const {
224 return 0;
225 }
226
227 /// Check for post-frame ptr elimination stack locations as well.
228 /// This uses a heuristic so it isn't reliable for correctness.
229 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
230 int &FrameIndex) const {
231 return 0;
232 }
233
234 /// If the specified machine instruction has a load from a stack slot,
235 /// return true along with the FrameIndex of the loaded stack slot and the
236 /// machine mem operand containing the reference.
237 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
238 /// any instructions that loads from the stack. This is just a hint, as some
239 /// cases may be missed.
240 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
241 const MachineMemOperand *&MMO,
242 int &FrameIndex) const;
243
244 /// If the specified machine instruction is a direct
245 /// store to a stack slot, return the virtual or physical register number of
246 /// the source reg along with the FrameIndex of the loaded stack slot. If
247 /// not, return 0. This predicate must return 0 if the instruction has
248 /// any side effects other than storing to the stack slot.
249 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
250 int &FrameIndex) const {
251 return 0;
252 }
253
254 /// Check for post-frame ptr elimination stack locations as well.
255 /// This uses a heuristic, so it isn't reliable for correctness.
256 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
257 int &FrameIndex) const {
258 return 0;
259 }
260
261 /// If the specified machine instruction has a store to a stack slot,
262 /// return true along with the FrameIndex of the loaded stack slot and the
263 /// machine mem operand containing the reference.
264 /// If not, return false. Unlike isStoreToStackSlot,
265 /// this returns true for any instructions that stores to the
266 /// stack. This is just a hint, as some cases may be missed.
267 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
268 const MachineMemOperand *&MMO,
269 int &FrameIndex) const;
270
271 /// Return true if the specified machine instruction
272 /// is a copy of one stack slot to another and has no other effect.
273 /// Provide the identity of the two frame indices.
274 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
275 int &SrcFrameIndex) const {
276 return false;
277 }
278
279 /// Compute the size in bytes and offset within a stack slot of a spilled
280 /// register or subregister.
281 ///
282 /// \param [out] Size in bytes of the spilled value.
283 /// \param [out] Offset in bytes within the stack slot.
284 /// \returns true if both Size and Offset are successfully computed.
285 ///
286 /// Not all subregisters have computable spill slots. For example,
287 /// subregisters registers may not be byte-sized, and a pair of discontiguous
288 /// subregisters has no single offset.
289 ///
290 /// Targets with nontrivial bigendian implementations may need to override
291 /// this, particularly to support spilled vector registers.
292 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
293 unsigned &Size, unsigned &Offset,
294 const MachineFunction &MF) const;
295
296 /// Returns the size in bytes of the specified MachineInstr, or ~0U
297 /// when this function is not implemented by a target.
298 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
299 return ~0U;
300 }
301
302 /// Return true if the instruction is as cheap as a move instruction.
303 ///
304 /// Targets for different archs need to override this, and different
305 /// micro-architectures can also be finely tuned inside.
306 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
307 return MI.isAsCheapAsAMove();
308 }
309
310 /// Return true if the instruction should be sunk by MachineSink.
311 ///
312 /// MachineSink determines on its own whether the instruction is safe to sink;
313 /// this gives the target a hook to override the default behavior with regards
314 /// to which instructions should be sunk.
315 virtual bool shouldSink(const MachineInstr &MI) const { return true; }
316
317 /// Re-issue the specified 'original' instruction at the
318 /// specific location targeting a new destination register.
319 /// The register in Orig->getOperand(0).getReg() will be substituted by
320 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
321 /// SubIdx.
322 virtual void reMaterialize(MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator MI, unsigned DestReg,
324 unsigned SubIdx, const MachineInstr &Orig,
325 const TargetRegisterInfo &TRI) const;
326
327 /// \brief Clones instruction or the whole instruction bundle \p Orig and
328 /// insert into \p MBB before \p InsertBefore. The target may update operands
329 /// that are required to be unique.
330 ///
331 /// \p Orig must not return true for MachineInstr::isNotDuplicable().
332 virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator InsertBefore,
334 const MachineInstr &Orig) const;
335
336 /// This method must be implemented by targets that
337 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
338 /// may be able to convert a two-address instruction into one or more true
339 /// three-address instructions on demand. This allows the X86 target (for
340 /// example) to convert ADD and SHL instructions into LEA instructions if they
341 /// would require register copies due to two-addressness.
342 ///
343 /// This method returns a null pointer if the transformation cannot be
344 /// performed, otherwise it returns the last new instruction.
345 ///
346 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
347 MachineInstr &MI,
348 LiveVariables *LV) const {
349 return nullptr;
350 }
351
352 // This constant can be used as an input value of operand index passed to
353 // the method findCommutedOpIndices() to tell the method that the
354 // corresponding operand index is not pre-defined and that the method
355 // can pick any commutable operand.
356 static const unsigned CommuteAnyOperandIndex = ~0U;
357
358 /// This method commutes the operands of the given machine instruction MI.
359 ///
360 /// The operands to be commuted are specified by their indices OpIdx1 and
361 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
362 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
363 /// any arbitrarily chosen commutable operand. If both arguments are set to
364 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
365 /// operands; then commutes them if such operands could be found.
366 ///
367 /// If NewMI is false, MI is modified in place and returned; otherwise, a
368 /// new machine instruction is created and returned.
369 ///
370 /// Do not call this method for a non-commutable instruction or
371 /// for non-commuable operands.
372 /// Even though the instruction is commutable, the method may still
373 /// fail to commute the operands, null pointer is returned in such cases.
374 MachineInstr *
375 commuteInstruction(MachineInstr &MI, bool NewMI = false,
376 unsigned OpIdx1 = CommuteAnyOperandIndex,
377 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
378
379 /// Returns true iff the routine could find two commutable operands in the
380 /// given machine instruction.
381 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
382 /// If any of the INPUT values is set to the special value
383 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
384 /// operand, then returns its index in the corresponding argument.
385 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
386 /// looks for 2 commutable operands.
387 /// If INPUT values refer to some operands of MI, then the method simply
388 /// returns true if the corresponding operands are commutable and returns
389 /// false otherwise.
390 ///
391 /// For example, calling this method this way:
392 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
393 /// findCommutedOpIndices(MI, Op1, Op2);
394 /// can be interpreted as a query asking to find an operand that would be
395 /// commutable with the operand#1.
396 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
397 unsigned &SrcOpIdx2) const;
398
399 /// A pair composed of a register and a sub-register index.
400 /// Used to give some type checking when modeling Reg:SubReg.
401 struct RegSubRegPair {
402 unsigned Reg;
403 unsigned SubReg;
404
405 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
406 : Reg(Reg), SubReg(SubReg) {}
407 };
408
409 /// A pair composed of a pair of a register and a sub-register index,
410 /// and another sub-register index.
411 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
412 struct RegSubRegPairAndIdx : RegSubRegPair {
413 unsigned SubIdx;
414
415 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
416 unsigned SubIdx = 0)
417 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
418 };
419
420 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
421 /// and \p DefIdx.
422 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
423 /// the list is modeled as .
424 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
425 /// two elements:
426 /// - vreg1:sub1, sub0
427 /// - vreg2<:0>, sub1
428 ///
429 /// \returns true if it is possible to build such an input sequence
430 /// with the pair \p MI, \p DefIdx. False otherwise.
431 ///
432 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
433 ///
434 /// \note The generic implementation does not provide any support for
435 /// MI.isRegSequenceLike(). In other words, one has to override
436 /// getRegSequenceLikeInputs for target specific instructions.
437 bool
438 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
439 SmallVectorImpl &InputRegs) const;
440
441 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
442 /// and \p DefIdx.
443 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
444 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
445 /// - vreg1:sub1, sub0
446 ///
447 /// \returns true if it is possible to build such an input sequence
448 /// with the pair \p MI, \p DefIdx. False otherwise.
449 ///
450 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
451 ///
452 /// \note The generic implementation does not provide any support for
453 /// MI.isExtractSubregLike(). In other words, one has to override
454 /// getExtractSubregLikeInputs for target specific instructions.
455 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
456 RegSubRegPairAndIdx &InputReg) const;
457
458 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
459 /// and \p DefIdx.
460 /// \p [out] BaseReg and \p [out] InsertedReg contain
461 /// the equivalent inputs of INSERT_SUBREG.
462 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
463 /// - BaseReg: vreg0:sub0
464 /// - InsertedReg: vreg1:sub1, sub3
465 ///
466 /// \returns true if it is possible to build such an input sequence
467 /// with the pair \p MI, \p DefIdx. False otherwise.
468 ///
469 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
470 ///
471 /// \note The generic implementation does not provide any support for
472 /// MI.isInsertSubregLike(). In other words, one has to override
473 /// getInsertSubregLikeInputs for target specific instructions.
474 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
475 RegSubRegPair &BaseReg,
476 RegSubRegPairAndIdx &InsertedReg) const;
477
478 /// Return true if two machine instructions would produce identical values.
479 /// By default, this is only true when the two instructions
480 /// are deemed identical except for defs. If this function is called when the
481 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
482 /// aggressive checks.
483 virtual bool produceSameValue(const MachineInstr &MI0,
484 const MachineInstr &MI1,
485 const MachineRegisterInfo *MRI = nullptr) const;
486
487 /// \returns true if a branch from an instruction with opcode \p BranchOpc
488 /// bytes is capable of jumping to a position \p BrOffset bytes away.
489 virtual bool isBranchOffsetInRange(unsigned BranchOpc,
490 int64_t BrOffset) const {
491 llvm_unreachable("target did not implement");
492 }
493
494 /// \returns The block that branch instruction \p MI jumps to.
495 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
496 llvm_unreachable("target did not implement");
497 }
498
499 /// Insert an unconditional indirect branch at the end of \p MBB to \p
500 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
501 /// the offset of the position to insert the new branch.
502 ///
503 /// \returns The number of bytes added to the block.
504 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
505 MachineBasicBlock &NewDestBB,
506 const DebugLoc &DL,
507 int64_t BrOffset = 0,
508 RegScavenger *RS = nullptr) const {
509 llvm_unreachable("target did not implement");
510 }
511
512 /// Analyze the branching code at the end of MBB, returning
513 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
514 /// implemented for a target). Upon success, this returns false and returns
515 /// with the following information in various cases:
516 ///
517 /// 1. If this block ends with no branches (it just falls through to its succ)
518 /// just return false, leaving TBB/FBB null.
519 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
520 /// the destination block.
521 /// 3. If this block ends with a conditional branch and it falls through to a
522 /// successor block, it sets TBB to be the branch destination block and a
523 /// list of operands that evaluate the condition. These operands can be
524 /// passed to other TargetInstrInfo methods to create new branches.
525 /// 4. If this block ends with a conditional branch followed by an
526 /// unconditional branch, it returns the 'true' destination in TBB, the
527 /// 'false' destination in FBB, and a list of operands that evaluate the
528 /// condition. These operands can be passed to other TargetInstrInfo
529 /// methods to create new branches.
530 ///
531 /// Note that removeBranch and insertBranch must be implemented to support
532 /// cases where this method returns success.
533 ///
534 /// If AllowModify is true, then this routine is allowed to modify the basic
535 /// block (e.g. delete instructions after the unconditional branch).
536 ///
537 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
538 /// before calling this function.
539 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
540 MachineBasicBlock *&FBB,
541 SmallVectorImpl &Cond,
542 bool AllowModify = false) const {
543 return true;
544 }
545
546 /// Represents a predicate at the MachineFunction level. The control flow a
547 /// MachineBranchPredicate represents is:
548 ///
549 /// Reg = LHS `Predicate` RHS == ConditionDef
550 /// if Reg then goto TrueDest else goto FalseDest
551 ///
552 struct MachineBranchPredicate {
553 enum ComparePredicate {
554 PRED_EQ, // True if two values are equal
555 PRED_NE, // True if two values are not equal
556 PRED_INVALID // Sentinel value
557 };
558
559 ComparePredicate Predicate = PRED_INVALID;
560 MachineOperand LHS = MachineOperand::CreateImm(0);
561 MachineOperand RHS = MachineOperand::CreateImm(0);
562 MachineBasicBlock *TrueDest = nullptr;
563 MachineBasicBlock *FalseDest = nullptr;
564 MachineInstr *ConditionDef = nullptr;
565
566 /// SingleUseCondition is true if ConditionDef is dead except for the
567 /// branch(es) at the end of the basic block.
568 ///
569 bool SingleUseCondition = false;
570
571 explicit MachineBranchPredicate() = default;
572 };
573
574 /// Analyze the branching code at the end of MBB and parse it into the
575 /// MachineBranchPredicate structure if possible. Returns false on success
576 /// and true on failure.
577 ///
578 /// If AllowModify is true, then this routine is allowed to modify the basic
579 /// block (e.g. delete instructions after the unconditional branch).
580 ///
581 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
582 MachineBranchPredicate &MBP,
583 bool AllowModify = false) const {
584 return true;
585 }
586
587 /// Remove the branching code at the end of the specific MBB.
588 /// This is only invoked in cases where AnalyzeBranch returns success. It
589 /// returns the number of instructions that were removed.
590 /// If \p BytesRemoved is non-null, report the change in code size from the
591 /// removed instructions.
592 virtual unsigned removeBranch(MachineBasicBlock &MBB,
593 int *BytesRemoved = nullptr) const {
594 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
595 }
596
597 /// Insert branch code into the end of the specified MachineBasicBlock. The
598 /// operands to this method are the same as those returned by AnalyzeBranch.
599 /// This is only invoked in cases where AnalyzeBranch returns success. It
600 /// returns the number of instructions inserted. If \p BytesAdded is non-null,
601 /// report the change in code size from the added instructions.
602 ///
603 /// It is also invoked by tail merging to add unconditional branches in
604 /// cases where AnalyzeBranch doesn't apply because there was no original
605 /// branch to analyze. At least this much must be implemented, else tail
606 /// merging needs to be disabled.
607 ///
608 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
609 /// before calling this function.
610 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
611 MachineBasicBlock *FBB,
612 ArrayRef Cond,
613 const DebugLoc &DL,
614 int *BytesAdded = nullptr) const {
615 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
616 }
617
618 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
619 MachineBasicBlock *DestBB,
620 const DebugLoc &DL,
621 int *BytesAdded = nullptr) const {
622 return insertBranch(MBB, DestBB, nullptr, ArrayRef(), DL,
623 BytesAdded);
624 }
625
626 /// Analyze the loop code, return true if it cannot be understoo. Upon
627 /// success, this function returns false and returns information about the
628 /// induction variable and compare instruction used at the end.
629 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
630 MachineInstr *&CmpInst) const {
631 return true;
632 }
633
634 /// Generate code to reduce the loop iteration by one and check if the loop is
635 /// finished. Return the value/register of the the new loop count. We need
636 /// this function when peeling off one or more iterations of a loop. This
637 /// function assumes the nth iteration is peeled first.
638 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
639 MachineInstr &Cmp,
640 SmallVectorImpl &Cond,
641 SmallVectorImpl &PrevInsts,
642 unsigned Iter, unsigned MaxIter) const {
643 llvm_unreachable("Target didn't implement ReduceLoopCount");
644 }
645
646 /// Delete the instruction OldInst and everything after it, replacing it with
647 /// an unconditional branch to NewDest. This is used by the tail merging pass.
648 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
649 MachineBasicBlock *NewDest) const;
650
651 /// Return true if it's legal to split the given basic
652 /// block at the specified instruction (i.e. instruction would be the start
653 /// of a new basic block).
654 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator MBBI) const {
656 return true;
657 }
658
659 /// Return true if it's profitable to predicate
660 /// instructions with accumulated instruction latency of "NumCycles"
661 /// of the specified basic block, where the probability of the instructions
662 /// being executed is given by Probability, and Confidence is a measure
663 /// of our confidence that it will be properly predicted.
664 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
665 unsigned ExtraPredCycles,
666 BranchProbability Probability) const {
667 return false;
668 }
669
670 /// Second variant of isProfitableToIfCvt. This one
671 /// checks for the case where two basic blocks from true and false path
672 /// of a if-then-else (diamond) are predicated on mutally exclusive
673 /// predicates, where the probability of the true path being taken is given
674 /// by Probability, and Confidence is a measure of our confidence that it
675 /// will be properly predicted.
676 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
677 unsigned ExtraTCycles,
678 MachineBasicBlock &FMBB, unsigned NumFCycles,
679 unsigned ExtraFCycles,
680 BranchProbability Probability) const {
681 return false;
682 }
683
684 /// Return true if it's profitable for if-converter to duplicate instructions
685 /// of specified accumulated instruction latencies in the specified MBB to
686 /// enable if-conversion.
687 /// The probability of the instructions being executed is given by
688 /// Probability, and Confidence is a measure of our confidence that it
689 /// will be properly predicted.
690 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
691 unsigned NumCycles,
692 BranchProbability Probability) const {
693 return false;
694 }
695
696 /// Return true if it's profitable to unpredicate
697 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
698 /// exclusive predicates.
699 /// e.g.
700 /// subeq r0, r1, #1
701 /// addne r0, r1, #1
702 /// =>
703 /// sub r0, r1, #1
704 /// addne r0, r1, #1
705 ///
706 /// This may be profitable is conditional instructions are always executed.
707 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
708 MachineBasicBlock &FMBB) const {
709 return false;
710 }
711
712 /// Return true if it is possible to insert a select
713 /// instruction that chooses between TrueReg and FalseReg based on the
714 /// condition code in Cond.
715 ///
716 /// When successful, also return the latency in cycles from TrueReg,
717 /// FalseReg, and Cond to the destination register. In most cases, a select
718 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
719 ///
720 /// Some x86 implementations have 2-cycle cmov instructions.
721 ///
722 /// @param MBB Block where select instruction would be inserted.
723 /// @param Cond Condition returned by AnalyzeBranch.
724 /// @param TrueReg Virtual register to select when Cond is true.
725 /// @param FalseReg Virtual register to select when Cond is false.
726 /// @param CondCycles Latency from Cond+Branch to select output.
727 /// @param TrueCycles Latency from TrueReg to select output.
728 /// @param FalseCycles Latency from FalseReg to select output.
729 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
730 ArrayRef Cond, unsigned TrueReg,
731 unsigned FalseReg, int &CondCycles,
732 int &TrueCycles, int &FalseCycles) const {
733 return false;
734 }
735
736 /// Insert a select instruction into MBB before I that will copy TrueReg to
737 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
738 ///
739 /// This function can only be called after canInsertSelect() returned true.
740 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
741 /// that the same flags or registers required by Cond are available at the
742 /// insertion point.
743 ///
744 /// @param MBB Block where select instruction should be inserted.
745 /// @param I Insertion point.
746 /// @param DL Source location for debugging.
747 /// @param DstReg Virtual register to be defined by select instruction.
748 /// @param Cond Condition as computed by AnalyzeBranch.
749 /// @param TrueReg Virtual register to copy when Cond is true.
750 /// @param FalseReg Virtual register to copy when Cons is false.
751 virtual void insertSelect(MachineBasicBlock &MBB,
752 MachineBasicBlock::iterator I, const DebugLoc &DL,
753 unsigned DstReg, ArrayRef Cond,
754 unsigned TrueReg, unsigned FalseReg) const {
755 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
756 }
757
758 /// Analyze the given select instruction, returning true if
759 /// it cannot be understood. It is assumed that MI->isSelect() is true.
760 ///
761 /// When successful, return the controlling condition and the operands that
762 /// determine the true and false result values.
763 ///
764 /// Result = SELECT Cond, TrueOp, FalseOp
765 ///
766 /// Some targets can optimize select instructions, for example by predicating
767 /// the instruction defining one of the operands. Such targets should set
768 /// Optimizable.
769 ///
770 /// @param MI Select instruction to analyze.
771 /// @param Cond Condition controlling the select.
772 /// @param TrueOp Operand number of the value selected when Cond is true.
773 /// @param FalseOp Operand number of the value selected when Cond is false.
774 /// @param Optimizable Returned as true if MI is optimizable.
775 /// @returns False on success.
776 virtual bool analyzeSelect(const MachineInstr &MI,
777 SmallVectorImpl &Cond,
778 unsigned &TrueOp, unsigned &FalseOp,
779 bool &Optimizable) const {
780 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
781 return true;
782 }
783
784 /// Given a select instruction that was understood by
785 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
786 /// merging it with one of its operands. Returns NULL on failure.
787 ///
788 /// When successful, returns the new select instruction. The client is
789 /// responsible for deleting MI.
790 ///
791 /// If both sides of the select can be optimized, PreferFalse is used to pick
792 /// a side.
793 ///
794 /// @param MI Optimizable select instruction.
795 /// @param NewMIs Set that record all MIs in the basic block up to \p
796 /// MI. Has to be updated with any newly created MI or deleted ones.
797 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
798 /// @returns Optimized instruction or NULL.
799 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
800 SmallPtrSetImpl &NewMIs,
801 bool PreferFalse = false) const {
802 // This function must be implemented if Optimizable is ever set.
803 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
804 }
805
806 /// Emit instructions to copy a pair of physical registers.
807 ///
808 /// This function should support copies within any legal register class as
809 /// well as any cross-class copies created during instruction selection.
810 ///
811 /// The source and destination registers may overlap, which may require a
812 /// careful implementation when multiple copy instructions are required for
813 /// large registers. See for example the ARM target.
814 virtual void copyPhysReg(MachineBasicBlock &MBB,
815 MachineBasicBlock::iterator MI, const DebugLoc &DL,
816 unsigned DestReg, unsigned SrcReg,
817 bool KillSrc) const {
818 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
819 }
820
821 /// Store the specified register of the given register class to the specified
822 /// stack frame index. The store instruction is to be added to the given
823 /// machine basic block before the specified machine instruction. If isKill
824 /// is true, the register operand is the last use and must be marked kill.
825 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
826 MachineBasicBlock::iterator MI,
827 unsigned SrcReg, bool isKill, int FrameIndex,
828 const TargetRegisterClass *RC,
829 const TargetRegisterInfo *TRI) const {
830 llvm_unreachable("Target didn't implement "
831 "TargetInstrInfo::storeRegToStackSlot!");
832 }
833
834 /// Load the specified register of the given register class from the specified
835 /// stack frame index. The load instruction is to be added to the given
836 /// machine basic block before the specified machine instruction.
837 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
838 MachineBasicBlock::iterator MI,
839 unsigned DestReg, int FrameIndex,
840 const TargetRegisterClass *RC,
841 const TargetRegisterInfo *TRI) const {
842 llvm_unreachable("Target didn't implement "
843 "TargetInstrInfo::loadRegFromStackSlot!");
844 }
845
846 /// This function is called for all pseudo instructions
847 /// that remain after register allocation. Many pseudo instructions are
848 /// created to help register allocation. This is the place to convert them
849 /// into real instructions. The target can edit MI in place, or it can insert
850 /// new instructions and erase MI. The function should return true if
851 /// anything was changed.
852 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
853
854 /// Check whether the target can fold a load that feeds a subreg operand
855 /// (or a subreg operand that feeds a store).
856 /// For example, X86 may want to return true if it can fold
857 /// movl (%esp), %eax
858 /// subb, %al, ...
859 /// Into:
860 /// subb (%esp), ...
861 ///
862 /// Ideally, we'd like the target implementation of foldMemoryOperand() to
863 /// reject subregs - but since this behavior used to be enforced in the
864 /// target-independent code, moving this responsibility to the targets
865 /// has the potential of causing nasty silent breakage in out-of-tree targets.
866 virtual bool isSubregFoldable() const { return false; }
867
868 /// Attempt to fold a load or store of the specified stack
869 /// slot into the specified machine instruction for the specified operand(s).
870 /// If this is possible, a new instruction is returned with the specified
871 /// operand folded, otherwise NULL is returned.
872 /// The new instruction is inserted before MI, and the client is responsible
873 /// for removing the old instruction.
874 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
875 int FrameIndex,
876 LiveIntervals *LIS = nullptr) const;
877
878 /// Same as the previous version except it allows folding of any load and
879 /// store from / to any address, not just from a specific stack slot.
880 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
881 MachineInstr &LoadMI,
882 LiveIntervals *LIS = nullptr) const;
883
884 /// Return true when there is potentially a faster code sequence
885 /// for an instruction chain ending in \p Root. All potential patterns are
886 /// returned in the \p Pattern vector. Pattern should be sorted in priority
887 /// order since the pattern evaluator stops checking as soon as it finds a
888 /// faster sequence.
889 /// \param Root - Instruction that could be combined with one of its operands
890 /// \param Patterns - Vector of possible combination patterns
891 virtual bool getMachineCombinerPatterns(
892 MachineInstr &Root,
893 SmallVectorImpl &Patterns) const;
894
895 /// Return true when a code sequence can improve throughput. It
896 /// should be called only for instructions in loops.
897 /// \param Pattern - combiner pattern
898 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
899
900 /// Return true if the input \P Inst is part of a chain of dependent ops
901 /// that are suitable for reassociation, otherwise return false.
902 /// If the instruction's operands must be commuted to have a previous
903 /// instruction of the same type define the first source operand, \P Commuted
904 /// will be set to true.
905 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
906
907 /// Return true when \P Inst is both associative and commutative.
908 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
909 return false;
910 }
911
912 /// Return true when \P Inst has reassociable operands in the same \P MBB.
913 virtual bool hasReassociableOperands(const MachineInstr &Inst,
914 const MachineBasicBlock *MBB) const;
915
916 /// Return true when \P Inst has reassociable sibling.
917 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
918
919 /// When getMachineCombinerPatterns() finds patterns, this function generates
920 /// the instructions that could replace the original code sequence. The client
921 /// has to decide whether the actual replacement is beneficial or not.
922 /// \param Root - Instruction that could be combined with one of its operands
923 /// \param Pattern - Combination pattern for Root
924 /// \param InsInstrs - Vector of new instructions that implement P
925 /// \param DelInstrs - Old instructions, including Root, that could be
926 /// replaced by InsInstr
927 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
928 /// InsInstr that defines it
929 virtual void genAlternativeCodeSequence(
930 MachineInstr &Root, MachineCombinerPattern Pattern,
931 SmallVectorImpl &InsInstrs,
932 SmallVectorImpl &DelInstrs,
933 DenseMap &InstrIdxForVirtReg) const;
934
935 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
936 /// reduce critical path length.
937 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
938 MachineCombinerPattern Pattern,
939 SmallVectorImpl &InsInstrs,
940 SmallVectorImpl &DelInstrs,
941 DenseMap &InstrIdxForVirtReg) const;
942
943 /// This is an architecture-specific helper function of reassociateOps.
944 /// Set special operand attributes for new instructions after reassociation.
945 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
946 MachineInstr &NewMI1,
947 MachineInstr &NewMI2) const {}
948
949 /// Return true when a target supports MachineCombiner.
950 virtual bool useMachineCombiner() const { return false; }
951
952 protected:
953 /// Target-dependent implementation for foldMemoryOperand.
954 /// Target-independent code in foldMemoryOperand will
955 /// take care of adding a MachineMemOperand to the newly created instruction.
956 /// The instruction and any auxiliary instructions necessary will be inserted
957 /// at InsertPt.
958 virtual MachineInstr *
959 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
960 ArrayRef Ops,
961 MachineBasicBlock::iterator InsertPt, int FrameIndex,
962 LiveIntervals *LIS = nullptr) const {
963 return nullptr;
964 }
965
966 /// Target-dependent implementation for foldMemoryOperand.
967 /// Target-independent code in foldMemoryOperand will
968 /// take care of adding a MachineMemOperand to the newly created instruction.
969 /// The instruction and any auxiliary instructions necessary will be inserted
970 /// at InsertPt.
971 virtual MachineInstr *foldMemoryOperandImpl(
972 MachineFunction &MF, MachineInstr &MI, ArrayRef Ops,
973 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
974 LiveIntervals *LIS = nullptr) const {
975 return nullptr;
976 }
977
978 /// \brief Target-dependent implementation of getRegSequenceInputs.
979 ///
980 /// \returns true if it is possible to build the equivalent
981 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
982 ///
983 /// \pre MI.isRegSequenceLike().
984 ///
985 /// \see TargetInstrInfo::getRegSequenceInputs.
986 virtual bool getRegSequenceLikeInputs(
987 const MachineInstr &MI, unsigned DefIdx,
988 SmallVectorImpl &InputRegs) const {
989 return false;
990 }
991
992 /// \brief Target-dependent implementation of getExtractSubregInputs.
993 ///
994 /// \returns true if it is possible to build the equivalent
995 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
996 ///
997 /// \pre MI.isExtractSubregLike().
998 ///
999 /// \see TargetInstrInfo::getExtractSubregInputs.
1000 virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1001 unsigned DefIdx,
1002 RegSubRegPairAndIdx &InputReg) const {
1003 return false;
1004 }
1005
1006 /// \brief Target-dependent implementation of getInsertSubregInputs.
1007 ///
1008 /// \returns true if it is possible to build the equivalent
1009 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1010 ///
1011 /// \pre MI.isInsertSubregLike().
1012 ///
1013 /// \see TargetInstrInfo::getInsertSubregInputs.
1014 virtual bool
1015 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1016 RegSubRegPair &BaseReg,
1017 RegSubRegPairAndIdx &InsertedReg) const {
1018 return false;
1019 }
1020
1021 public:
1022 /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1023 /// (e.g. stack) the target returns the corresponding address space.
1024 virtual unsigned
1025 getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
1026 return 0;
1027 }
1028
1029 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1030 /// a store or a load and a store into two or more instruction. If this is
1031 /// possible, returns true as well as the new instructions by reference.
1032 virtual bool
1033 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1034 bool UnfoldLoad, bool UnfoldStore,
1035 SmallVectorImpl &NewMIs) const {
1036 return false;
1037 }
1038
1039 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1040 SmallVectorImpl &NewNodes) const {
1041 return false;
1042 }
1043
1044 /// Returns the opcode of the would be new
1045 /// instruction after load / store are unfolded from an instruction of the
1046 /// specified opcode. It returns zero if the specified unfolding is not
1047 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1048 /// index of the operand which will hold the register holding the loaded
1049 /// value.
1050 virtual unsigned
1051 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1052 unsigned *LoadRegIndex = nullptr) const {
1053 return 0;
1054 }
1055
1056 /// This is used by the pre-regalloc scheduler to determine if two loads are
1057 /// loading from the same base address. It should only return true if the base
1058 /// pointers are the same and the only differences between the two addresses
1059 /// are the offset. It also returns the offsets by reference.
1060 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1061 int64_t &Offset1,
1062 int64_t &Offset2) const {
1063 return false;
1064 }
1065
1066 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1067 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1068 /// On some targets if two loads are loading from
1069 /// addresses in the same cache line, it's better if they are scheduled
1070 /// together. This function takes two integers that represent the load offsets
1071 /// from the common base address. It returns true if it decides it's desirable
1072 /// to schedule the two loads together. "NumLoads" is the number of loads that
1073 /// have already been scheduled after Load1.
1074 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1075 int64_t Offset1, int64_t Offset2,
1076 unsigned NumLoads) const {
1077 return false;
1078 }
1079
1080 /// Get the base register and byte offset of an instruction that reads/writes
1081 /// memory.
1082 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1083 int64_t &Offset,
1084 const TargetRegisterInfo *TRI) const {
1085 return false;
1086 }
1087
1088 /// Return true if the instruction contains a base register and offset. If
1089 /// true, the function also sets the operand position in the instruction
1090 /// for the base register and offset.
1091 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1092 unsigned &BasePos,
1093 unsigned &OffsetPos) const {
1094 return false;
1095 }
1096
1097 /// If the instruction is an increment of a constant value, return the amount.
1098 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1099 return false;
1100 }
1101
1102 /// Returns true if the two given memory operations should be scheduled
1103 /// adjacent. Note that you have to add:
1104 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1105 /// or
1106 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1107 /// to TargetPassConfig::createMachineScheduler() to have an effect.
1108 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
1109 MachineInstr &SecondLdSt, unsigned BaseReg2,
1110 unsigned NumLoads) const {
1111 llvm_unreachable("target did not implement shouldClusterMemOps()");
1112 }
1113
1114 /// Reverses the branch condition of the specified condition list,
1115 /// returning false on success and true if it cannot be reversed.
1116 virtual bool
1117 reverseBranchCondition(SmallVectorImpl &Cond) const {
1118 return true;
1119 }
1120
1121 /// Insert a noop into the instruction stream at the specified point.
1122 virtual void insertNoop(MachineBasicBlock &MBB,
1123 MachineBasicBlock::iterator MI) const;
1124
1125 /// Return the noop instruction to use for a noop.
1126 virtual void getNoop(MCInst &NopInst) const;
1127
1128 /// Return true for post-incremented instructions.
1129 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1130
1131 /// Returns true if the instruction is already predicated.
1132 virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1133
1134 /// Returns true if the instruction is a
1135 /// terminator instruction that has not been predicated.
1136 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1137
1138 /// Returns true if MI is an unconditional tail call.
1139 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1140 return false;
1141 }
1142
1143 /// Returns true if the tail call can be made conditional on BranchCond.
1144 virtual bool canMakeTailCallConditional(SmallVectorImpl &Cond,
1145 const MachineInstr &TailCall) const {
1146 return false;
1147 }
1148
1149 /// Replace the conditional branch in MBB with a conditional tail call.
1150 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1151 SmallVectorImpl &Cond,
1152 const MachineInstr &TailCall) const {
1153 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1154 }
1155
1156 /// Convert the instruction into a predicated instruction.
1157 /// It returns true if the operation was successful.
1158 virtual bool PredicateInstruction(MachineInstr &MI,
1159 ArrayRef Pred) const;
1160
1161 /// Returns true if the first specified predicate
1162 /// subsumes the second, e.g. GE subsumes GT.
1163 virtual bool SubsumesPredicate(ArrayRef Pred1,
1164 ArrayRef Pred2) const {
1165 return false;
1166 }
1167
1168 /// If the specified instruction defines any predicate
1169 /// or condition code register(s) used for predication, returns true as well
1170 /// as the definition predicate(s) by reference.
1171 virtual bool DefinesPredicate(MachineInstr &MI,
1172 std::vector &Pred) const {
1173 return false;
1174 }
1175
1176 /// Return true if the specified instruction can be predicated.
1177 /// By default, this returns true for every instruction with a
1178 /// PredicateOperand.
1179 virtual bool isPredicable(const MachineInstr &MI) const {
1180 return MI.getDesc().isPredicable();
1181 }
1182
1183 /// Return true if it's safe to move a machine
1184 /// instruction that defines the specified register class.
1185 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1186 return true;
1187 }
1188
1189 /// Test if the given instruction should be considered a scheduling boundary.
1190 /// This primarily includes labels and terminators.
1191 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1192 const MachineBasicBlock *MBB,
1193 const MachineFunction &MF) const;
1194
1195 /// Measure the specified inline asm to determine an approximation of its
1196 /// length.
1197 virtual unsigned getInlineAsmLength(const char *Str,
1198 const MCAsmInfo &MAI) const;
1199
1200 /// Allocate and return a hazard recognizer to use for this target when
1201 /// scheduling the machine instructions before register allocation.
1202 virtual ScheduleHazardRecognizer *
1203 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1204 const ScheduleDAG *DAG) const;
1205
1206 /// Allocate and return a hazard recognizer to use for this target when
1207 /// scheduling the machine instructions before register allocation.
1208 virtual ScheduleHazardRecognizer *
1209 CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1210 const ScheduleDAG *DAG) const;
1211
1212 /// Allocate and return a hazard recognizer to use for this target when
1213 /// scheduling the machine instructions after register allocation.
1214 virtual ScheduleHazardRecognizer *
1215 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1216 const ScheduleDAG *DAG) const;
1217
1218 /// Allocate and return a hazard recognizer to use for by non-scheduling
1219 /// passes.
1220 virtual ScheduleHazardRecognizer *
1221 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1222 return nullptr;
1223 }
1224
1225 /// Provide a global flag for disabling the PreRA hazard recognizer that
1226 /// targets may choose to honor.
1227 bool usePreRAHazardRecognizer() const;
1228
1229 /// For a comparison instruction, return the source registers
1230 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1231 /// compares against in CmpValue. Return true if the comparison instruction
1232 /// can be analyzed.
1233 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1234 unsigned &SrcReg2, int &Mask, int &Value) const {
1235 return false;
1236 }
1237
1238 /// See if the comparison instruction can be converted
1239 /// into something more efficient. E.g., on ARM most instructions can set the
1240 /// flags register, obviating the need for a separate CMP.
1241 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1242 unsigned SrcReg2, int Mask, int Value,
1243 const MachineRegisterInfo *MRI) const {
1244 return false;
1245 }
1246 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1247
1248 /// Try to remove the load by folding it to a register operand at the use.
1249 /// We fold the load instructions if and only if the
1250 /// def and use are in the same BB. We only look at one load and see
1251 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1252 /// defined by the load we are trying to fold. DefMI returns the machine
1253 /// instruction that defines FoldAsLoadDefReg, and the function returns
1254 /// the machine instruction generated due to folding.
1255 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1256 const MachineRegisterInfo *MRI,
1257 unsigned &FoldAsLoadDefReg,
1258 MachineInstr *&DefMI) const {
1259 return nullptr;
1260 }
1261
1262 /// 'Reg' is known to be defined by a move immediate instruction,
1263 /// try to fold the immediate into the use instruction.
1264 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1265 /// then the caller may assume that DefMI has been erased from its parent
1266 /// block. The caller may assume that it will not be erased by this
1267 /// function otherwise.
1268 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1269 unsigned Reg, MachineRegisterInfo *MRI) const {
1270 return false;
1271 }
1272
1273 /// Return the number of u-operations the given machine
1274 /// instruction will be decoded to on the target cpu. The itinerary's
1275 /// IssueWidth is the number of microops that can be dispatched each
1276 /// cycle. An instruction with zero microops takes no dispatch resources.
1277 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1278 const MachineInstr &MI) const;
1279
1280 /// Return true for pseudo instructions that don't consume any
1281 /// machine resources in their current form. These are common cases that the
1282 /// scheduler should consider free, rather than conservatively handling them
1283 /// as instructions with no itinerary.
1284 bool isZeroCost(unsigned Opcode) const {
1285 return Opcode <= TargetOpcode::COPY;
1286 }
1287
1288 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1289 SDNode *DefNode, unsigned DefIdx,
1290 SDNode *UseNode, unsigned UseIdx) const;
1291
1292 /// Compute and return the use operand latency of a given pair of def and use.
1293 /// In most cases, the static scheduling itinerary was enough to determine the
1294 /// operand latency. But it may not be possible for instructions with variable
1295 /// number of defs / uses.
1296 ///
1297 /// This is a raw interface to the itinerary that may be directly overridden
1298 /// by a target. Use computeOperandLatency to get the best estimate of
1299 /// latency.
1300 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1301 const MachineInstr &DefMI, unsigned DefIdx,
1302 const MachineInstr &UseMI,
1303 unsigned UseIdx) const;
1304
1305 /// Compute the instruction latency of a given instruction.
1306 /// If the instruction has higher cost when predicated, it's returned via
1307 /// PredCost.
1308 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1309 const MachineInstr &MI,
1310 unsigned *PredCost = nullptr) const;
1311
1312 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1313
1314 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1315 SDNode *Node) const;
1316
1317 /// Return the default expected latency for a def based on its opcode.
1318 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1319 const MachineInstr &DefMI) const;
1320
1321 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1322 const MachineInstr &DefMI) const;
1323
1324 /// Return true if this opcode has high latency to its result.
1325 virtual bool isHighLatencyDef(int opc) const { return false; }
1326
1327 /// Compute operand latency between a def of 'Reg'
1328 /// and a use in the current loop. Return true if the target considered
1329 /// it 'high'. This is used by optimization passes such as machine LICM to
1330 /// determine whether it makes sense to hoist an instruction out even in a
1331 /// high register pressure situation.
1332 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1333 const MachineRegisterInfo *MRI,
1334 const MachineInstr &DefMI, unsigned DefIdx,
1335 const MachineInstr &UseMI,
1336 unsigned UseIdx) const {
1337 return false;
1338 }
1339
1340 /// Compute operand latency of a def of 'Reg'. Return true
1341 /// if the target considered it 'low'.
1342 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1343 const MachineInstr &DefMI,
1344 unsigned DefIdx) const;
1345
1346 /// Perform target-specific instruction verification.
1347 virtual bool verifyInstruction(const MachineInstr &MI,
1348 StringRef &ErrInfo) const {
1349 return true;
1350 }
1351
1352 /// Return the current execution domain and bit mask of
1353 /// possible domains for instruction.
1354 ///
1355 /// Some micro-architectures have multiple execution domains, and multiple
1356 /// opcodes that perform the same operation in different domains. For
1357 /// example, the x86 architecture provides the por, orps, and orpd
1358 /// instructions that all do the same thing. There is a latency penalty if a
1359 /// register is written in one domain and read in another.
1360 ///
1361 /// This function returns a pair (domain, mask) containing the execution
1362 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1363 /// function can be used to change the opcode to one of the domains in the
1364 /// bit mask. Instructions whose execution domain can't be changed should
1365 /// return a 0 mask.
1366 ///
1367 /// The execution domain numbers don't have any special meaning except domain
1368 /// 0 is used for instructions that are not associated with any interesting
1369 /// execution domain.
1370 ///
1371 virtual std::pair
1372 getExecutionDomain(const MachineInstr &MI) const {
1373 return std::make_pair(0, 0);
1374 }
1375
1376 /// Change the opcode of MI to execute in Domain.
1377 ///
1378 /// The bit (1 << Domain) must be set in the mask returned from
1379 /// getExecutionDomain(MI).
1380 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1381
1382 /// Returns the preferred minimum clearance
1383 /// before an instruction with an unwanted partial register update.
1384 ///
1385 /// Some instructions only write part of a register, and implicitly need to
1386 /// read the other parts of the register. This may cause unwanted stalls
1387 /// preventing otherwise unrelated instructions from executing in parallel in
1388 /// an out-of-order CPU.
1389 ///
1390 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1391 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1392 /// the instruction needs to wait for the old value of the register to become
1393 /// available:
1394 ///
1395 /// addps %xmm1, %xmm0
1396 /// movaps %xmm0, (%rax)
1397 /// cvtsi2ss %rbx, %xmm0
1398 ///
1399 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1400 /// instruction before it can issue, even though the high bits of %xmm0
1401 /// probably aren't needed.
1402 ///
1403 /// This hook returns the preferred clearance before MI, measured in
1404 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1405 /// instructions before MI. It should only return a positive value for
1406 /// unwanted dependencies. If the old bits of the defined register have
1407 /// useful values, or if MI is determined to otherwise read the dependency,
1408 /// the hook should return 0.
1409 ///
1410 /// The unwanted dependency may be handled by:
1411 ///
1412 /// 1. Allocating the same register for an MI def and use. That makes the
1413 /// unwanted dependency identical to a required dependency.
1414 ///
1415 /// 2. Allocating a register for the def that has no defs in the previous N
1416 /// instructions.
1417 ///
1418 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1419 /// allows the target to insert a dependency breaking instruction.
1420 ///
1421 virtual unsigned
1422 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1423 const TargetRegisterInfo *TRI) const {
1424 // The default implementation returns 0 for no partial register dependency.
1425 return 0;
1426 }
1427
1428 /// \brief Return the minimum clearance before an instruction that reads an
1429 /// unused register.
1430 ///
1431 /// For example, AVX instructions may copy part of a register operand into
1432 /// the unused high bits of the destination register.
1433 ///
1434 /// vcvtsi2sdq %rax, %xmm0, %xmm14
1435 ///
1436 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1437 /// false dependence on any previous write to %xmm0.
1438 ///
1439 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1440 /// does not take an operand index. Instead sets \p OpNum to the index of the
1441 /// unused register.
1442 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1443 const TargetRegisterInfo *TRI) const {
1444 // The default implementation returns 0 for no undef register dependency.
1445 return 0;
1446 }
1447
1448 /// Insert a dependency-breaking instruction
1449 /// before MI to eliminate an unwanted dependency on OpNum.
1450 ///
1451 /// If it wasn't possible to avoid a def in the last N instructions before MI
1452 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1453 /// unwanted dependency.
1454 ///
1455 /// On x86, an xorps instruction can be used as a dependency breaker:
1456 ///
1457 /// addps %xmm1, %xmm0
1458 /// movaps %xmm0, (%rax)
1459 /// xorps %xmm0, %xmm0
1460 /// cvtsi2ss %rbx, %xmm0
1461 ///
1462 /// An operand should be added to MI if an instruction was
1463 /// inserted. This ties the instructions together in the post-ra scheduler.
1464 ///
1465 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1466 const TargetRegisterInfo *TRI) const {}
1467
1468 /// Create machine specific model for scheduling.
1469 virtual DFAPacketizer *
1470 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1471 return nullptr;
1472 }
1473
1474 /// Sometimes, it is possible for the target
1475 /// to tell, even without aliasing information, that two MIs access different
1476 /// memory addresses. This function returns true if two MIs access different
1477 /// memory addresses and false otherwise.
1478 ///
1479 /// Assumes any physical registers used to compute addresses have the same
1480 /// value for both instructions. (This is the most useful assumption for
1481 /// post-RA scheduling.)
1482 ///
1483 /// See also MachineInstr::mayAlias, which is implemented on top of this
1484 /// function.
1485 virtual bool
1486 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1487 AliasAnalysis *AA = nullptr) const {
1488 assert((MIa.mayLoad() || MIa.mayStore()) &&
1489 "MIa must load from or modify a memory location");
1490 assert((MIb.mayLoad() || MIb.mayStore()) &&
1491 "MIb must load from or modify a memory location");
1492 return false;
1493 }
1494
1495 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1496 /// which is a heuristic used for CSE'ing phys reg defs.
1497 virtual unsigned getMachineCSELookAheadLimit() const {
1498 // The default lookahead is small to prevent unprofitable quadratic
1499 // behavior.
1500 return 5;
1501 }
1502
1503 /// Return an array that contains the ids of the target indices (used for the
1504 /// TargetIndex machine operand) and their names.
1505 ///
1506 /// MIR Serialization is able to serialize only the target indices that are
1507 /// defined by this method.
1508 virtual ArrayRef>
1509 getSerializableTargetIndices() const {
1510 return None;
1511 }
1512
1513 /// Decompose the machine operand's target flags into two values - the direct
1514 /// target flag value and any of bit flags that are applied.
1515 virtual std::pair
1516 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1517 return std::make_pair(0u, 0u);
1518 }
1519
1520 /// Return an array that contains the direct target flag values and their
1521 /// names.
1522 ///
1523 /// MIR Serialization is able to serialize only the target flags that are
1524 /// defined by this method.
1525 virtual ArrayRef>
1526 getSerializableDirectMachineOperandTargetFlags() const {
1527 return None;
1528 }
1529
1530 /// Return an array that contains the bitmask target flag values and their
1531 /// names.
1532 ///
1533 /// MIR Serialization is able to serialize only the target flags that are
1534 /// defined by this method.
1535 virtual ArrayRef>
1536 getSerializableBitmaskMachineOperandTargetFlags() const {
1537 return None;
1538 }
1539
1540 /// Return an array that contains the MMO target flag values and their
1541 /// names.
1542 ///
1543 /// MIR Serialization is able to serialize only the MMO target flags that are
1544 /// defined by this method.
1545 virtual ArrayRef>
1546 getSerializableMachineMemOperandTargetFlags() const {
1547 return None;
1548 }
1549
1550 /// Determines whether \p Inst is a tail call instruction. Override this
1551 /// method on targets that do not properly set MCID::Return and MCID::Call on
1552 /// tail call instructions."
1553 virtual bool isTailCall(const MachineInstr &Inst) const {
1554 return Inst.isReturn() && Inst.isCall();
1555 }
1556
1557 /// True if the instruction is bound to the top of its basic block and no
1558 /// other instructions shall be inserted before it. This can be implemented
1559 /// to prevent register allocator to insert spills before such instructions.
1560 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1561 return false;
1562 }
1563
1564 /// \brief Describes the number of instructions that it will take to call and
1565 /// construct a frame for a given outlining candidate.
1566 struct MachineOutlinerInfo {
1567 /// Number of instructions to call an outlined function for this candidate.
1568 unsigned CallOverhead;
1569
1570 /// \brief Number of instructions to construct an outlined function frame
1571 /// for this candidate.
1572 unsigned FrameOverhead;
1573
1574 /// \brief Represents the specific instructions that must be emitted to
1575 /// construct a call to this candidate.
1576 unsigned CallConstructionID;
1577
1578 /// \brief Represents the specific instructions that must be emitted to
1579 /// construct a frame for this candidate's outlined function.
1580 unsigned FrameConstructionID;
1581
1582 MachineOutlinerInfo() {}
1583 MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
1584 unsigned CallConstructionID,
1585 unsigned FrameConstructionID)
1586 : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
1587 CallConstructionID(CallConstructionID),
1588 FrameConstructionID(FrameConstructionID) {}
1589 };
1590
1591 /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
1592 /// information for a set of outlining candidates.
1593 virtual MachineOutlinerInfo getOutlininingCandidateInfo(
1594 std::vector<
1595 std::pair>
1596 &RepeatedSequenceLocs) const {
1597 llvm_unreachable(
1598 "Target didn't implement TargetInstrInfo::getOutliningOverhead!");
1599 }
1600
1601 /// Represents how an instruction should be mapped by the outliner.
1602 /// \p Legal instructions are those which are safe to outline.
1603 /// \p Illegal instructions are those which cannot be outlined.
1604 /// \p Invisible instructions are instructions which can be outlined, but
1605 /// shouldn't actually impact the outlining result.
1606 enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
1607
1608 /// Returns how or if \p MI should be outlined.
1609 virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
1610 llvm_unreachable(
1611 "Target didn't implement TargetInstrInfo::getOutliningType!");
1612 }
1613
1614 /// Insert a custom epilogue for outlined functions.
1615 /// This may be empty, in which case no epilogue or return statement will be
1616 /// emitted.
1617 virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
1618 MachineFunction &MF,
1619 const MachineOutlinerInfo &MInfo) const {
1620 llvm_unreachable(
1621 "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
1622 }
1623
1624 /// Insert a call to an outlined function into the program.
1625 /// Returns an iterator to the spot where we inserted the call. This must be
1626 /// implemented by the target.
1627 virtual MachineBasicBlock::iterator
1628 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1629 MachineBasicBlock::iterator &It, MachineFunction &MF,
1630 const MachineOutlinerInfo &MInfo) const {
1631 llvm_unreachable(
1632 "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1633 }
1634
1635 /// Insert a custom prologue for outlined functions.
1636 /// This may be empty, in which case no prologue will be emitted.
1637 virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
1638 MachineFunction &MF,
1639 const MachineOutlinerInfo &MInfo) const {
1640 llvm_unreachable(
1641 "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
1642 }
1643
1644 /// Return true if the function can safely be outlined from.
1645 /// A function \p MF is considered safe for outlining if an outlined function
1646 /// produced from instructions in F will produce a program which produces the
1647 /// same output for any set of given inputs.
1648 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
1649 bool OutlineFromLinkOnceODRs) const {
1650 llvm_unreachable("Target didn't implement "
1651 "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1652 }
1653
1654 private:
1655 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1656 unsigned CatchRetOpcode;
1657 unsigned ReturnOpcode;
1658 };
1659
1660 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1661 template <> struct DenseMapInfo {
1662 using RegInfo = DenseMapInfo;
1663
1664 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1665 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1666 RegInfo::getEmptyKey());
1667 }
1668
1669 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1670 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1671 RegInfo::getTombstoneKey());
1672 }
1673
1674 /// \brief Reuse getHashValue implementation from
1675 /// std::pair.
1676 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1677 std::pair PairVal = std::make_pair(Val.Reg, Val.SubReg);
1678 return DenseMapInfo>::getHashValue(PairVal);
1679 }
1680
1681 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1682 const TargetInstrInfo::RegSubRegPair &RHS) {
1683 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1684 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1685 }
1686 };
1687
1688 } // end namespace llvm
1689
1690 #endif // LLVM_TARGET_TARGETINSTRINFO_H
+0
-1691
include/llvm/Target/TargetInstrInfo.h less more
None //===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
14 #define LLVM_TARGET_TARGETINSTRINFO_H
15
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineCombinerPattern.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/Support/BranchProbability.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include
32 #include
33 #include
34 #include
35 #include
36
37 namespace llvm {
38
39 class DFAPacketizer;
40 class InstrItineraryData;
41 class LiveVariables;
42 class MachineMemOperand;
43 class MachineRegisterInfo;
44 class MCAsmInfo;
45 class MCInst;
46 struct MCSchedModel;
47 class Module;
48 class ScheduleDAG;
49 class ScheduleHazardRecognizer;
50 class SDNode;
51 class SelectionDAG;
52 class RegScavenger;
53 class TargetRegisterClass;
54 class TargetRegisterInfo;
55 class TargetSchedModel;
56 class TargetSubtargetInfo;
57
58 template class SmallVectorImpl;
59
60 //---------------------------------------------------------------------------
61 ///
62 /// TargetInstrInfo - Interface to description of machine instruction set
63 ///
64 class TargetInstrInfo : public MCInstrInfo {
65 public:
66 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
67 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
68 : CallFrameSetupOpcode(CFSetupOpcode),
69 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
70 ReturnOpcode(ReturnOpcode) {}
71 TargetInstrInfo(const TargetInstrInfo &) = delete;
72 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
73 virtual ~TargetInstrInfo();
74
75 static bool isGenericOpcode(unsigned Opc) {
76 return Opc <= TargetOpcode::GENERIC_OP_END;
77 }
78
79 /// Given a machine instruction descriptor, returns the register
80 /// class constraint for OpNum, or NULL.
81 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
82 const TargetRegisterInfo *TRI,
83 const MachineFunction &MF) const;
84
85 /// Return true if the instruction is trivially rematerializable, meaning it
86 /// has no side effects and requires no operands that aren't always available.
87 /// This means the only allowed uses are constants and unallocatable physical
88 /// registers so that the instructions result is independent of the place
89 /// in the function.
90 bool isTriviallyReMaterializable(const MachineInstr &MI,
91 AliasAnalysis *AA = nullptr) const {
92 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
93 (MI.getDesc().isRematerializable() &&
94 (isReallyTriviallyReMaterializable(MI, AA) ||
95 isReallyTriviallyReMaterializableGeneric(MI, AA)));
96 }
97
98 protected:
99 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
100 /// set, this hook lets the target specify whether the instruction is actually
101 /// trivially rematerializable, taking into consideration its operands. This
102 /// predicate must return false if the instruction has any side effects other
103 /// than producing a value, or if it requres any address registers that are
104 /// not always available.
105 /// Requirements must be check as stated in isTriviallyReMaterializable() .
106 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
107 AliasAnalysis *AA) const {
108 return false;
109 }
110
111 /// This method commutes the operands of the given machine instruction MI.
112 /// The operands to be commuted are specified by their indices OpIdx1 and
113 /// OpIdx2.
114 ///
115 /// If a target has any instructions that are commutable but require
116 /// converting to different instructions or making non-trivial changes
117 /// to commute them, this method can be overloaded to do that.
118 /// The default implementation simply swaps the commutable operands.
119 ///
120 /// If NewMI is false, MI is modified in place and returned; otherwise, a
121 /// new machine instruction is created and returned.
122 ///
123 /// Do not call this method for a non-commutable instruction.
124 /// Even though the instruction is commutable, the method may still
125 /// fail to commute the operands, null pointer is returned in such cases.
126 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
127 unsigned OpIdx1,
128 unsigned OpIdx2) const;
129
130 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
131 /// operand indices to (ResultIdx1, ResultIdx2).
132 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
133 /// predefined to some indices or be undefined (designated by the special
134 /// value 'CommuteAnyOperandIndex').
135 /// The predefined result indices cannot be re-defined.
136 /// The function returns true iff after the result pair redefinition
137 /// the fixed result pair is equal to or equivalent to the source pair of
138 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
139 /// the pairs (x,y) and (y,x) are equivalent.
140 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
141 unsigned CommutableOpIdx1,
142 unsigned CommutableOpIdx2);
143
144 private:
145 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
146 /// set and the target hook isReallyTriviallyReMaterializable returns false,
147 /// this function does target-independent tests to determine if the
148 /// instruction is really trivially rematerializable.
149 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
150 AliasAnalysis *AA) const;
151
152 public:
153 /// These methods return the opcode of the frame setup/destroy instructions
154 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
155 /// order to abstract away the difference between operating with a frame
156 /// pointer and operating without, through the use of these two instructions.
157 ///
158 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
159 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
160
161 /// Returns true if the argument is a frame pseudo instruction.
162 bool isFrameInstr(const MachineInstr &I) const {
163 return I.getOpcode() == getCallFrameSetupOpcode() ||
164 I.getOpcode() == getCallFrameDestroyOpcode();
165 }
166
167 /// Returns true if the argument is a frame setup pseudo instruction.
168 bool isFrameSetup(const MachineInstr &I) const {
169 return I.getOpcode() == getCallFrameSetupOpcode();
170 }
171
172 /// Returns size of the frame associated with the given frame instruction.
173 /// For frame setup instruction this is frame that is set up space set up
174 /// after the instruction. For frame destroy instruction this is the frame
175 /// freed by the caller.
176 /// Note, in some cases a call frame (or a part of it) may be prepared prior
177 /// to the frame setup instruction. It occurs in the calls that involve
178 /// inalloca arguments. This function reports only the size of the frame part
179 /// that is set up between the frame setup and destroy pseudo instructions.
180 int64_t getFrameSize(const MachineInstr &I) const {
181 assert(isFrameInstr(I) && "Not a frame instruction");
182 assert(I.getOperand(0).getImm() >= 0);
183 return I.getOperand(0).getImm();
184 }
185
186 /// Returns the total frame size, which is made up of the space set up inside
187 /// the pair of frame start-stop instructions and the space that is set up
188 /// prior to the pair.
189 int64_t getFrameTotalSize(const MachineInstr &I) const {
190 if (isFrameSetup(I)) {
191 assert(I.getOperand(1).getImm() >= 0 &&
192 "Frame size must not be negative");
193 return getFrameSize(I) + I.getOperand(1).getImm();
194 }
195 return getFrameSize(I);
196 }
197
198 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
199 unsigned getReturnOpcode() const { return ReturnOpcode; }
200
201 /// Returns the actual stack pointer adjustment made by an instruction
202 /// as part of a call sequence. By default, only call frame setup/destroy
203 /// instructions adjust the stack, but targets may want to override this
204 /// to enable more fine-grained adjustment, or adjust by a different value.
205 virtual int getSPAdjust(const MachineInstr &MI) const;
206
207 /// Return true if the instruction is a "coalescable" extension instruction.
208 /// That is, it's like a copy where it's legal for the source to overlap the
209 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
210 /// expected the pre-extension value is available as a subreg of the result
211 /// register. This also returns the sub-register index in SubIdx.
212 virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
213 unsigned &DstReg, unsigned &SubIdx) const {
214 return false;
215 }
216
217 /// If the specified machine instruction is a direct
218 /// load from a stack slot, return the virtual or physical register number of
219 /// the destination along with the FrameIndex of the loaded stack slot. If
220 /// not, return 0. This predicate must return 0 if the instruction has
221 /// any side effects other than loading from the stack slot.
222 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
223 int &FrameIndex) const {
224 return 0;
225 }
226
227 /// Check for post-frame ptr elimination stack locations as well.
228 /// This uses a heuristic so it isn't reliable for correctness.
229 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
230 int &FrameIndex) const {
231 return 0;
232 }
233
234 /// If the specified machine instruction has a load from a stack slot,
235 /// return true along with the FrameIndex of the loaded stack slot and the
236 /// machine mem operand containing the reference.
237 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
238 /// any instructions that loads from the stack. This is just a hint, as some
239 /// cases may be missed.
240 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
241 const MachineMemOperand *&MMO,
242 int &FrameIndex) const;
243
244 /// If the specified machine instruction is a direct
245 /// store to a stack slot, return the virtual or physical register number of
246 /// the source reg along with the FrameIndex of the loaded stack slot. If
247 /// not, return 0. This predicate must return 0 if the instruction has
248 /// any side effects other than storing to the stack slot.
249 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
250 int &FrameIndex) const {
251 return 0;
252 }
253
254 /// Check for post-frame ptr elimination stack locations as well.
255 /// This uses a heuristic, so it isn't reliable for correctness.
256 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
257 int &FrameIndex) const {
258 return 0;
259 }
260
261 /// If the specified machine instruction has a store to a stack slot,
262 /// return true along with the FrameIndex of the loaded stack slot and the
263 /// machine mem operand containing the reference.
264 /// If not, return false. Unlike isStoreToStackSlot,
265 /// this returns true for any instructions that stores to the
266 /// stack. This is just a hint, as some cases may be missed.
267 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
268 const MachineMemOperand *&MMO,
269 int &FrameIndex) const;
270
271 /// Return true if the specified machine instruction
272 /// is a copy of one stack slot to another and has no other effect.
273 /// Provide the identity of the two frame indices.
274 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
275 int &SrcFrameIndex) const {
276 return false;
277 }
278
279 /// Compute the size in bytes and offset within a stack slot of a spilled
280 /// register or subregister.
281 ///
282 /// \param [out] Size in bytes of the spilled value.
283 /// \param [out] Offset in bytes within the stack slot.
284 /// \returns true if both Size and Offset are successfully computed.
285 ///
286 /// Not all subregisters have computable spill slots. For example,
287 /// subregisters registers may not be byte-sized, and a pair of discontiguous
288 /// subregisters has no single offset.
289 ///
290 /// Targets with nontrivial bigendian implementations may need to override
291 /// this, particularly to support spilled vector registers.
292 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
293 unsigned &Size, unsigned &Offset,
294 const MachineFunction &MF) const;
295
296 /// Returns the size in bytes of the specified MachineInstr, or ~0U
297 /// when this function is not implemented by a target.
298 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
299 return ~0U;
300 }
301
302 /// Return true if the instruction is as cheap as a move instruction.
303 ///
304 /// Targets for different archs need to override this, and different
305 /// micro-architectures can also be finely tuned inside.
306 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
307 return MI.isAsCheapAsAMove();
308 }
309
310 /// Return true if the instruction should be sunk by MachineSink.
311 ///
312 /// MachineSink determines on its own whether the instruction is safe to sink;
313 /// this gives the target a hook to override the default behavior with regards
314 /// to which instructions should be sunk.
315 virtual bool shouldSink(const MachineInstr &MI) const { return true; }
316
317 /// Re-issue the specified 'original' instruction at the
318 /// specific location targeting a new destination register.
319 /// The register in Orig->getOperand(0).getReg() will be substituted by
320 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
321 /// SubIdx.
322 virtual void reMaterialize(MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator MI, unsigned DestReg,
324 unsigned SubIdx, const MachineInstr &Orig,
325 const TargetRegisterInfo &TRI) const;
326
327 /// \brief Clones instruction or the whole instruction bundle \p Orig and
328 /// insert into \p MBB before \p InsertBefore. The target may update operands
329 /// that are required to be unique.
330 ///
331 /// \p Orig must not return true for MachineInstr::isNotDuplicable().
332 virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator InsertBefore,
334 const MachineInstr &Orig) const;
335
336 /// This method must be implemented by targets that
337 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
338 /// may be able to convert a two-address instruction into one or more true
339 /// three-address instructions on demand. This allows the X86 target (for
340 /// example) to convert ADD and SHL instructions into LEA instructions if they
341 /// would require register copies due to two-addressness.
342 ///
343 /// This method returns a null pointer if the transformation cannot be
344 /// performed, otherwise it returns the last new instruction.
345 ///
346 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
347 MachineInstr &MI,
348 LiveVariables *LV) const {
349 return nullptr;
350 }
351
352 // This constant can be used as an input value of operand index passed to
353 // the method findCommutedOpIndices() to tell the method that the
354 // corresponding operand index is not pre-defined and that the method
355 // can pick any commutable operand.
356 static const unsigned CommuteAnyOperandIndex = ~0U;
357
358 /// This method commutes the operands of the given machine instruction MI.
359 ///
360 /// The operands to be commuted are specified by their indices OpIdx1 and
361 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
362 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
363 /// any arbitrarily chosen commutable operand. If both arguments are set to
364 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
365 /// operands; then commutes them if such operands could be found.
366 ///
367 /// If NewMI is false, MI is modified in place and returned; otherwise, a
368 /// new machine instruction is created and returned.
369 ///
370 /// Do not call this method for a non-commutable instruction or
371 /// for non-commuable operands.
372 /// Even though the instruction is commutable, the method may still
373 /// fail to commute the operands, null pointer is returned in such cases.
374 MachineInstr *
375 commuteInstruction(MachineInstr &MI, bool NewMI = false,
376 unsigned OpIdx1 = CommuteAnyOperandIndex,
377 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
378
379 /// Returns true iff the routine could find two commutable operands in the
380 /// given machine instruction.
381 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
382 /// If any of the INPUT values is set to the special value
383 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
384 /// operand, then returns its index in the corresponding argument.
385 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
386 /// looks for 2 commutable operands.
387 /// If INPUT values refer to some operands of MI, then the method simply
388 /// returns true if the corresponding operands are commutable and returns
389 /// false otherwise.
390 ///
391 /// For example, calling this method this way:
392 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
393 /// findCommutedOpIndices(MI, Op1, Op2);
394 /// can be interpreted as a query asking to find an operand that would be
395 /// commutable with the operand#1.
396 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
397 unsigned &SrcOpIdx2) const;
398
399 /// A pair composed of a register and a sub-register index.
400 /// Used to give some type checking when modeling Reg:SubReg.
401 struct RegSubRegPair {
402 unsigned Reg;
403 unsigned SubReg;
404
405 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
406 : Reg(Reg), SubReg(SubReg) {}
407 };
408
409 /// A pair composed of a pair of a register and a sub-register index,
410 /// and another sub-register index.
411 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
412 struct RegSubRegPairAndIdx : RegSubRegPair {
413 unsigned SubIdx;
414
415 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
416 unsigned SubIdx = 0)
417 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
418 };
419
420 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
421 /// and \p DefIdx.
422 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
423 /// the list is modeled as .
424 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
425 /// two elements:
426 /// - vreg1:sub1, sub0
427 /// - vreg2<:0>, sub1
428 ///
429 /// \returns true if it is possible to build such an input sequence
430 /// with the pair \p MI, \p DefIdx. False otherwise.
431 ///
432 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
433 ///
434 /// \note The generic implementation does not provide any support for
435 /// MI.isRegSequenceLike(). In other words, one has to override
436 /// getRegSequenceLikeInputs for target specific instructions.
437 bool
438 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
439 SmallVectorImpl &InputRegs) const;
440
441 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
442 /// and \p DefIdx.
443 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
444 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
445 /// - vreg1:sub1, sub0
446 ///
447 /// \returns true if it is possible to build such an input sequence
448 /// with the pair \p MI, \p DefIdx. False otherwise.
449 ///
450 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
451 ///
452 /// \note The generic implementation does not provide any support for
453 /// MI.isExtractSubregLike(). In other words, one has to override
454 /// getExtractSubregLikeInputs for target specific instructions.
455 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
456 RegSubRegPairAndIdx &InputReg) const;
457
458 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
459 /// and \p DefIdx.
460 /// \p [out] BaseReg and \p [out] InsertedReg contain
461 /// the equivalent inputs of INSERT_SUBREG.
462 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
463 /// - BaseReg: vreg0:sub0
464 /// - InsertedReg: vreg1:sub1, sub3
465 ///
466 /// \returns true if it is possible to build such an input sequence
467 /// with the pair \p MI, \p DefIdx. False otherwise.
468 ///
469 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
470 ///
471 /// \note The generic implementation does not provide any support for
472 /// MI.isInsertSubregLike(). In other words, one has to override
473 /// getInsertSubregLikeInputs for target specific instructions.
474 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
475 RegSubRegPair &BaseReg,
476 RegSubRegPairAndIdx &InsertedReg) const;
477
478 /// Return true if two machine instructions would produce identical values.
479 /// By default, this is only true when the two instructions
480 /// are deemed identical except for defs. If this function is called when the
481 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
482 /// aggressive checks.
483 virtual bool produceSameValue(const MachineInstr &MI0,
484 const MachineInstr &MI1,
485 const MachineRegisterInfo *MRI = nullptr) const;
486
487 /// \returns true if a branch from an instruction with opcode \p BranchOpc
488 /// bytes is capable of jumping to a position \p BrOffset bytes away.
489 virtual bool isBranchOffsetInRange(unsigned BranchOpc,
490 int64_t BrOffset) const {
491 llvm_unreachable("target did not implement");
492 }
493
494 /// \returns The block that branch instruction \p MI jumps to.
495 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
496 llvm_unreachable("target did not implement");
497 }
498
499 /// Insert an unconditional indirect branch at the end of \p MBB to \p
500 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
501 /// the offset of the position to insert the new branch.
502 ///
503 /// \returns The number of bytes added to the block.
504 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
505 MachineBasicBlock &NewDestBB,
506 const DebugLoc &DL,
507 int64_t BrOffset = 0,
508 RegScavenger *RS = nullptr) const {
509 llvm_unreachable("target did not implement");
510 }
511
512 /// Analyze the branching code at the end of MBB, returning
513 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
514 /// implemented for a target). Upon success, this returns false and returns
515 /// with the following information in various cases:
516 ///
517 /// 1. If this block ends with no branches (it just falls through to its succ)
518 /// just return false, leaving TBB/FBB null.
519 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
520 /// the destination block.
521 /// 3. If this block ends with a conditional branch and it falls through to a
522 /// successor block, it sets TBB to be the branch destination block and a
523 /// list of operands that evaluate the condition. These operands can be
524 /// passed to other TargetInstrInfo methods to create new branches.
525 /// 4. If this block ends with a conditional branch followed by an
526 /// unconditional branch, it returns the 'true' destination in TBB, the
527 /// 'false' destination in FBB, and a list of operands that evaluate the
528 /// condition. These operands can be passed to other TargetInstrInfo
529 /// methods to create new branches.
530 ///
531 /// Note that removeBranch and insertBranch must be implemented to support
532 /// cases where this method returns success.
533 ///
534 /// If AllowModify is true, then this routine is allowed to modify the basic
535 /// block (e.g. delete instructions after the unconditional branch).
536 ///
537 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
538 /// before calling this function.
539 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
540 MachineBasicBlock *&FBB,
541 SmallVectorImpl &Cond,
542 bool AllowModify = false) const {
543 return true;
544 }
545
546 /// Represents a predicate at the MachineFunction level. The control flow a
547 /// MachineBranchPredicate represents is:
548 ///
549 /// Reg = LHS `Predicate` RHS == ConditionDef
550 /// if Reg then goto TrueDest else goto FalseDest
551 ///
552 struct MachineBranchPredicate {
553 enum ComparePredicate {
554 PRED_EQ, // True if two values are equal
555 PRED_NE, // True if two values are not equal
556 PRED_INVALID // Sentinel value
557 };
558
559 ComparePredicate Predicate = PRED_INVALID;
560 MachineOperand LHS = MachineOperand::CreateImm(0);
561 MachineOperand RHS = MachineOperand::CreateImm(0);
562 MachineBasicBlock *TrueDest = nullptr;
563 MachineBasicBlock *FalseDest = nullptr;
564 MachineInstr *ConditionDef = nullptr;
565
566 /// SingleUseCondition is true if ConditionDef is dead except for the
567 /// branch(es) at the end of the basic block.
568 ///
569 bool SingleUseCondition = false;
570
571 explicit MachineBranchPredicate() = default;
572 };
573
574 /// Analyze the branching code at the end of MBB and parse it into the
575 /// MachineBranchPredicate structure if possible. Returns false on success
576 /// and true on failure.
577 ///
578 /// If AllowModify is true, then this routine is allowed to modify the basic
579 /// block (e.g. delete instructions after the unconditional branch).
580 ///
581 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
582 MachineBranchPredicate &MBP,
583 bool AllowModify = false) const {
584 return true;
585 }
586
587 /// Remove the branching code at the end of the specific MBB.
588 /// This is only invoked in cases where AnalyzeBranch returns success. It
589 /// returns the number of instructions that were removed.
590 /// If \p BytesRemoved is non-null, report the change in code size from the
591 /// removed instructions.
592 virtual unsigned removeBranch(MachineBasicBlock &MBB,
593 int *BytesRemoved = nullptr) const {
594 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
595 }
596
597 /// Insert branch code into the end of the specified MachineBasicBlock. The
598 /// operands to this method are the same as those returned by AnalyzeBranch.
599 /// This is only invoked in cases where AnalyzeBranch returns success. It
600 /// returns the number of instructions inserted. If \p BytesAdded is non-null,
601 /// report the change in code size from the added instructions.
602 ///
603 /// It is also invoked by tail merging to add unconditional branches in
604 /// cases where AnalyzeBranch doesn't apply because there was no original
605 /// branch to analyze. At least this much must be implemented, else tail
606 /// merging needs to be disabled.
607 ///
608 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
609 /// before calling this function.
610 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
611 MachineBasicBlock *FBB,
612 ArrayRef Cond,
613 const DebugLoc &DL,
614 int *BytesAdded = nullptr) const {
615 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
616 }
617
618 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
619 MachineBasicBlock *DestBB,
620 const DebugLoc &DL,
621 int *BytesAdded = nullptr) const {
622 return insertBranch(MBB, DestBB, nullptr, ArrayRef(), DL,
623 BytesAdded);
624 }
625
626 /// Analyze the loop code, return true if it cannot be understoo. Upon
627 /// success, this function returns false and returns information about the
628 /// induction variable and compare instruction used at the end.
629 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
630 MachineInstr *&CmpInst) const {
631 return true;
632 }
633
634 /// Generate code to reduce the loop iteration by one and check if the loop is
635 /// finished. Return the value/register of the the new loop count. We need
636 /// this function when peeling off one or more iterations of a loop. This
637 /// function assumes the nth iteration is peeled first.
638 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
639 MachineInstr &Cmp,
640 SmallVectorImpl &Cond,
641 SmallVectorImpl &PrevInsts,
642 unsigned Iter, unsigned MaxIter) const {
643 llvm_unreachable("Target didn't implement ReduceLoopCount");
644 }
645
646 /// Delete the instruction OldInst and everything after it, replacing it with
647 /// an unconditional branch to NewDest. This is used by the tail merging pass.
648 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
649 MachineBasicBlock *NewDest) const;
650
651 /// Return true if it's legal to split the given basic
652 /// block at the specified instruction (i.e. instruction would be the start
653 /// of a new basic block).
654 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator MBBI) const {
656 return true;
657 }
658
659 /// Return true if it's profitable to predicate
660 /// instructions with accumulated instruction latency of "NumCycles"
661 /// of the specified basic block, where the probability of the instructions
662 /// being executed is given by Probability, and Confidence is a measure
663 /// of our confidence that it will be properly predicted.
664 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
665 unsigned ExtraPredCycles,
666 BranchProbability Probability) const {
667 return false;
668 }
669
670 /// Second variant of isProfitableToIfCvt. This one
671 /// checks for the case where two basic blocks from true and false path
672 /// of a if-then-else (diamond) are predicated on mutally exclusive
673 /// predicates, where the probability of the true path being taken is given
674 /// by Probability, and Confidence is a measure of our confidence that it
675 /// will be properly predicted.
676 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
677 unsigned ExtraTCycles,
678 MachineBasicBlock &FMBB, unsigned NumFCycles,
679 unsigned ExtraFCycles,
680 BranchProbability Probability) const {
681 return false;
682 }
683
684 /// Return true if it's profitable for if-converter to duplicate instructions
685 /// of specified accumulated instruction latencies in the specified MBB to
686 /// enable if-conversion.
687 /// The probability of the instructions being executed is given by
688 /// Probability, and Confidence is a measure of our confidence that it
689 /// will be properly predicted.
690 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
691 unsigned NumCycles,
692 BranchProbability Probability) const {
693 return false;
694 }
695
696 /// Return true if it's profitable to unpredicate
697 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
698 /// exclusive predicates.
699 /// e.g.
700 /// subeq r0, r1, #1
701 /// addne r0, r1, #1
702 /// =>
703 /// sub r0, r1, #1
704 /// addne r0, r1, #1
705 ///
706 /// This may be profitable is conditional instructions are always executed.
707 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
708 MachineBasicBlock &FMBB) const {
709 return false;
710 }
711
712 /// Return true if it is possible to insert a select
713 /// instruction that chooses between TrueReg and FalseReg based on the
714 /// condition code in Cond.
715 ///
716 /// When successful, also return the latency in cycles from TrueReg,
717 /// FalseReg, and Cond to the destination register. In most cases, a select
718 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
719 ///
720 /// Some x86 implementations have 2-cycle cmov instructions.
721 ///
722 /// @param MBB Block where select instruction would be inserted.
723 /// @param Cond Condition returned by AnalyzeBranch.
724 /// @param TrueReg Virtual register to select when Cond is true.
725 /// @param FalseReg Virtual register to select when Cond is false.
726 /// @param CondCycles Latency from Cond+Branch to select output.
727 /// @param TrueCycles Latency from TrueReg to select output.
728 /// @param FalseCycles Latency from FalseReg to select output.
729 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
730 ArrayRef Cond, unsigned TrueReg,
731 unsigned FalseReg, int &CondCycles,
732 int &TrueCycles, int &FalseCycles) const {
733 return false;
734 }
735
736 /// Insert a select instruction into MBB before I that will copy TrueReg to
737 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
738 ///
739 /// This function can only be called after canInsertSelect() returned true.
740 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
741 /// that the same flags or registers required by Cond are available at the
742 /// insertion point.
743 ///
744 /// @param MBB Block where select instruction should be inserted.
745 /// @param I Insertion point.
746 /// @param DL Source location for debugging.
747 /// @param DstReg Virtual register to be defined by select instruction.
748 /// @param Cond Condition as computed by AnalyzeBranch.
749 /// @param TrueReg Virtual register to copy when Cond is true.
750 /// @param FalseReg Virtual register to copy when Cons is false.
751 virtual void insertSelect(MachineBasicBlock &MBB,
752 MachineBasicBlock::iterator I, const DebugLoc &DL,
753 unsigned DstReg, ArrayRef Cond,
754 unsigned TrueReg, unsigned FalseReg) const {
755 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
756 }
757
758 /// Analyze the given select instruction, returning true if
759 /// it cannot be understood. It is assumed that MI->isSelect() is true.
760 ///
761 /// When successful, return the controlling condition and the operands that
762 /// determine the true and false result values.
763 ///
764 /// Result = SELECT Cond, TrueOp, FalseOp
765 ///
766 /// Some targets can optimize select instructions, for example by predicating
767 /// the instruction defining one of the operands. Such targets should set
768 /// Optimizable.
769 ///
770 /// @param MI Select instruction to analyze.
771 /// @param Cond Condition controlling the select.
772 /// @param TrueOp Operand number of the value selected when Cond is true.
773 /// @param FalseOp Operand number of the value selected when Cond is false.
774 /// @param Optimizable Returned as true if MI is optimizable.
775 /// @returns False on success.
776 virtual bool analyzeSelect(const MachineInstr &MI,
777 SmallVectorImpl &Cond,
778 unsigned &TrueOp, unsigned &FalseOp,
779 bool &Optimizable) const {
780 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
781 return true;
782 }
783
784 /// Given a select instruction that was understood by
785 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
786 /// merging it with one of its operands. Returns NULL on failure.
787 ///
788 /// When successful, returns the new select instruction. The client is
789 /// responsible for deleting MI.
790 ///
791 /// If both sides of the select can be optimized, PreferFalse is used to pick
792 /// a side.
793 ///
794 /// @param MI Optimizable select instruction.
795 /// @param NewMIs Set that record all MIs in the basic block up to \p
796 /// MI. Has to be updated with any newly created MI or deleted ones.
797 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
798 /// @returns Optimized instruction or NULL.
799 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
800 SmallPtrSetImpl &NewMIs,
801 bool PreferFalse = false) const {
802 // This function must be implemented if Optimizable is ever set.
803 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
804 }
805
806 /// Emit instructions to copy a pair of physical registers.
807 ///
808 /// This function should support copies within any legal register class as
809 /// well as any cross-class copies created during instruction selection.
810 ///
811 /// The source and destination registers may overlap, which may require a
812 /// careful implementation when multiple copy instructions are required for
813 /// large registers. See for example the ARM target.
814 virtual void copyPhysReg(MachineBasicBlock &MBB,
815 MachineBasicBlock::iterator MI, const DebugLoc &DL,
816 unsigned DestReg, unsigned SrcReg,
817 bool KillSrc) const {
818 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
819 }
820
821 /// Store the specified register of the given register class to the specified
822 /// stack frame index. The store instruction is to be added to the given
823 /// machine basic block before the specified machine instruction. If isKill
824 /// is true, the register operand is the last use and must be marked kill.
825 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
826 MachineBasicBlock::iterator MI,
827 unsigned SrcReg, bool isKill, int FrameIndex,
828 const TargetRegisterClass *RC,
829 const TargetRegisterInfo *TRI) const {
830 llvm_unreachable("Target didn't implement "
831 "TargetInstrInfo::storeRegToStackSlot!");
832 }
833
834 /// Load the specified register of the given register class from the specified
835 /// stack frame index. The load instruction is to be added to the given
836 /// machine basic block before the specified machine instruction.
837 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
838 MachineBasicBlock::iterator MI,
839 unsigned DestReg, int FrameIndex,
840 const TargetRegisterClass *RC,
841 const TargetRegisterInfo *TRI) const {
842 llvm_unreachable("Target didn't implement "
843 "TargetInstrInfo::loadRegFromStackSlot!");
844 }
845
846 /// This function is called for all pseudo instructions
847 /// that remain after register allocation. Many pseudo instructions are
848 /// created to help register allocation. This is the place to convert them
849 /// into real instructions. The target can edit MI in place, or it can insert
850 /// new instructions and erase MI. The function should return true if
851 /// anything was changed.
852 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
853
854 /// Check whether the target can fold a load that feeds a subreg operand
855 /// (or a subreg operand that feeds a store).
856 /// For example, X86 may want to return true if it can fold
857 /// movl (%esp), %eax
858 /// subb, %al, ...
859 /// Into:
860 /// subb (%esp), ...
861 ///
862 /// Ideally, we'd like the target implementation of foldMemoryOperand() to
863 /// reject subregs - but since this behavior used to be enforced in the
864 /// target-independent code, moving this responsibility to the targets
865 /// has the potential of causing nasty silent breakage in out-of-tree targets.
866 virtual bool isSubregFoldable() const { return false; }
867
868 /// Attempt to fold a load or store of the specified stack
869 /// slot into the specified machine instruction for the specified operand(s).
870 /// If this is possible, a new instruction is returned with the specified
871 /// operand folded, otherwise NULL is returned.
872 /// The new instruction is inserted before MI, and the client is responsible
873 /// for removing the old instruction.
874 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
875 int FrameIndex,
876 LiveIntervals *LIS = nullptr) const;
877
878 /// Same as the previous version except it allows folding of any load and
879 /// store from / to any address, not just from a specific stack slot.
880 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
881 MachineInstr &LoadMI,
882 LiveIntervals *LIS = nullptr) const;
883
884 /// Return true when there is potentially a faster code sequence
885 /// for an instruction chain ending in \p Root. All potential patterns are
886 /// returned in the \p Pattern vector. Pattern should be sorted in priority
887 /// order since the pattern evaluator stops checking as soon as it finds a
888 /// faster sequence.
889 /// \param Root - Instruction that could be combined with one of its operands
890 /// \param Patterns - Vector of possible combination patterns
891 virtual bool getMachineCombinerPatterns(
892 MachineInstr &Root,
893 SmallVectorImpl &Patterns) const;
894
895 /// Return true when a code sequence can improve throughput. It
896 /// should be called only for instructions in loops.
897 /// \param Pattern - combiner pattern
898 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
899
900 /// Return true if the input \P Inst is part of a chain of dependent ops
901 /// that are suitable for reassociation, otherwise return false.
902 /// If the instruction's operands must be commuted to have a previous
903 /// instruction of the same type define the first source operand, \P Commuted
904 /// will be set to true.
905 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
906
907 /// Return true when \P Inst is both associative and commutative.
908 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
909 return false;
910 }
911
912 /// Return true when \P Inst has reassociable operands in the same \P MBB.
913 virtual bool hasReassociableOperands(const MachineInstr &Inst,
914 const MachineBasicBlock *MBB) const;
915
916 /// Return true when \P Inst has reassociable sibling.
917 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
918
919 /// When getMachineCombinerPatterns() finds patterns, this function generates
920 /// the instructions that could replace the original code sequence. The client
921 /// has to decide whether the actual replacement is beneficial or not.
922 /// \param Root - Instruction that could be combined with one of its operands
923 /// \param Pattern - Combination pattern for Root
924 /// \param InsInstrs - Vector of new instructions that implement P
925 /// \param DelInstrs - Old instructions, including Root, that could be
926 /// replaced by InsInstr
927 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
928 /// InsInstr that defines it
929 virtual void genAlternativeCodeSequence(
930 MachineInstr &Root, MachineCombinerPattern Pattern,
931 SmallVectorImpl &InsInstrs,
932 SmallVectorImpl &DelInstrs,
933 DenseMap &InstrIdxForVirtReg) const;
934
935 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
936 /// reduce critical path length.
937 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
938 MachineCombinerPattern Pattern,
939 SmallVectorImpl &InsInstrs,
940 SmallVectorImpl &DelInstrs,
941 DenseMap &InstrIdxForVirtReg) const;
942
943 /// This is an architecture-specific helper function of reassociateOps.
944 /// Set special operand attributes for new instructions after reassociation.
945 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
946 MachineInstr &NewMI1,
947 MachineInstr &NewMI2) const {}
948
949 /// Return true when a target supports MachineCombiner.
950 virtual bool useMachineCombiner() const { return false; }
951
952 protected:
953 /// Target-dependent implementation for foldMemoryOperand.
954 /// Target-independent code in foldMemoryOperand will
955 /// take care of adding a MachineMemOperand to the newly created instruction.
956 /// The instruction and any auxiliary instructions necessary will be inserted
957 /// at InsertPt.
958 virtual MachineInstr *
959 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
960 ArrayRef Ops,
961 MachineBasicBlock::iterator InsertPt, int FrameIndex,
962 LiveIntervals *LIS = nullptr) const {
963 return nullptr;
964 }
965
966 /// Target-dependent implementation for foldMemoryOperand.
967 /// Target-independent code in foldMemoryOperand will
968 /// take care of adding a MachineMemOperand to the newly created instruction.
969 /// The instruction and any auxiliary instructions necessary will be inserted
970 /// at InsertPt.
971 virtual MachineInstr *foldMemoryOperandImpl(
972 MachineFunction &MF, MachineInstr &MI, ArrayRef Ops,
973 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
974 LiveIntervals *LIS = nullptr) const {
975 return nullptr;
976 }
977
978 /// \brief Target-dependent implementation of getRegSequenceInputs.
979 ///
980 /// \returns true if it is possible to build the equivalent
981 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
982 ///
983 /// \pre MI.isRegSequenceLike().
984 ///
985 /// \see TargetInstrInfo::getRegSequenceInputs.
986 virtual bool getRegSequenceLikeInputs(
987 const MachineInstr &MI, unsigned DefIdx,
988 SmallVectorImpl &InputRegs) const {
989 return false;
990 }
991
992 /// \brief Target-dependent implementation of getExtractSubregInputs.
993 ///
994 /// \returns true if it is possible to build the equivalent
995 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
996 ///
997 /// \pre MI.isExtractSubregLike().
998 ///
999 /// \see TargetInstrInfo::getExtractSubregInputs.
1000 virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1001 unsigned DefIdx,
1002 RegSubRegPairAndIdx &InputReg) const {
1003 return false;
1004 }
1005
1006 /// \brief Target-dependent implementation of getInsertSubregInputs.
1007 ///
1008 /// \returns true if it is possible to build the equivalent
1009 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1010 ///
1011 /// \pre MI.isInsertSubregLike().
1012 ///
1013 /// \see TargetInstrInfo::getInsertSubregInputs.
1014 virtual bool
1015 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1016 RegSubRegPair &BaseReg,
1017 RegSubRegPairAndIdx &InsertedReg) const {
1018 return false;
1019 }
1020
1021 public:
1022 /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1023 /// (e.g. stack) the target returns the corresponding address space.
1024 virtual unsigned
1025 getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
1026 return 0;
1027 }
1028
1029 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1030 /// a store or a load and a store into two or more instruction. If this is
1031 /// possible, returns true as well as the new instructions by reference.
1032 virtual bool
1033 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1034 bool UnfoldLoad, bool UnfoldStore,
1035 SmallVectorImpl &NewMIs) const {
1036 return false;
1037 }
1038
1039 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1040 SmallVectorImpl &NewNodes) const {
1041 return false;
1042 }
1043
1044 /// Returns the opcode of the would be new
1045 /// instruction after load / store are unfolded from an instruction of the
1046 /// specified opcode. It returns zero if the specified unfolding is not
1047 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1048 /// index of the operand which will hold the register holding the loaded
1049 /// value.
1050 virtual unsigned
1051 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1052 unsigned *LoadRegIndex = nullptr) const {
1053 return 0;
1054 }
1055
1056 /// This is used by the pre-regalloc scheduler to determine if two loads are
1057 /// loading from the same base address. It should only return true if the base
1058 /// pointers are the same and the only differences between the two addresses
1059 /// are the offset. It also returns the offsets by reference.
1060 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1061 int64_t &Offset1,
1062 int64_t &Offset2) const {
1063 return false;
1064 }
1065
1066 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1067 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1068 /// On some targets if two loads are loading from
1069 /// addresses in the same cache line, it's better if they are scheduled
1070 /// together. This function takes two integers that represent the load offsets
1071 /// from the common base address. It returns true if it decides it's desirable
1072 /// to schedule the two loads together. "NumLoads" is the number of loads that
1073 /// have already been scheduled after Load1.
1074 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1075 int64_t Offset1, int64_t Offset2,
1076 unsigned NumLoads) const {
1077 return false;
1078 }
1079
1080 /// Get the base register and byte offset of an instruction that reads/writes
1081 /// memory.
1082 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1083 int64_t &Offset,
1084 const TargetRegisterInfo *TRI) const {
1085 return false;
1086 }
1087
1088 /// Return true if the instruction contains a base register and offset. If
1089 /// true, the function also sets the operand position in the instruction
1090 /// for the base register and offset.
1091 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1092 unsigned &BasePos,
1093 unsigned &OffsetPos) const {
1094 return false;
1095 }
1096
1097 /// If the instruction is an increment of a constant value, return the amount.
1098 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1099 return false;
1100 }
1101
1102 /// Returns true if the two given memory operations should be scheduled
1103 /// adjacent. Note that you have to add:
1104 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1105 /// or
1106 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1107 /// to TargetPassConfig::createMachineScheduler() to have an effect.
1108 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
1109 MachineInstr &SecondLdSt, unsigned BaseReg2,
1110 unsigned NumLoads) const {
1111 llvm_unreachable("target did not implement shouldClusterMemOps()");
1112 }
1113
1114 /// Reverses the branch condition of the specified condition list,
1115 /// returning false on success and true if it cannot be reversed.
1116 virtual bool
1117 reverseBranchCondition(SmallVectorImpl &Cond) const {
1118 return true;
1119 }
1120
1121 /// Insert a noop into the instruction stream at the specified point.
1122 virtual void insertNoop(MachineBasicBlock &MBB,
1123 MachineBasicBlock::iterator MI) const;
1124
1125 /// Return the noop instruction to use for a noop.
1126 virtual void getNoop(MCInst &NopInst) const;
1127
1128 /// Return true for post-incremented instructions.
1129 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1130
1131 /// Returns true if the instruction is already predicated.
1132 virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1133
1134 /// Returns true if the instruction is a
1135 /// terminator instruction that has not been predicated.
1136 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1137
1138 /// Returns true if MI is an unconditional tail call.
1139 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1140 return false;
1141 }
1142
1143 /// Returns true if the tail call can be made conditional on BranchCond.
1144 virtual bool canMakeTailCallConditional(SmallVectorImpl &Cond,
1145 const MachineInstr &TailCall) const {
1146 return false;
1147 }
1148
1149 /// Replace the conditional branch in MBB with a conditional tail call.
1150 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1151 SmallVectorImpl &Cond,
1152 const MachineInstr &TailCall) const {
1153 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1154 }
1155
1156 /// Convert the instruction into a predicated instruction.
1157 /// It returns true if the operation was successful.
1158 virtual bool PredicateInstruction(MachineInstr &MI,
1159 ArrayRef Pred) const;
1160
1161 /// Returns true if the first specified predicate
1162 /// subsumes the second, e.g. GE subsumes GT.
1163 virtual bool SubsumesPredicate(ArrayRef Pred1,
1164 ArrayRef Pred2) const {
1165 return false;
1166 }
1167
1168 /// If the specified instruction defines any predicate
1169 /// or condition code register(s) used for predication, returns true as well
1170 /// as the definition predicate(s) by reference.
1171 virtual bool DefinesPredicate(MachineInstr &MI,
1172 std::vector &Pred) const {
1173 return false;
1174 }
1175
1176 /// Return true if the specified instruction can be predicated.
1177 /// By default, this returns true for every instruction with a
1178 /// PredicateOperand.
1179 virtual bool isPredicable(const MachineInstr &MI) const {
1180 return MI.getDesc().isPredicable();
1181 }
1182
1183 /// Return true if it's safe to move a machine
1184 /// instruction that defines the specified register class.
1185 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1186 return true;
1187 }
1188
1189 /// Test if the given instruction should be considered a scheduling boundary.
1190 /// This primarily includes labels and terminators.
1191 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1192 const MachineBasicBlock *MBB,
1193 const MachineFunction &MF) const;
1194
1195 /// Measure the specified inline asm to determine an approximation of its
1196 /// length.
1197 virtual unsigned getInlineAsmLength(const char *Str,
1198 const MCAsmInfo &MAI) const;
1199
1200 /// Allocate and return a hazard recognizer to use for this target when
1201 /// scheduling the machine instructions before register allocation.
1202 virtual ScheduleHazardRecognizer *
1203 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1204 const ScheduleDAG *DAG) const;
1205
1206 /// Allocate and return a hazard recognizer to use for this target when
1207 /// scheduling the machine instructions before register allocation.
1208 virtual ScheduleHazardRecognizer *
1209 CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1210 const ScheduleDAG *DAG) const;
1211
1212 /// Allocate and return a hazard recognizer to use for this target when
1213 /// scheduling the machine instructions after register allocation.
1214 virtual ScheduleHazardRecognizer *
1215 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1216 const ScheduleDAG *DAG) const;
1217
1218 /// Allocate and return a hazard recognizer to use for by non-scheduling
1219 /// passes.
1220 virtual ScheduleHazardRecognizer *
1221 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1222 return nullptr;
1223 }
1224
1225 /// Provide a global flag for disabling the PreRA hazard recognizer that
1226 /// targets may choose to honor.
1227 bool usePreRAHazardRecognizer() const;
1228
1229 /// For a comparison instruction, return the source registers
1230 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1231 /// compares against in CmpValue. Return true if the comparison instruction
1232 /// can be analyzed.
1233 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1234 unsigned &SrcReg2, int &Mask, int &Value) const {
1235 return false;
1236 }
1237
1238 /// See if the comparison instruction can be converted
1239 /// into something more efficient. E.g., on ARM most instructions can set the
1240 /// flags register, obviating the need for a separate CMP.
1241 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1242 unsigned SrcReg2, int Mask, int Value,
1243 const MachineRegisterInfo *MRI) const {
1244 return false;
1245 }
1246 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1247
1248 /// Try to remove the load by folding it to a register operand at the use.
1249 /// We fold the load instructions if and only if the
1250 /// def and use are in the same BB. We only look at one load and see
1251 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1252 /// defined by the load we are trying to fold. DefMI returns the machine
1253 /// instruction that defines FoldAsLoadDefReg, and the function returns
1254 /// the machine instruction generated due to folding.
1255 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1256 const MachineRegisterInfo *MRI,
1257 unsigned &FoldAsLoadDefReg,
1258 MachineInstr *&DefMI) const {
1259 return nullptr;
1260 }
1261
1262 /// 'Reg' is known to be defined by a move immediate instruction,
1263 /// try to fold the immediate into the use instruction.
1264 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1265 /// then the caller may assume that DefMI has been erased from its parent
1266 /// block. The caller may assume that it will not be erased by this
1267 /// function otherwise.
1268 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1269 unsigned Reg, MachineRegisterInfo *MRI) const {
1270 return false;
1271 }
1272
1273 /// Return the number of u-operations the given machine
1274 /// instruction will be decoded to on the target cpu. The itinerary's
1275 /// IssueWidth is the number of microops that can be dispatched each
1276 /// cycle. An instruction with zero microops takes no dispatch resources.
1277 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1278 const MachineInstr &MI) const;
1279
1280 /// Return true for pseudo instructions that don't consume any
1281 /// machine resources in their current form. These are common cases that the
1282 /// scheduler should consider free, rather than conservatively handling them
1283 /// as instructions with no itinerary.
1284 bool isZeroCost(unsigned Opcode) const {
1285 return Opcode <= TargetOpcode::COPY;
1286 }
1287
1288 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1289 SDNode *DefNode, unsigned DefIdx,
1290 SDNode *UseNode, unsigned UseIdx) const;
1291
1292 /// Compute and return the use operand latency of a given pair of def and use.
1293 /// In most cases, the static scheduling itinerary was enough to determine the
1294 /// operand latency. But it may not be possible for instructions with variable
1295 /// number of defs / uses.
1296 ///
1297 /// This is a raw interface to the itinerary that may be directly overridden
1298 /// by a target. Use computeOperandLatency to get the best estimate of
1299 /// latency.
1300 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1301 const MachineInstr &DefMI, unsigned DefIdx,
1302 const MachineInstr &UseMI,
1303 unsigned UseIdx) const;
1304
1305 /// Compute the instruction latency of a given instruction.
1306 /// If the instruction has higher cost when predicated, it's returned via
1307 /// PredCost.
1308 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1309 const MachineInstr &MI,
1310 unsigned *PredCost = nullptr) const;
1311
1312 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1313
1314 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1315 SDNode *Node) const;
1316
1317 /// Return the default expected latency for a def based on its opcode.
1318 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1319 const MachineInstr &DefMI) const;
1320
1321 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1322 const MachineInstr &DefMI) const;
1323
1324 /// Return true if this opcode has high latency to its result.
1325 virtual bool isHighLatencyDef(int opc) const { return false; }
1326
1327 /// Compute operand latency between a def of 'Reg'
1328 /// and a use in the current loop. Return true if the target considered
1329 /// it 'high'. This is used by optimization passes such as machine LICM to
1330 /// determine whether it makes sense to hoist an instruction out even in a
1331 /// high register pressure situation.
1332 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1333 const MachineRegisterInfo *MRI,
1334 const MachineInstr &DefMI, unsigned DefIdx,
1335 const MachineInstr &UseMI,
1336 unsigned UseIdx) const {
1337 return false;
1338 }
1339
1340 /// Compute operand latency of a def of 'Reg'. Return true
1341 /// if the target considered it 'low'.
1342 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1343 const MachineInstr &DefMI,
1344 unsigned DefIdx) const;
1345
1346 /// Perform target-specific instruction verification.
1347 virtual bool verifyInstruction(const MachineInstr &MI,
1348 StringRef &ErrInfo) const {
1349 return true;
1350 }
1351
1352 /// Return the current execution domain and bit mask of
1353 /// possible domains for instruction.
1354 ///
1355 /// Some micro-architectures have multiple execution domains, and multiple
1356 /// opcodes that perform the same operation in different domains. For
1357 /// example, the x86 architecture provides the por, orps, and orpd
1358 /// instructions that all do the same thing. There is a latency penalty if a
1359 /// register is written in one domain and read in another.
1360 ///
1361 /// This function returns a pair (domain, mask) containing the execution
1362 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1363 /// function can be used to change the opcode to one of the domains in the
1364 /// bit mask. Instructions whose execution domain can't be changed should
1365 /// return a 0 mask.
1366 ///
1367 /// The execution domain numbers don't have any special meaning except domain
1368 /// 0 is used for instructions that are not associated with any interesting
1369 /// execution domain.
1370 ///
1371 virtual std::pair
1372 getExecutionDomain(const MachineInstr &MI) const {
1373 return std::make_pair(0, 0);
1374 }
1375
1376 /// Change the opcode of MI to execute in Domain.
1377 ///
1378 /// The bit (1 << Domain) must be set in the mask returned from
1379 /// getExecutionDomain(MI).
1380 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1381
1382 /// Returns the preferred minimum clearance
1383 /// before an instruction with an unwanted partial register update.
1384 ///
1385 /// Some instructions only write part of a register, and implicitly need to
1386 /// read the other parts of the register. This may cause unwanted stalls
1387 /// preventing otherwise unrelated instructions from executing in parallel in
1388 /// an out-of-order CPU.
1389 ///
1390 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1391 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1392 /// the instruction needs to wait for the old value of the register to become
1393 /// available:
1394 ///
1395 /// addps %xmm1, %xmm0
1396 /// movaps %xmm0, (%rax)
1397 /// cvtsi2ss %rbx, %xmm0
1398 ///
1399 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1400 /// instruction before it can issue, even though the high bits of %xmm0
1401 /// probably aren't needed.
1402 ///
1403 /// This hook returns the preferred clearance before MI, measured in
1404 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1405 /// instructions before MI. It should only return a positive value for
1406 /// unwanted dependencies. If the old bits of the defined register have
1407 /// useful values, or if MI is determined to otherwise read the dependency,
1408 /// the hook should return 0.
1409 ///
1410 /// The unwanted dependency may be handled by:
1411 ///
1412 /// 1. Allocating the same register for an MI def and use. That makes the
1413 /// unwanted dependency identical to a required dependency.
1414 ///
1415 /// 2. Allocating a register for the def that has no defs in the previous N
1416 /// instructions.
1417 ///
1418 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1419 /// allows the target to insert a dependency breaking instruction.
1420 ///
1421 virtual unsigned
1422 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1423 const TargetRegisterInfo *TRI) const {
1424 // The default implementation returns 0 for no partial register dependency.
1425 return 0;
1426 }
1427
1428 /// \brief Return the minimum clearance before an instruction that reads an
1429 /// unused register.
1430 ///
1431 /// For example, AVX instructions may copy part of a register operand into
1432 /// the unused high bits of the destination register.
1433 ///
1434 /// vcvtsi2sdq %rax, %xmm0, %xmm14
1435 ///
1436 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1437 /// false dependence on any previous write to %xmm0.
1438 ///
1439 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1440 /// does not take an operand index. Instead sets \p OpNum to the index of the
1441 /// unused register.
1442 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1443 const TargetRegisterInfo *TRI) const {
1444 // The default implementation returns 0 for no undef register dependency.
1445 return 0;
1446 }
1447
1448 /// Insert a dependency-breaking instruction
1449 /// before MI to eliminate an unwanted dependency on OpNum.
1450 ///
1451 /// If it wasn't possible to avoid a def in the last N instructions before MI
1452 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1453 /// unwanted dependency.
1454 ///
1455 /// On x86, an xorps instruction can be used as a dependency breaker:
1456 ///
1457 /// addps %xmm1, %xmm0
1458 /// movaps %xmm0, (%rax)
1459 /// xorps %xmm0, %xmm0
1460 /// cvtsi2ss %rbx, %xmm0
1461 ///
1462 /// An operand should be added to MI if an instruction was
1463 /// inserted. This ties the instructions together in the post-ra scheduler.
1464 ///
1465 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1466 const TargetRegisterInfo *TRI) const {}
1467
1468 /// Create machine specific model for scheduling.
1469 virtual DFAPacketizer *
1470 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1471 return nullptr;
1472 }
1473
1474 /// Sometimes, it is possible for the target
1475 /// to tell, even without aliasing information, that two MIs access different
1476 /// memory addresses. This function returns true if two MIs access different
1477 /// memory addresses and false otherwise.
1478 ///
1479 /// Assumes any physical registers used to compute addresses have the same
1480 /// value for both instructions. (This is the most useful assumption for
1481 /// post-RA scheduling.)
1482 ///
1483 /// See also MachineInstr::mayAlias, which is implemented on top of this
1484 /// function.
1485 virtual bool
1486 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1487 AliasAnalysis *AA = nullptr) const {
1488 assert((MIa.mayLoad() || MIa.mayStore()) &&
1489 "MIa must load from or modify a memory location");
1490 assert((MIb.mayLoad() || MIb.mayStore()) &&
1491 "MIb must load from or modify a memory location");
1492 return false;
1493 }
1494
1495 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1496 /// which is a heuristic used for CSE'ing phys reg defs.
1497 virtual unsigned getMachineCSELookAheadLimit() const {
1498 // The default lookahead is small to prevent unprofitable quadratic
1499 // behavior.
1500 return 5;
1501 }
1502
1503 /// Return an array that contains the ids of the target indices (used for the
1504 /// TargetIndex machine operand) and their names.
1505 ///
1506 /// MIR Serialization is able to serialize only the target indices that are
1507 /// defined by this method.
1508 virtual ArrayRef>
1509 getSerializableTargetIndices() const {
1510 return None;
1511 }
1512
1513 /// Decompose the machine operand's target flags into two values - the direct
1514 /// target flag value and any of bit flags that are applied.
1515 virtual std::pair
1516 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1517 return std::make_pair(0u, 0u);
1518 }
1519
1520 /// Return an array that contains the direct target flag values and their
1521 /// names.
1522 ///
1523 /// MIR Serialization is able to serialize only the target flags that are
1524 /// defined by this method.
1525 virtual ArrayRef>
1526 getSerializableDirectMachineOperandTargetFlags() const {
1527 return None;
1528 }
1529
1530 /// Return an array that contains the bitmask target flag values and their
1531 /// names.
1532 ///
1533 /// MIR Serialization is able to serialize only the target flags that are
1534 /// defined by this method.
1535 virtual ArrayRef>
1536 getSerializableBitmaskMachineOperandTargetFlags() const {
1537 return None;
1538 }
1539
1540 /// Return an array that contains the MMO target flag values and their
1541 /// names.
1542 ///
1543 /// MIR Serialization is able to serialize only the MMO target flags that are
1544 /// defined by this method.
1545 virtual ArrayRef>
1546 getSerializableMachineMemOperandTargetFlags() const {
1547 return None;
1548 }
1549
1550 /// Determines whether \p Inst is a tail call instruction. Override this
1551 /// method on targets that do not properly set MCID::Return and MCID::Call on
1552 /// tail call instructions."
1553 virtual bool isTailCall(const MachineInstr &Inst) const {
1554 return Inst.isReturn() && Inst.isCall();
1555 }
1556
1557 /// True if the instruction is bound to the top of its basic block and no
1558 /// other instructions shall be inserted before it. This can be implemented
1559 /// to prevent register allocator to insert spills before such instructions.
1560 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1561 return false;
1562 }
1563
1564 /// \brief Describes the number of instructions that it will take to call and
1565 /// construct a frame for a given outlining candidate.
1566 struct MachineOutlinerInfo {
1567 /// Number of instructions to call an outlined function for this candidate.
1568 unsigned CallOverhead;
1569
1570 /// \brief Number of instructions to construct an outlined function frame
1571 /// for this candidate.
1572 unsigned FrameOverhead;
1573
1574 /// \brief Represents the specific instructions that must be emitted to
1575 /// construct a call to this candidate.
1576 unsigned CallConstructionID;
1577
1578 /// \brief Represents the specific instructions that must be emitted to
1579 /// construct a frame for this candidate's outlined function.
1580 unsigned FrameConstructionID;
1581
1582 MachineOutlinerInfo() {}
1583 MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
1584 unsigned CallConstructionID,
1585 unsigned FrameConstructionID)
1586 : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
1587 CallConstructionID(CallConstructionID),
1588 FrameConstructionID(FrameConstructionID) {}
1589 };
1590
1591 /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
1592 /// information for a set of outlining candidates.
1593 virtual MachineOutlinerInfo getOutlininingCandidateInfo(
1594 std::vector<
1595 std::pair>
1596 &RepeatedSequenceLocs) const {
1597 llvm_unreachable(
1598 "Target didn't implement TargetInstrInfo::getOutliningOverhead!");
1599 }
1600
1601 /// Represents how an instruction should be mapped by the outliner.
1602 /// \p Legal instructions are those which are safe to outline.
1603 /// \p Illegal instructions are those which cannot be outlined.
1604 /// \p Invisible instructions are instructions which can be outlined, but
1605 /// shouldn't actually impact the outlining result.
1606 enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
1607
1608 /// Returns how or if \p MI should be outlined.
1609 virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
1610 llvm_unreachable(
1611 "Target didn't implement TargetInstrInfo::getOutliningType!");
1612 }
1613
1614 /// Insert a custom epilogue for outlined functions.
1615 /// This may be empty, in which case no epilogue or return statement will be
1616 /// emitted.
1617 virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
1618 MachineFunction &MF,
1619 const MachineOutlinerInfo &MInfo) const {
1620 llvm_unreachable(
1621 "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
1622 }
1623
1624 /// Insert a call to an outlined function into the program.
1625 /// Returns an iterator to the spot where we inserted the call. This must be
1626 /// implemented by the target.
1627 virtual MachineBasicBlock::iterator
1628 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1629 MachineBasicBlock::iterator &It, MachineFunction &MF,
1630 const MachineOutlinerInfo &MInfo) const {
1631 llvm_unreachable(
1632 "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1633 }
1634
1635 /// Insert a custom prologue for outlined functions.
1636 /// This may be empty, in which case no prologue will be emitted.
1637 virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
1638 MachineFunction &MF,
1639 const MachineOutlinerInfo &MInfo) const {
1640 llvm_unreachable(
1641 "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
1642 }
1643
1644 /// Return true if the function can safely be outlined from.
1645 /// A function \p MF is considered safe for outlining if an outlined function
1646 /// produced from instructions in F will produce a program which produces the
1647 /// same output for any set of given inputs.
1648 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
1649 bool OutlineFromLinkOnceODRs) const {
1650 llvm_unreachable("Target didn't implement "
1651 "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1652 }
1653
1654 private:
1655 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1656 unsigned CatchRetOpcode;
1657 unsigned ReturnOpcode;
1658 };
1659
1660 /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1661 template <> struct DenseMapInfo {
1662 using RegInfo = DenseMapInfo;
1663
1664 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1665 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1666 RegInfo::getEmptyKey());
1667 }
1668
1669 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1670 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1671 RegInfo::getTombstoneKey());
1672 }
1673
1674 /// \brief Reuse getHashValue implementation from
1675 /// std::pair.
1676 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1677 std::pair PairVal = std::make_pair(Val.Reg, Val.SubReg);
1678 return DenseMapInfo>::getHashValue(PairVal);
1679 }
1680
1681 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1682 const TargetInstrInfo::RegSubRegPair &RHS) {
1683 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1684 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1685 }
1686 };
1687
1688 } // end namespace llvm
1689
1690 #endif // LLVM_TARGET_TARGETINSTRINFO_H
2727 #include "llvm/CodeGen/MachineValueType.h"
2828 #include "llvm/CodeGen/RegisterClassInfo.h"
2929 #include "llvm/CodeGen/ScheduleDAG.h"
30 #include "llvm/CodeGen/TargetInstrInfo.h"
3031 #include "llvm/MC/MCInstrDesc.h"
3132 #include "llvm/MC/MCRegisterInfo.h"
3233 #include "llvm/Support/CommandLine.h"
3334 #include "llvm/Support/Debug.h"
3435 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
3636 #include "llvm/Target/TargetRegisterInfo.h"
3737 #include "llvm/Target/TargetSubtargetInfo.h"
3838 #include
1414 #include "llvm/Analysis/ValueTracking.h"
1515 #include "llvm/CodeGen/MachineFunction.h"
1616 #include "llvm/CodeGen/MachineModuleInfo.h"
17 #include "llvm/CodeGen/TargetInstrInfo.h"
1718 #include "llvm/IR/DataLayout.h"
1819 #include "llvm/IR/DerivedTypes.h"
1920 #include "llvm/IR/Function.h"
2324 #include "llvm/IR/Module.h"
2425 #include "llvm/Support/ErrorHandling.h"
2526 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Target/TargetInstrInfo.h"
2727 #include "llvm/Target/TargetLowering.h"
2828 #include "llvm/Target/TargetSubtargetInfo.h"
2929 #include "llvm/Transforms/Utils/GlobalStatus.h"
5050 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
5151 #include "llvm/CodeGen/MachineOperand.h"
5252 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
53 #include "llvm/CodeGen/TargetFrameLowering.h"
54 <