llvm.org GIT mirror llvm / 4830110
Flip -disable-post-RA-scheduler to -post-RA-scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
6 changed file(s) with 13 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
4444 cl::desc("Verify generated machine code"),
4545 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
4646
47 // When this works it will be on by default.
47 // This is not enabled by default due to 1) high compile time cost, 2) it's not
48 // beneficial to all targets. The plan is to let targets decide whether this
49 // is enabled.
4850 static cl::opt
49 DisablePostRAScheduler("disable-post-RA-scheduler",
50 cl::desc("Disable scheduling after register allocation"),
51 cl::init(true));
51 EnablePostRAScheduler("post-RA-scheduler",
52 cl::desc("Enable scheduling after register allocation"),
53 cl::init(false));
5254
5355 // Enable or disable FastISel. Both options are needed, because
5456 // FastISel is enabled by default with -fast, and we wish to be
323325 printAndVerify(PM);
324326
325327 // Second pass scheduler.
326 if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
328 if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
327329 PM.add(createPostRAScheduler());
328330 printAndVerify(PM);
329331 }
None ; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
0 ; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -post-RA-scheduler -avoid-hazards
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
0 ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
0 ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
0 ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies=false > %t
0 ; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t
11 ; RUN: grep {%xmm0} %t | count 14
22 ; RUN: not grep {%xmm1} %t
3 ; RUN: llc < %s -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies > %t
3 ; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t
44 ; RUN: grep {%xmm0} %t | count 7
55 ; RUN: grep {%xmm1} %t | count 7
66