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Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC. Eric has replied and has demanded the patch be reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247702 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 5 years ago
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include/llvm/ADT/TargetTuple.h less more
None //===-- llvm/ADT/TargetTuple.h - Target tuple class -------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// @file
10 /// This file contains the definitions for TargetTuples which describe the
11 /// target in a unique unambiguous way. This is in contrast to the GNU triples
12 /// handled by the Triple class which are more of a guideline than a
13 /// description and whose meaning can be overridden by vendors and distributors.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef LLVM_ADT_TARGETTUPLE_H
18 #define LLVM_ADT_TARGETTUPLE_H
19
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/ADT/Triple.h"
22
23 // Some system headers or GCC predefined macros conflict with identifiers in
24 // this file. Undefine them here.
25 #undef NetBSD
26 #undef mips
27 #undef sparc
28
29 namespace llvm {
30
31 /// TargetTuple is currently a proxy for Triple but will become an unambiguous,
32 /// authoratitive, and mutable counterpart to the GNU triples handled by Triple.
33 class TargetTuple {
34 public:
35 // FIXME: Don't duplicate Triple::ArchType. It's worth mentioning that these
36 // these values don't have to match Triple::ArchType. For example, it
37 // would be fairly sensible to have a single 'mips' architecture and
38 // distinguish endianness and ABI elsewhere.
39 enum ArchType {
40 UnknownArch,
41
42 arm, // ARM (little endian): arm, armv.*, xscale
43 armeb, // ARM (big endian): armeb
44 aarch64, // AArch64 (little endian): aarch64
45 aarch64_be, // AArch64 (big endian): aarch64_be
46 bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
47 bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
48 hexagon, // Hexagon: hexagon
49 mips, // MIPS: mips, mipsallegrex
50 mipsel, // MIPSEL: mipsel, mipsallegrexel
51 mips64, // MIPS64: mips64
52 mips64el, // MIPS64EL: mips64el
53 msp430, // MSP430: msp430
54 ppc, // PPC: powerpc
55 ppc64, // PPC64: powerpc64, ppu
56 ppc64le, // PPC64LE: powerpc64le
57 r600, // R600: AMD GPUs HD2XXX - HD6XXX
58 amdgcn, // AMDGCN: AMD GCN GPUs
59 sparc, // Sparc: sparc
60 sparcv9, // Sparcv9: Sparcv9
61 sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
62 systemz, // SystemZ: s390x
63 tce, // TCE (http://tce.cs.tut.fi/): tce
64 // FIXME: thumb/thumbeb will be merged into arm/armeb soon.
65 thumb, // Thumb (little endian): thumb, thumbv.*
66 thumbeb, // Thumb (big endian): thumbeb
67 x86, // X86: i[3-9]86
68 x86_64, // X86-64: amd64, x86_64
69 xcore, // XCore: xcore
70 nvptx, // NVPTX: 32-bit
71 nvptx64, // NVPTX: 64-bit
72 le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
73 le64, // le64: generic little-endian 64-bit CPU (PNaCl / Emscripten)
74 amdil, // AMDIL
75 amdil64, // AMDIL with 64-bit pointers
76 hsail, // AMD HSAIL
77 hsail64, // AMD HSAIL with 64-bit pointers
78 spir, // SPIR: standard portable IR for OpenCL 32-bit version
79 spir64, // SPIR: standard portable IR for OpenCL 64-bit version
80 kalimba, // Kalimba: generic kalimba
81 shave, // SHAVE: Movidius vector VLIW processors
82 wasm32, // WebAssembly with 32-bit pointers
83 wasm64, // WebAssembly with 64-bit pointers
84 LastArchType = wasm64
85 };
86
87 enum SubArchType {
88 NoSubArch,
89
90 ARMSubArch_v8_1a,
91 ARMSubArch_v8,
92 ARMSubArch_v7,
93 ARMSubArch_v7em,
94 ARMSubArch_v7m,
95 ARMSubArch_v7s,
96 ARMSubArch_v6,
97 ARMSubArch_v6m,
98 ARMSubArch_v6k,
99 ARMSubArch_v6t2,
100 ARMSubArch_v5,
101 ARMSubArch_v5te,
102 ARMSubArch_v4t,
103
104 KalimbaSubArch_v3,
105 KalimbaSubArch_v4,
106 KalimbaSubArch_v5
107 };
108
109 enum VendorType {
110 UnknownVendor,
111
112 Apple,
113 PC,
114 SCEI,
115 BGP,
116 BGQ,
117 Freescale,
118 IBM,
119 ImaginationTechnologies,
120 MipsTechnologies,
121 NVIDIA,
122 CSR,
123 Myriad,
124 LastVendorType = Myriad
125 };
126
127 enum OSType {
128 UnknownOS,
129
130 CloudABI,
131 Darwin,
132 DragonFly,
133 FreeBSD,
134 IOS,
135 KFreeBSD,
136 Linux,
137 Lv2, // PS3
138 MacOSX,
139 NetBSD,
140 OpenBSD,
141 Solaris,
142 Win32,
143 Haiku,
144 Minix,
145 RTEMS,
146 NaCl, // Native Client
147 CNK, // BG/P Compute-Node Kernel
148 Bitrig,
149 AIX,
150 CUDA, // NVIDIA CUDA
151 NVCL, // NVIDIA OpenCL
152 AMDHSA, // AMD HSA Runtime
153 PS4,
154 LastOSType = PS4
155 };
156
157 enum EnvironmentType {
158 UnknownEnvironment,
159
160 GNU,
161 GNUEABI,
162 GNUEABIHF,
163 GNUX32,
164 CODE16,
165 EABI,
166 EABIHF,
167 Android,
168
169 MSVC,
170 Itanium,
171 Cygnus,
172 AMDOpenCL,
173 CoreCLR,
174 LastEnvironmentType = CoreCLR
175 };
176
177 enum ObjectFormatType {
178 UnknownObjectFormat,
179
180 COFF,
181 ELF,
182 MachO,
183 };
184
185 public:
186 /// @name Constructors
187 /// @{
188
189 /// Default constructor leaves all fields unknown.
190 TargetTuple() : GnuTT() {}
191
192 /// Convert a GNU Triple to a TargetTuple.
193 ///
194 /// This conversion assumes that GNU Triple's have a specific defined meaning
195 /// which isn't strictly true. A single Triple can potentially have multiple
196 /// contradictory meanings depending on compiler options and configure-time
197 /// options. Despite this, Triple's do tend to have a 'usual' meaning, or
198 /// rather a default behaviour and this function selects it.
199 ///
200 /// When tool options affect the desired TargetTuple, the tool should obtain
201 /// the usual meaning of the GNU Triple using this constructor and then use
202 /// the mutator methods to apply the tool options.
203 explicit TargetTuple(const Triple &GnuTT) : GnuTT(GnuTT) {}
204
205 /// @}
206 /// @name Typed Component Access
207 /// @{
208
209 /// Get the parsed architecture type of this triple.
210 ArchType getArch() const;
211
212 /// get the parsed subarchitecture type for this triple.
213 SubArchType getSubArch() const;
214
215 /// Get the parsed vendor type of this triple.
216 VendorType getVendor() const;
217
218 /// Get the parsed operating system type of this triple.
219 OSType getOS() const;
220
221 /// Does this triple have the optional environment
222 /// (fourth) component?
223 bool hasEnvironment() const { return GnuTT.hasEnvironment(); }
224
225 /// Get the parsed environment type of this triple.
226 EnvironmentType getEnvironment() const;
227
228 /// Parse the version number from the OS name component of the
229 /// triple, if present.
230 ///
231 /// For example, "fooos1.2.3" would return (1, 2, 3).
232 ///
233 /// If an entry is not defined, it will be returned as 0.
234 void getEnvironmentVersion(unsigned &Major, unsigned &Minor,
235 unsigned &Micro) const;
236
237 /// Get the object format for this triple.
238 ObjectFormatType getObjectFormat() const;
239
240 /// Parse the version number from the OS name component of the
241 /// triple, if present.
242 ///
243 /// For example, "fooos1.2.3" would return (1, 2, 3).
244 ///
245 /// If an entry is not defined, it will be returned as 0.
246 void getOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const {
247 return GnuTT.getOSVersion(Major, Minor, Micro);
248 }
249
250 /// Return just the major version number, this is
251 /// specialized because it is a common query.
252 unsigned getOSMajorVersion() const { return GnuTT.getOSMajorVersion(); }
253
254 /// Parse the version number as with getOSVersion and then
255 /// translate generic "darwin" versions to the corresponding OS X versions.
256 /// This may also be called with IOS triples but the OS X version number is
257 /// just set to a constant 10.4.0 in that case. Returns true if successful.
258 bool getMacOSXVersion(unsigned &Major, unsigned &Minor,
259 unsigned &Micro) const {
260 return GnuTT.getMacOSXVersion(Major, Minor, Micro);
261 }
262
263 /// Parse the version number as with getOSVersion. This
264 /// should
265 /// only be called with IOS triples.
266 void getiOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const {
267 return GnuTT.getiOSVersion(Major, Minor, Micro);
268 }
269
270 /// @}
271 /// @name Direct Component Access
272 /// @{
273
274 const std::string &str() const { return GnuTT.str(); }
275
276 const std::string &getTriple() const { return GnuTT.str(); }
277
278 /// Get the architecture (first) component of the
279 /// triple.
280 StringRef getArchName() const { return GnuTT.getArchName(); }
281
282 /// Get the vendor (second) component of the triple.
283 StringRef getVendorName() const { return GnuTT.getVendorName(); }
284
285 /// Get the operating system (third) component of the
286 /// triple.
287 StringRef getOSName() const { return GnuTT.getOSName(); }
288
289 /// Get the optional environment (fourth)
290 /// component of the triple, or "" if empty.
291 StringRef getEnvironmentName() const { return GnuTT.getEnvironmentName(); }
292
293 /// Get the operating system and optional
294 /// environment components as a single string (separated by a '-'
295 /// if the environment component is present).
296 StringRef getOSAndEnvironmentName() const {
297 return GnuTT.getOSAndEnvironmentName();
298 }
299
300 /// @}
301 /// @name Convenience Predicates
302 /// @{
303
304 /// Test whether the architecture is 64-bit
305 ///
306 /// Note that this tests for 64-bit pointer width, and nothing else. Note
307 /// that we intentionally expose only three predicates, 64-bit, 32-bit, and
308 /// 16-bit. The inner details of pointer width for particular architectures
309 /// is not summed up in the triple, and so only a coarse grained predicate
310 /// system is provided.
311 bool isArch64Bit() const { return GnuTT.isArch64Bit(); }
312
313 /// Test whether the architecture is 32-bit
314 ///
315 /// Note that this tests for 32-bit pointer width, and nothing else.
316 bool isArch32Bit() const { return GnuTT.isArch32Bit(); }
317
318 /// Test whether the architecture is 16-bit
319 ///
320 /// Note that this tests for 16-bit pointer width, and nothing else.
321 bool isArch16Bit() const { return GnuTT.isArch16Bit(); }
322
323 /// Helper function for doing comparisons against version
324 /// numbers included in the target triple.
325 bool isOSVersionLT(unsigned Major, unsigned Minor = 0,
326 unsigned Micro = 0) const {
327 return GnuTT.isOSVersionLT(Major, Minor, Micro);
328 }
329
330 bool isOSVersionLT(const Triple &Other) const {
331 return GnuTT.isOSVersionLT(Other);
332 }
333
334 /// Comparison function for checking OS X version
335 /// compatibility, which handles supporting skewed version numbering schemes
336 /// used by the "darwin" triples.
337 unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
338 unsigned Micro = 0) const {
339 return GnuTT.isMacOSXVersionLT(Major, Minor, Micro);
340 }
341
342 /// Is this a Mac OS X triple. For legacy reasons, we support both
343 /// "darwin" and "osx" as OS X triples.
344 bool isMacOSX() const { return GnuTT.isMacOSX(); }
345
346 /// Is this an iOS triple.
347 bool isiOS() const { return GnuTT.isiOS(); }
348
349 /// Is this a "Darwin" OS (OS X or iOS).
350 bool isOSDarwin() const { return GnuTT.isOSDarwin(); }
351
352 bool isOSNetBSD() const { return GnuTT.isOSNetBSD(); }
353
354 bool isOSOpenBSD() const { return GnuTT.isOSOpenBSD(); }
355
356 bool isOSFreeBSD() const { return GnuTT.isOSFreeBSD(); }
357
358 bool isOSDragonFly() const { return GnuTT.isOSDragonFly(); }
359
360 bool isOSSolaris() const { return GnuTT.isOSSolaris(); }
361
362 bool isOSBitrig() const { return GnuTT.isOSBitrig(); }
363
364 bool isWindowsMSVCEnvironment() const {
365 return GnuTT.isWindowsMSVCEnvironment();
366 }
367
368 bool isKnownWindowsMSVCEnvironment() const {
369 return GnuTT.isKnownWindowsMSVCEnvironment();
370 }
371
372 bool isWindowsCoreCLREnvironment() const {
373 return GnuTT.isWindowsCoreCLREnvironment();
374 }
375
376 bool isWindowsItaniumEnvironment() const {
377 return GnuTT.isWindowsItaniumEnvironment();
378 }
379
380 bool isWindowsCygwinEnvironment() const {
381 return GnuTT.isWindowsCygwinEnvironment();
382 }
383
384 bool isWindowsGNUEnvironment() const {
385 return GnuTT.isWindowsGNUEnvironment();
386 }
387
388 /// Tests for either Cygwin or MinGW OS
389 bool isOSCygMing() const { return GnuTT.isOSCygMing(); }
390
391 /// Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
392 bool isOSMSVCRT() const { return GnuTT.isOSMSVCRT(); }
393
394 /// Tests whether the OS is Windows.
395 bool isOSWindows() const { return GnuTT.isOSWindows(); }
396
397 /// Tests whether the OS is NaCl (Native Client)
398 bool isOSNaCl() const { return GnuTT.isOSNaCl(); }
399
400 /// Tests whether the OS is Linux.
401 bool isOSLinux() const { return GnuTT.isOSLinux(); }
402
403 /// Tests whether the OS uses the ELF binary format.
404 bool isOSBinFormatELF() const { return GnuTT.isOSBinFormatELF(); }
405
406 /// Tests whether the OS uses the COFF binary format.
407 bool isOSBinFormatCOFF() const { return GnuTT.isOSBinFormatCOFF(); }
408
409 /// Tests whether the environment is MachO.
410 bool isOSBinFormatMachO() const { return GnuTT.isOSBinFormatMachO(); }
411
412 /// Tests whether the target is the PS4 CPU
413 bool isPS4CPU() const { return GnuTT.isPS4CPU(); }
414
415 /// Tests whether the target is the PS4 platform
416 bool isPS4() const { return GnuTT.isPS4(); }
417
418 /// @}
419
420 // FIXME: Remove. This function exists to avoid having to migrate everything
421 // at once.
422 const Triple &getTargetTriple() const { return GnuTT; }
423
424 private:
425 Triple GnuTT;
426 };
427
428 } // End llvm namespace
429
430 #endif
99 #ifndef LLVM_MC_MCELFOBJECTWRITER_H
1010 #define LLVM_MC_MCELFOBJECTWRITER_H
1111
12 #include "llvm/ADT/TargetTuple.h"
12 #include "llvm/ADT/Triple.h"
1313 #include "llvm/Support/DataTypes.h"
1414 #include "llvm/Support/ELF.h"
1515 #include
4949 bool IsN64=false);
5050
5151 public:
52 static uint8_t getOSABI(TargetTuple::OSType OSType) {
52 static uint8_t getOSABI(Triple::OSType OSType) {
5353 switch (OSType) {
54 case TargetTuple::CloudABI:
55 return ELF::ELFOSABI_CLOUDABI;
56 case TargetTuple::PS4:
57 case TargetTuple::FreeBSD:
58 return ELF::ELFOSABI_FREEBSD;
59 case TargetTuple::Linux:
60 return ELF::ELFOSABI_LINUX;
61 default:
62 return ELF::ELFOSABI_NONE;
54 case Triple::CloudABI:
55 return ELF::ELFOSABI_CLOUDABI;
56 case Triple::PS4:
57 case Triple::FreeBSD:
58 return ELF::ELFOSABI_FREEBSD;
59 case Triple::Linux:
60 return ELF::ELFOSABI_LINUX;
61 default:
62 return ELF::ELFOSABI_NONE;
6363 }
6464 }
6565
1313 #ifndef LLVM_MC_MCSUBTARGETINFO_H
1414 #define LLVM_MC_MCSUBTARGETINFO_H
1515
16 #include "llvm/ADT/TargetTuple.h"
1716 #include "llvm/MC/MCInstrItineraries.h"
1817 #include "llvm/MC/SubtargetFeature.h"
1918 #include
2726 /// MCSubtargetInfo - Generic base class for all target subtargets.
2827 ///
2928 class MCSubtargetInfo {
30 TargetTuple TheTargetTuple; // Target triple
31 std::string CPU; // CPU being targeted.
29 Triple TargetTriple; // Target triple
30 std::string CPU; // CPU being targeted.
3231 ArrayRef ProcFeatures; // Processor feature list
33 ArrayRef ProcDesc; // Processor descriptions
32 ArrayRef ProcDesc; // Processor descriptions
3433
3534 // Scheduler machine model
3635 const SubtargetInfoKV *ProcSchedModels;
5049
5150 public:
5251 MCSubtargetInfo(const MCSubtargetInfo &) = default;
53 MCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS,
52 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
5453 ArrayRef PF,
5554 ArrayRef PD,
5655 const SubtargetInfoKV *ProcSched,
5857 const MCReadAdvanceEntry *RA, const InstrStage *IS,
5958 const unsigned *OC, const unsigned *FP);
6059
61 /// getTargetTuple - Return the target triple string.
62 const TargetTuple &getTargetTuple() const { return TheTargetTuple; }
60 /// getTargetTriple - Return the target triple string.
61 const Triple &getTargetTriple() const { return TargetTriple; }
6362
6463 /// getCPU - Return the CPU string.
6564 StringRef getCPU() const {
2020
2121 #include "llvm-c/Disassembler.h"
2222 #include "llvm/ADT/Triple.h"
23 #include "llvm/ADT/TargetTuple.h"
2423 #include "llvm/Support/CodeGen.h"
2524 #include "llvm/Support/FormattedStream.h"
2625 #include
6968 bool RelaxAll, bool DWARFMustBeAtTheEnd,
7069 bool LabelSections = false);
7170
72 MCRelocationInfo *createMCRelocationInfo(const TargetTuple &TT, MCContext &Ctx);
73
74 MCSymbolizer *createMCSymbolizer(const TargetTuple &TT,
75 LLVMOpInfoCallback GetOpInfo,
71 MCRelocationInfo *createMCRelocationInfo(const Triple &TT, MCContext &Ctx);
72
73 MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
7674 LLVMSymbolLookupCallback SymbolLookUp,
7775 void *DisInfo, MCContext *Ctx,
7876 std::unique_ptr &&RelInfo);
9290 typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch);
9391
9492 typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
95 const TargetTuple &TT);
96 typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const TargetTuple &TT,
93 const Triple &TT);
94 typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT,
9795 Reloc::Model RM,
9896 CodeModel::Model CM,
9997 CodeGenOpt::Level OL);
10098 typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
10199 typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
102 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const TargetTuple &TT);
103 // FIXME: CPU and Features should be merged into TargetTuple when possible.
104 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const TargetTuple &TT,
100 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(const Triple &TT);
101 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
105102 StringRef CPU,
106103 StringRef Features);
107 // FIXME: CPU and Features should be merged into TargetTuple when possible.
108104 typedef TargetMachine *(*TargetMachineCtorTy)(
109 const Target &T, const TargetTuple &TT, StringRef CPU, StringRef Features,
105 const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
110106 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
111107 CodeGenOpt::Level OL);
112108 // If it weren't for layering issues (this header is in llvm/Support, but
114110 // reference.
115111 typedef AsmPrinter *(*AsmPrinterCtorTy)(
116112 TargetMachine &TM, std::unique_ptr &&Streamer);
117 // FIXME: CPU and Features should be merged into TargetTuple when possible.
118113 typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
119114 const MCRegisterInfo &MRI,
120 const TargetTuple &TT,
121 StringRef CPU);
115 const Triple &TT, StringRef CPU);
122116 typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
123117 MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
124118 const MCTargetOptions &Options);
125119 typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
126120 const MCSubtargetInfo &STI,
127121 MCContext &Ctx);
128 typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const TargetTuple &T,
122 typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Triple &T,
129123 unsigned SyntaxVariant,
130124 const MCAsmInfo &MAI,
131125 const MCInstrInfo &MII,
133127 typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
134128 const MCRegisterInfo &MRI,
135129 MCContext &Ctx);
136 typedef MCStreamer *(*ELFStreamerCtorTy)(const TargetTuple &T, MCContext &Ctx,
130 typedef MCStreamer *(*ELFStreamerCtorTy)(const Triple &T, MCContext &Ctx,
137131 MCAsmBackend &TAB,
138132 raw_pwrite_stream &OS,
139133 MCCodeEmitter *Emitter,
153147 bool IsVerboseAsm);
154148 typedef MCTargetStreamer *(*ObjectTargetStreamerCtorTy)(
155149 MCStreamer &S, const MCSubtargetInfo &STI);
156 typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(const TargetTuple &TT,
150 typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(const Triple &TT,
157151 MCContext &Ctx);
158152 typedef MCSymbolizer *(*MCSymbolizerCtorTy)(
159 const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
153 const Triple &TT, LLVMOpInfoCallback GetOpInfo,
160154 LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
161155 std::unique_ptr &&RelInfo);
162156
293287 /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
294288 /// target triple.
295289 ///
296 /// \param TT This argument is used to determine the target machine
290 /// \param TheTriple This argument is used to determine the target machine
297291 /// feature set; it should always be provided. Generally this should be
298292 /// either the target triple from the module, or the target triple of the
299293 /// host if that does not exist.
300 MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) const {
294 MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
295 StringRef TheTriple) const {
301296 if (!MCAsmInfoCtorFn)
302297 return nullptr;
303 return MCAsmInfoCtorFn(MRI, TargetTuple(Triple(TT)));
298 return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
304299 }
305300
306301 /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
310305 CodeGenOpt::Level OL) const {
311306 if (!MCCodeGenInfoCtorFn)
312307 return nullptr;
313 return MCCodeGenInfoCtorFn(TargetTuple(Triple(TT)), RM, CM, OL);
308 return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL);
314309 }
315310
316311 /// createMCInstrInfo - Create a MCInstrInfo implementation.
334329 MCRegisterInfo *createMCRegInfo(StringRef TT) const {
335330 if (!MCRegInfoCtorFn)
336331 return nullptr;
337 return MCRegInfoCtorFn(TargetTuple(Triple(TT)));
332 return MCRegInfoCtorFn(Triple(TT));
338333 }
339334
340335 /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
341336 ///
342 /// \param TT This argument is used to determine the target machine
337 /// \param TheTriple This argument is used to determine the target machine
343338 /// feature set; it should always be provided. Generally this should be
344339 /// either the target triple from the module, or the target triple of the
345340 /// host if that does not exist.
346341 /// \param CPU This specifies the name of the target CPU.
347342 /// \param Features This specifies the string representation of the
348343 /// additional target features.
349 MCSubtargetInfo *createMCSubtargetInfo(StringRef TT, StringRef CPU,
344 MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
350345 StringRef Features) const {
351346 if (!MCSubtargetInfoCtorFn)
352347 return nullptr;
353 return MCSubtargetInfoCtorFn(TargetTuple(Triple(TT)), CPU, Features);
348 return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
354349 }
355350
356351 /// createTargetMachine - Create a target specific machine implementation
357 /// for the specified \p TT.
352 /// for the specified \p Triple.
358353 ///
359354 /// \param TT This argument is used to determine the target machine
360355 /// feature set; it should always be provided. Generally this should be
368363 CodeGenOpt::Level OL = CodeGenOpt::Default) const {
369364 if (!TargetMachineCtorFn)
370365 return nullptr;
371 return TargetMachineCtorFn(*this, TargetTuple(Triple(TT)), CPU, Features,
372 Options, RM, CM, OL);
366 return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
367 CM, OL);
373368 }
374369
375370 /// createMCAsmBackend - Create a target specific assembly parser.
376371 ///
377 /// \param TT The target triple string.
378 MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, StringRef TT,
379 StringRef CPU) const {
372 /// \param TheTriple The target triple string.
373 MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
374 StringRef TheTriple, StringRef CPU) const {
380375 if (!MCAsmBackendCtorFn)
381376 return nullptr;
382 return MCAsmBackendCtorFn(*this, MRI, TargetTuple(Triple(TT)), CPU);
377 return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
383378 }
384379
385380 /// createMCAsmParser - Create a target specific assembly parser.
411406 return MCDisassemblerCtorFn(*this, STI, Ctx);
412407 }
413408
414 MCInstPrinter *createMCInstPrinter(const TargetTuple &TT,
415 unsigned SyntaxVariant,
409 MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
416410 const MCAsmInfo &MAI,
417411 const MCInstrInfo &MII,
418412 const MCRegisterInfo &MRI) const {
419413 if (!MCInstPrinterCtorFn)
420414 return nullptr;
421 return MCInstPrinterCtorFn(TT, SyntaxVariant, MAI, MII, MRI);
415 return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI);
422416 }
423417
424418 /// createMCCodeEmitter - Create a target specific code emitter.
432426
433427 /// Create a target specific MCStreamer.
434428 ///
435 /// \param TT The target triple.
429 /// \param T The target triple.
436430 /// \param Ctx The target context.
437431 /// \param TAB The target assembler backend object. Takes ownership.
438432 /// \param OS The stream object.
439433 /// \param Emitter The target independent assembler object.Takes ownership.
440434 /// \param RelaxAll Relax all fixups?
441 MCStreamer *createMCObjectStreamer(const TargetTuple &TT, MCContext &Ctx,
435 MCStreamer *createMCObjectStreamer(const Triple &T, MCContext &Ctx,
442436 MCAsmBackend &TAB, raw_pwrite_stream &OS,
443437 MCCodeEmitter *Emitter,
444438 const MCSubtargetInfo &STI, bool RelaxAll,
445439 bool DWARFMustBeAtTheEnd) const {
446440 MCStreamer *S;
447 switch (TT.getObjectFormat()) {
441 switch (T.getObjectFormat()) {
448442 default:
449443 llvm_unreachable("Unknown object format");
450 case TargetTuple::COFF:
451 assert(TT.isOSWindows() && "only Windows COFF is supported");
444 case Triple::COFF:
445 assert(T.isOSWindows() && "only Windows COFF is supported");
452446 S = COFFStreamerCtorFn(Ctx, TAB, OS, Emitter, RelaxAll);
453447 break;
454 case TargetTuple::MachO:
448 case Triple::MachO:
455449 if (MachOStreamerCtorFn)
456450 S = MachOStreamerCtorFn(Ctx, TAB, OS, Emitter, RelaxAll,
457451 DWARFMustBeAtTheEnd);
459453 S = createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
460454 DWARFMustBeAtTheEnd);
461455 break;
462 case TargetTuple::ELF:
456 case Triple::ELF:
463457 if (ELFStreamerCtorFn)
464 S = ELFStreamerCtorFn(TT, Ctx, TAB, OS, Emitter, RelaxAll);
458 S = ELFStreamerCtorFn(T, Ctx, TAB, OS, Emitter, RelaxAll);
465459 else
466460 S = createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
467461 break;
513507 MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
514508 ? MCRelocationInfoCtorFn
515509 : llvm::createMCRelocationInfo;
516 return Fn(TargetTuple(Triple(TT)), Ctx);
510 return Fn(Triple(TT), Ctx);
517511 }
518512
519513 /// createMCSymbolizer - Create a target specific MCSymbolizer.
535529 std::unique_ptr &&RelInfo) const {
536530 MCSymbolizerCtorTy Fn =
537531 MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolizer;
538 return Fn(TargetTuple(Triple(TT)), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
532 return Fn(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
539533 std::move(RelInfo));
540534 }
541535
593587
594588 /// lookupTarget - Lookup a target based on a target triple.
595589 ///
596 /// \param TT - The triple to use for finding a target.
590 /// \param Triple - The triple to use for finding a target.
597591 /// \param Error - On failure, an error string describing why no target was
598592 /// found.
599 static const Target *lookupTarget(const std::string &TT, std::string &Error);
593 static const Target *lookupTarget(const std::string &Triple,
594 std::string &Error);
600595
601596 /// lookupTarget - Lookup a target based on an architecture name
602597 /// and a target triple. If the architecture name is non-empty,
604599 /// triple is used.
605600 ///
606601 /// \param ArchName - The architecture to use for finding a target.
607 /// \param TT - The triple to use for finding a target. The
602 /// \param TheTriple - The triple to use for finding a target. The
608603 /// triple is updated with canonical architecture name if a lookup
609604 /// by architecture is done.
610605 /// \param Error - On failure, an error string describing why no target was
611606 /// found.
612 static const Target *lookupTarget(const std::string &ArchName, Triple &TT,
613 std::string &Error);
607 static const Target *lookupTarget(const std::string &ArchName,
608 Triple &TheTriple, std::string &Error);
614609
615610 /// @}
616611 /// @name Target Registration
896891
897892 private:
898893 static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
899 const TargetTuple &TT) {
900 return new MCAsmInfoImpl(TargetTuple(TT));
894 const Triple &TT) {
895 return new MCAsmInfoImpl(TT);
901896 }
902897 };
903898
930925 }
931926
932927 private:
933 static MCCodeGenInfo *Allocator(const TargetTuple & /*TT*/,
934 Reloc::Model /*RM*/, CodeModel::Model /*CM*/,
928 static MCCodeGenInfo *Allocator(const Triple & /*TT*/, Reloc::Model /*RM*/,
929 CodeModel::Model /*CM*/,
935930 CodeGenOpt::Level /*OL*/) {
936931 return new MCCodeGenInfoImpl();
937932 }
10291024 }
10301025
10311026 private:
1032 static MCRegisterInfo *Allocator(const TargetTuple & /*TT*/) {
1027 static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
10331028 return new MCRegisterInfoImpl();
10341029 }
10351030 };
10621057 }
10631058
10641059 private:
1065 static MCSubtargetInfo *Allocator(const TargetTuple & /*TT*/,
1066 StringRef /*CPU*/, StringRef /*FS*/) {
1060 static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
1061 StringRef /*FS*/) {
10671062 return new MCSubtargetInfoImpl();
10681063 }
10691064 };
10961091 }
10971092
10981093 private:
1099 static TargetMachine *Allocator(const Target &T, const TargetTuple &TT,
1094 static TargetMachine *Allocator(const Target &T, const Triple &TT,
11001095 StringRef CPU, StringRef FS,
11011096 const TargetOptions &Options, Reloc::Model RM,
11021097 CodeModel::Model CM, CodeGenOpt::Level OL) {
1103 return new TargetMachineImpl(T, TT.getTargetTriple(), CPU, FS, Options, RM,
1104 CM, OL);
1098 return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
11051099 }
11061100 };
11071101
11191113
11201114 private:
11211115 static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
1122 const TargetTuple &TT, StringRef CPU) {
1123 return new MCAsmBackendImpl(T, MRI, TT, CPU);
1116 const Triple &TheTriple, StringRef CPU) {
1117 return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
11241118 }
11251119 };
11261120
1414 #define LLVM_TARGET_TARGETMACHINE_H
1515
1616 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/TargetTuple.h"
1817 #include "llvm/ADT/Triple.h"
1918 #include "llvm/IR/DataLayout.h"
2019 #include "llvm/Pass.h"
116115 const Target &getTarget() const { return TheTarget; }
117116
118117 const Triple &getTargetTriple() const { return TargetTriple; }
119 // FIXME: Return a reference once we store a TargetTuple
120 const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
121118 StringRef getTargetCPU() const { return TargetCPU; }
122119 StringRef getTargetFeatureString() const { return TargetFS; }
123120
4747 TargetSubtargetInfo() = delete;
4848
4949 protected: // Can only create subclasses...
50 TargetSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS,
50 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
5151 ArrayRef PF,
5252 ArrayRef PD,
5353 const SubtargetInfoKV *ProcSched,
169169 switch (FileType) {
170170 case CGFT_AssemblyFile: {
171171 MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
172 getTargetTuple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
172 getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
173173
174174 // Create a code emitter if asked to show the encoding.
175175 MCCodeEmitter *MCE = nullptr;
198198 // Don't waste memory on names of temp labels.
199199 Context->setUseNamesOnTempLabels(false);
200200
201 TargetTuple T(Triple(getTargetTriple().str()));
201 Triple T(getTargetTriple().str());
202202 AsmStreamer.reset(getTarget().createMCObjectStreamer(
203203 T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
204204 /*DWARFMustBeAtTheEnd*/ true));
249249 if (!MCE || !MAB)
250250 return true;
251251
252 const TargetTuple &TT = getTargetTuple();
252 const Triple &T = getTargetTriple();
253253 const MCSubtargetInfo &STI = *getMCSubtargetInfo();
254254 std::unique_ptr AsmStreamer(getTarget().createMCObjectStreamer(
255 TT, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
255 T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll,
256256 /*DWARFMustBeAtTheEnd*/ true));
257257
258258 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
8282 // Set up the instruction printer.
8383 int AsmPrinterVariant = MAI->getAssemblerDialect();
8484 MCInstPrinter *IP = TheTarget->createMCInstPrinter(
85 TargetTuple(Triple(TT)), AsmPrinterVariant, *MAI, *MII, *MRI);
85 Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
8686 if (!IP)
8787 return nullptr;
8888
309309 int AsmPrinterVariant = MAI->getAssemblerDialect();
310310 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
311311 MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
312 TargetTuple(Triple(DC->getTripleName())), AsmPrinterVariant, *MAI,
313 *MII, *MRI);
312 Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
314313 if (IP) {
315314 DC->setIP(IP);
316315 DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
1616 using namespace llvm;
1717
1818 namespace llvm {
19 class TargetTuple;
19 class Triple;
2020 }
2121
2222 // This function tries to add a symbolic operand in place of the immediate
187187 }
188188
189189 namespace llvm {
190 MCSymbolizer *createMCSymbolizer(const TargetTuple &TT,
191 LLVMOpInfoCallback GetOpInfo,
190 MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
192191 LLVMSymbolLookupCallback SymbolLookUp,
193192 void *DisInfo, MCContext *Ctx,
194193 std::unique_ptr &&RelInfo) {
3333 return SubExpr;
3434 }
3535
36 MCRelocationInfo *llvm::createMCRelocationInfo(const TargetTuple &TT,
36 MCRelocationInfo *llvm::createMCRelocationInfo(const Triple &TT,
3737 MCContext &Ctx) {
3838 return new MCRelocationInfo(Ctx);
3939 }
88
99 #include "llvm/MC/MCSubtargetInfo.h"
1010 #include "llvm/ADT/StringRef.h"
11 #include "llvm/ADT/TargetTuple.h"
11 #include "llvm/ADT/Triple.h"
1212 #include "llvm/MC/MCInstrItineraries.h"
1313 #include "llvm/MC/SubtargetFeature.h"
1414 #include "llvm/Support/raw_ostream.h"
3636 }
3737
3838 MCSubtargetInfo::MCSubtargetInfo(
39 const TargetTuple &TT, StringRef C, StringRef FS,
39 const Triple &TT, StringRef C, StringRef FS,
4040 ArrayRef PF, ArrayRef PD,
4141 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
4242 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
4343 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
44 : TheTargetTuple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
44 : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
4545 ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
4646 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
4747 InitMCProcessorInfo(CPU, FS);
8787 StringRef.cpp
8888 SystemUtils.cpp
8989 TargetParser.cpp
90 TargetTuple.cpp
9190 Timer.cpp
9291 ToolOutputFile.cpp
9392 Triple.cpp
+0
-315
lib/Support/TargetTuple.cpp less more
None //===--- TargetTuple.cpp - Target tuple class -----------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/ADT/StringSwitch.h"
10 #include "llvm/ADT/TargetTuple.h"
11 #include "llvm/Support/TargetParser.h"
12
13 using namespace llvm;
14
15 // FIXME: These should be removed as soon as the Triple member is replaced.
16 static TargetTuple::ArchType
17 convertTripleArchToTupleArch(Triple::ArchType Arch) {
18 switch (Arch) {
19 case Triple::UnknownArch:
20 return TargetTuple::UnknownArch;
21 case Triple::arm:
22 return TargetTuple::arm;
23 case Triple::armeb:
24 return TargetTuple::armeb;
25 case Triple::aarch64:
26 return TargetTuple::aarch64;
27 case Triple::aarch64_be:
28 return TargetTuple::aarch64_be;
29 case Triple::bpfel:
30 return TargetTuple::bpfel;
31 case Triple::bpfeb:
32 return TargetTuple::bpfeb;
33 case Triple::hexagon:
34 return TargetTuple::hexagon;
35 case Triple::mips:
36 return TargetTuple::mips;
37 case Triple::mipsel:
38 return TargetTuple::mipsel;
39 case Triple::mips64:
40 return TargetTuple::mips64;
41 case Triple::mips64el:
42 return TargetTuple::mips64el;
43 case Triple::msp430:
44 return TargetTuple::msp430;
45 case Triple::ppc:
46 return TargetTuple::ppc;
47 case Triple::ppc64:
48 return TargetTuple::ppc64;
49 case Triple::ppc64le:
50 return TargetTuple::ppc64le;
51 case Triple::r600:
52 return TargetTuple::r600;
53 case Triple::amdgcn:
54 return TargetTuple::amdgcn;
55 case Triple::sparc:
56 return TargetTuple::sparc;
57 case Triple::sparcv9:
58 return TargetTuple::sparcv9;
59 case Triple::sparcel:
60 return TargetTuple::sparcel;
61 case Triple::systemz:
62 return TargetTuple::systemz;
63 case Triple::tce:
64 return TargetTuple::tce;
65 case Triple::thumb:
66 return TargetTuple::thumb;
67 case Triple::thumbeb:
68 return TargetTuple::thumbeb;
69 case Triple::x86:
70 return TargetTuple::x86;
71 case Triple::x86_64:
72 return TargetTuple::x86_64;
73 case Triple::xcore:
74 return TargetTuple::xcore;
75 case Triple::nvptx:
76 return TargetTuple::nvptx;
77 case Triple::nvptx64:
78 return TargetTuple::nvptx64;
79 case Triple::le32:
80 return TargetTuple::le32;
81 case Triple::le64:
82 return TargetTuple::le64;
83 case Triple::amdil:
84 return TargetTuple::amdil;
85 case Triple::amdil64:
86 return TargetTuple::amdil64;
87 case Triple::hsail:
88 return TargetTuple::hsail;
89 case Triple::hsail64:
90 return TargetTuple::hsail64;
91 case Triple::spir:
92 return TargetTuple::spir;
93 case Triple::spir64:
94 return TargetTuple::spir64;
95 case Triple::kalimba:
96 return TargetTuple::kalimba;
97 case Triple::shave:
98 return TargetTuple::shave;
99 case Triple::wasm32:
100 return TargetTuple::wasm32;
101 case Triple::wasm64:
102 return TargetTuple::wasm64;
103 }
104 llvm_unreachable("Unmapped architecture.");
105 }
106
107 // FIXME: These should be removed as soon as the Triple member is replaced.
108 static TargetTuple::SubArchType
109 convertTripleSubArchToTupleSubArch(Triple::SubArchType SubArch) {
110 switch (SubArch) {
111 case Triple::NoSubArch:
112 return TargetTuple::NoSubArch;
113 case Triple::ARMSubArch_v8_1a:
114 return TargetTuple::ARMSubArch_v8_1a;
115 case Triple::ARMSubArch_v8:
116 return TargetTuple::ARMSubArch_v8;
117 case Triple::ARMSubArch_v7:
118 return TargetTuple::ARMSubArch_v7;
119 case Triple::ARMSubArch_v7em:
120 return TargetTuple::ARMSubArch_v7em;
121 case Triple::ARMSubArch_v7m:
122 return TargetTuple::ARMSubArch_v7m;
123 case Triple::ARMSubArch_v7s:
124 return TargetTuple::ARMSubArch_v7s;
125 case Triple::ARMSubArch_v6:
126 return TargetTuple::ARMSubArch_v6;
127 case Triple::ARMSubArch_v6m:
128 return TargetTuple::ARMSubArch_v6m;
129 case Triple::ARMSubArch_v6k:
130 return TargetTuple::ARMSubArch_v6k;
131 case Triple::ARMSubArch_v6t2:
132 return TargetTuple::ARMSubArch_v6t2;
133 case Triple::ARMSubArch_v5:
134 return TargetTuple::ARMSubArch_v5;
135 case Triple::ARMSubArch_v5te:
136 return TargetTuple::ARMSubArch_v5te;
137 case Triple::ARMSubArch_v4t:
138 return TargetTuple::ARMSubArch_v4t;
139 case Triple::KalimbaSubArch_v3:
140 return TargetTuple::KalimbaSubArch_v3;
141 case Triple::KalimbaSubArch_v4:
142 return TargetTuple::KalimbaSubArch_v4;
143 case Triple::KalimbaSubArch_v5:
144 return TargetTuple::KalimbaSubArch_v5;
145 }
146 llvm_unreachable("Unmapped subarchitecture.");
147 }
148
149 // FIXME: These should be removed as soon as the Triple member is replaced.
150 static TargetTuple::VendorType
151 convertTripleVendorToTupleVendor(Triple::VendorType Vendor) {
152 switch (Vendor) {
153 case Triple::UnknownVendor:
154 return TargetTuple::UnknownVendor;
155 case Triple::Apple:
156 return TargetTuple::Apple;
157 case Triple::PC:
158 return TargetTuple::PC;
159 case Triple::SCEI:
160 return TargetTuple::SCEI;
161 case Triple::BGP:
162 return TargetTuple::BGP;
163 case Triple::BGQ:
164 return TargetTuple::BGQ;
165 case Triple::Freescale:
166 return TargetTuple::Freescale;
167 case Triple::IBM:
168 return TargetTuple::IBM;
169 case Triple::ImaginationTechnologies:
170 return TargetTuple::ImaginationTechnologies;
171 case Triple::MipsTechnologies:
172 return TargetTuple::MipsTechnologies;
173 case Triple::NVIDIA:
174 return TargetTuple::NVIDIA;
175 case Triple::CSR:
176 return TargetTuple::CSR;
177 case Triple::Myriad:
178 return TargetTuple::Myriad;
179 }
180 llvm_unreachable("Unmapped vendor.");
181 }
182
183 // FIXME: These should be removed as soon as the Triple member is replaced.
184 static TargetTuple::OSType convertTripleOSToTupleOS(Triple::OSType OS) {
185 switch (OS) {
186 case Triple::UnknownOS:
187 return TargetTuple::UnknownOS;
188 case Triple::CloudABI:
189 return TargetTuple::CloudABI;
190 case Triple::Darwin:
191 return TargetTuple::Darwin;
192 case Triple::DragonFly:
193 return TargetTuple::DragonFly;
194 case Triple::FreeBSD:
195 return TargetTuple::FreeBSD;
196 case Triple::IOS:
197 return TargetTuple::IOS;
198 case Triple::KFreeBSD:
199 return TargetTuple::KFreeBSD;
200 case Triple::Linux:
201 return TargetTuple::Linux;
202 case Triple::Lv2:
203 return TargetTuple::Lv2;
204 case Triple::MacOSX:
205 return TargetTuple::MacOSX;
206 case Triple::NetBSD:
207 return TargetTuple::NetBSD;
208 case Triple::OpenBSD:
209 return TargetTuple::OpenBSD;
210 case Triple::Solaris:
211 return TargetTuple::Solaris;
212 case Triple::Win32:
213 return TargetTuple::Win32;
214 case Triple::Haiku:
215 return TargetTuple::Haiku;
216 case Triple::Minix:
217 return TargetTuple::Minix;
218 case Triple::RTEMS:
219 return TargetTuple::RTEMS;
220 case Triple::NaCl:
221 return TargetTuple::NaCl;
222 case Triple::CNK:
223 return TargetTuple::CNK;
224 case Triple::Bitrig:
225 return TargetTuple::Bitrig;
226 case Triple::AIX:
227 return TargetTuple::AIX;
228 case Triple::CUDA:
229 return TargetTuple::CUDA;
230 case Triple::NVCL:
231 return TargetTuple::NVCL;
232 case Triple::AMDHSA:
233 return TargetTuple::AMDHSA;
234 case Triple::PS4:
235 return TargetTuple::PS4;
236 }
237 llvm_unreachable("Unmapped OS.");
238 }
239
240 // FIXME: These should be removed as soon as the Triple member is replaced.
241 static TargetTuple::EnvironmentType
242 convertTripleEnvToTupleEnv(Triple::EnvironmentType Env) {
243 switch (Env) {
244 case Triple::UnknownEnvironment:
245 return TargetTuple::UnknownEnvironment;
246 case Triple::GNU:
247 return TargetTuple::GNU;
248 case Triple::GNUEABI:
249 return TargetTuple::GNUEABI;
250 case Triple::GNUEABIHF:
251 return TargetTuple::GNUEABIHF;
252 case Triple::GNUX32:
253 return TargetTuple::GNUX32;
254 case Triple::CODE16:
255 return TargetTuple::CODE16;
256 case Triple::EABI:
257 return TargetTuple::EABI;
258 case Triple::EABIHF:
259 return TargetTuple::EABIHF;
260 case Triple::Android:
261 return TargetTuple::Android;
262 case Triple::MSVC:
263 return TargetTuple::MSVC;
264 case Triple::Itanium:
265 return TargetTuple::Itanium;
266 case Triple::Cygnus:
267 return TargetTuple::Cygnus;
268 case Triple::AMDOpenCL:
269 return TargetTuple::AMDOpenCL;
270 case Triple::CoreCLR:
271 return TargetTuple::CoreCLR;
272 }
273 llvm_unreachable("Unmapped Environment.");
274 }
275
276 // FIXME: These should be removed as soon as the Triple member is replaced.
277 static TargetTuple::ObjectFormatType
278 convertTripleObjFmtToTupleObjFmt(Triple::ObjectFormatType ObjFmt) {
279 switch (ObjFmt) {
280 case Triple::UnknownObjectFormat:
281 return TargetTuple::UnknownObjectFormat;
282 case Triple::COFF:
283 return TargetTuple::COFF;
284 case Triple::ELF:
285 return TargetTuple::ELF;
286 case Triple::MachO:
287 return TargetTuple::MachO;
288 }
289 llvm_unreachable("Unmapped Object Format.");
290 }
291
292 TargetTuple::ArchType TargetTuple::getArch() const {
293 return convertTripleArchToTupleArch(GnuTT.getArch());
294 }
295
296 TargetTuple::SubArchType TargetTuple::getSubArch() const {
297 return convertTripleSubArchToTupleSubArch(GnuTT.getSubArch());
298 }
299
300 TargetTuple::VendorType TargetTuple::getVendor() const {
301 return convertTripleVendorToTupleVendor(GnuTT.getVendor());
302 }
303
304 TargetTuple::OSType TargetTuple::getOS() const {
305 return convertTripleOSToTupleOS(GnuTT.getOS());
306 }
307
308 TargetTuple::EnvironmentType TargetTuple::getEnvironment() const {
309 return convertTripleEnvToTupleEnv(GnuTT.getEnvironment());
310 }
311
312 TargetTuple::ObjectFormatType TargetTuple::getObjectFormat() const {
313 return convertTripleObjFmtToTupleObjFmt(GnuTT.getObjectFormat());
314 }
4444 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
4545 const std::string &FS,
4646 const TargetMachine &TM, bool LittleEndian)
47 : AArch64GenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
47 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
4848 HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
4949 HasCRC(false), HasPerfMon(false), HasZeroCycleRegMove(false),
5050 HasZeroCycleZeroing(false), StrictAlign(false), ReserveX18(false),
1818 #include "AArch64InstrInfo.h"
1919 #include "AArch64RegisterInfo.h"
2020 #include "AArch64SelectionDAGInfo.h"
21 #include "llvm/ADT/TargetTuple.h"
2221 #include "llvm/IR/DataLayout.h"
2322 #include "llvm/Target/TargetSubtargetInfo.h"
2423 #include
9796 return &getInstrInfo()->getRegisterInfo();
9897 }
9998 const Triple &getTargetTriple() const { return TargetTriple; }
100 // FIXME: Return a references once our member is a TargetTuple.
101 const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
10299 bool enableMachineScheduler() const override { return true; }
103100 bool enablePostRAScheduler() const override {
104101 return isCortexA53() || isCortexA57();
226226 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
227227 }
228228
229 static MCSymbolizer *createAArch64ExternalSymbolizer(
230 const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
231 LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
232 std::unique_ptr &&RelInfo) {
229 static MCSymbolizer *
230 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
231 LLVMSymbolLookupCallback SymbolLookUp,
232 void *DisInfo, MCContext *Ctx,
233 std::unique_ptr &&RelInfo) {
233234 return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
234235 SymbolLookUp, DisInfo);
235236 }
99 #include "AArch64.h"
1010 #include "AArch64RegisterInfo.h"
1111 #include "MCTargetDesc/AArch64FixupKinds.h"
12 #include "llvm/ADT/TargetTuple.h"
12 #include "llvm/ADT/Triple.h"
1313 #include "llvm/MC/MCAsmBackend.h"
1414 #include "llvm/MC/MCDirectives.h"
1515 #include "llvm/MC/MCELFObjectWriter.h"
520520
521521 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
522522 const MCRegisterInfo &MRI,
523 const TargetTuple &TT,
523 const Triple &TheTriple,
524524 StringRef CPU) {
525 if (TT.isOSBinFormatMachO())
525 if (TheTriple.isOSBinFormatMachO())
526526 return new DarwinAArch64AsmBackend(T, MRI);
527527
528 assert(TT.isOSBinFormatELF() && "Expect either MachO or ELF target");
529 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
528 assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
529 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
530530 return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
531531 }
532532
533533 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
534534 const MCRegisterInfo &MRI,
535 const TargetTuple &TT,
535 const Triple &TheTriple,
536536 StringRef CPU) {
537 assert(TT.isOSBinFormatELF() &&
537 assert(TheTriple.isOSBinFormatELF() &&
538538 "Big endian is only supported for ELF targets!");
539 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
539 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
540540 return new ELFAArch64AsmBackend(T, OSABI,
541541 /*IsLittleEndian=*/false);
542542 }
1616 #include "llvm/MC/MCELFStreamer.h"
1717 #include "llvm/ADT/SmallPtrSet.h"
1818 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/TargetTuple.h"
2019 #include "llvm/ADT/Twine.h"
2120 #include "llvm/MC/MCAsmBackend.h"
2221 #include "llvm/MC/MCAsmInfo.h"
198197
199198 MCTargetStreamer *
200199 createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
201 const TargetTuple &TT = STI.getTargetTuple();
200 const Triple &TT = STI.getTargetTriple();
202201 if (TT.isOSBinFormatELF())
203202 return new AArch64TargetELFStreamer(S);
204203 return nullptr;
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "AArch64MCAsmInfo.h"
14 #include "llvm/ADT/TargetTuple.h"
14 #include "llvm/ADT/Triple.h"
1515 #include "llvm/MC/MCContext.h"
1616 #include "llvm/MC/MCExpr.h"
1717 #include "llvm/MC/MCStreamer.h"
6868 return MCBinaryExpr::createSub(Res, PC, Context);
6969 }
7070
71 AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const TargetTuple &T) {
72 if (T.getArch() == TargetTuple::aarch64_be)
71 AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) {
72 if (T.getArch() == Triple::aarch64_be)
7373 IsLittleEndian = false;
7474
7575 // We prefer NEON instructions to be printed in the short form.
1919 namespace llvm {
2020 class MCStreamer;
2121 class Target;
22 class TargetTuple;
22 class Triple;
2323
2424 struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin {
2525 explicit AArch64MCAsmInfoDarwin();
2929 };
3030
3131 struct AArch64MCAsmInfoELF : public MCAsmInfoELF {
32 explicit AArch64MCAsmInfoELF(const TargetTuple &TT);
32 explicit AArch64MCAsmInfoELF(const Triple &T);
3333 };
3434
3535 } // namespace llvm
3939 return X;
4040 }
4141
42 static MCSubtargetInfo *createAArch64MCSubtargetInfo(const TargetTuple &TT,
43 StringRef CPU,
44 StringRef FS) {
42 static MCSubtargetInfo *
43 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
4544 if (CPU.empty())
4645 CPU = "generic";
4746
4847 return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
4948 }
5049
51 static MCRegisterInfo *createAArch64MCRegisterInfo(const TargetTuple &TT) {
50 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
5251 MCRegisterInfo *X = new MCRegisterInfo();
5352 InitAArch64MCRegisterInfo(X, AArch64::LR);
5453 return X;
5554 }
5655
5756 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
58 const TargetTuple &TT) {
57 const Triple &TheTriple) {
5958 MCAsmInfo *MAI;
60 if (TT.isOSBinFormatMachO())
59 if (TheTriple.isOSBinFormatMachO())
6160 MAI = new AArch64MCAsmInfoDarwin();
6261 else {
63 assert(TT.isOSBinFormatELF() && "Only expect Darwin or ELF");
64 MAI = new AArch64MCAsmInfoELF(TT);
62 assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
63 MAI = new AArch64MCAsmInfoELF(TheTriple);
6564 }
6665
6766 // Initial state of the frame pointer is SP.
7271 return MAI;
7372 }
7473
75 static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT,
74 static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT,
7675 Reloc::Model RM,
7776 CodeModel::Model CM,
7877 CodeGenOpt::Level OL) {
104103 return X;
105104 }
106105
107 static MCInstPrinter *createAArch64MCInstPrinter(const TargetTuple &TT,
106 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
108107 unsigned SyntaxVariant,
109108 const MCAsmInfo &MAI,
110109 const MCInstrInfo &MII,
117116 return nullptr;
118117 }
119118
120 static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
119 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
121120 MCAsmBackend &TAB, raw_pwrite_stream &OS,
122121 MCCodeEmitter *Emitter, bool RelaxAll) {
123122 return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
3030 class MCTargetStreamer;
3131 class StringRef;
3232 class Target;
33 class TargetTuple;
33 class Triple;
3434 class raw_ostream;
3535 class raw_pwrite_stream;
3636
4343 MCContext &Ctx);
4444 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
4545 const MCRegisterInfo &MRI,
46 const TargetTuple &TT, StringRef CPU);
46 const Triple &TT, StringRef CPU);
4747 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
4848 const MCRegisterInfo &MRI,
49 const TargetTuple &TT, StringRef CPU);
49 const Triple &TT, StringRef CPU);
5050
5151 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
5252 uint8_t OSABI,
6262
6363 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
6464 TargetMachine &TM)
65 : AMDGPUGenSubtargetInfo(TargetTuple(TT), GPU, FS), DevName(GPU),
66 Is64bit(false), DumpCode(false), R600ALUInst(false),
67 HasVertexCache(false), TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600),
68 FP64(false), FP64Denormals(false), FP32Denormals(false),
69 FastFMAF32(false), CaymanISA(false), FlatAddressSpace(false),
70 EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
71 EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
65 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
66 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
67 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
68 FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
69 CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
70 EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
71 EnableUnsafeDSOffsetFolding(false),
7272 WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
7373 EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
7474 GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
173173
174174 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
175175 const MCRegisterInfo &MRI,
176 const TargetTuple &TT,
177 StringRef CPU) {
176 const Triple &TT, StringRef CPU) {
177 Triple TargetTriple(TT);
178
178179 // Use 64-bit ELF for amdgcn
179 return new ELFAMDGPUAsmBackend(T, TT.getArch() == TargetTuple::amdgcn);
180 return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
180181 }
1010 #include "AMDGPUMCAsmInfo.h"
1111
1212 using namespace llvm;
13 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const TargetTuple &TT) : MCAsmInfoELF() {
13 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() {
1414 HasSingleParameterDotFile = false;
1515 //===------------------------------------------------------------------===//
1616 MaxInstLength = 16;
1616 #include "llvm/MC/MCAsmInfoELF.h"
1717 namespace llvm {
1818
19 class TargetTuple;
19 class Triple;
2020
2121 // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo,
2222 // you will need to make sure your new class sets PrivateGlobalPrefix to
2525 // with 'L' as a local symbol.
2626 class AMDGPUMCAsmInfo : public MCAsmInfoELF {
2727 public:
28 explicit AMDGPUMCAsmInfo(const TargetTuple &TT);
28 explicit AMDGPUMCAsmInfo(const Triple &TT);
2929 };
3030 } // namespace llvm
3131 #endif
4343 return X;
4444 }
4545
46 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const TargetTuple &TT) {
46 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
4747 MCRegisterInfo *X = new MCRegisterInfo();
4848 InitAMDGPUMCRegisterInfo(X, 0);
4949 return X;
5050 }
5151
52 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(const TargetTuple &TT,
53 StringRef CPU,
54 StringRef FS) {
52 static MCSubtargetInfo *
53 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
5554 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
5655 }
5756
58 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const TargetTuple &TT,
57 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
5958 Reloc::Model RM,
6059 CodeModel::Model CM,
6160 CodeGenOpt::Level OL) {
6463 return X;
6564 }
6665
67 static MCInstPrinter *createAMDGPUMCInstPrinter(const TargetTuple &T,
66 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
6867 unsigned SyntaxVariant,
6968 const MCAsmInfo &MAI,
7069 const MCInstrInfo &MII,
2727 class MCRegisterInfo;
2828 class MCSubtargetInfo;
2929 class Target;
30 class TargetTuple;
30 class Triple;
3131 class raw_pwrite_stream;
3232 class raw_ostream;
3333
4343 MCContext &Ctx);
4444
4545 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
46 const TargetTuple &TT, StringRef CPU);
46 const Triple &TT, StringRef CPU);
4747
4848 MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
4949 raw_pwrite_stream &OS);
557557 const Triple &TT = TM.getTargetTriple();
558558 StringRef CPU = TM.getTargetCPU();
559559 StringRef FS = TM.getTargetFeatureString();
560 std::string ArchFS = ARM_MC::ParseARMTargetTuple(TargetTuple(TT), CPU);
560 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
561561 if (!FS.empty()) {
562562 if (!ArchFS.empty())
563563 ArchFS = (Twine(ArchFS) + "," + FS).str();
8080 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
8181 const std::string &FS,
8282 const ARMBaseTargetMachine &TM, bool IsLittle)
83 : ARMGenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
83 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
8484 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
8585 TargetTriple(TT), Options(TM.Options), TM(TM),
8686 FrameLowering(initializeFrameLowering(CPU, FS)),
158158 // Insert the architecture feature derived from the target triple into the
159159 // feature string. This is important for setting features that are implied
160160 // based on the architecture version.
161 std::string ArchFS =
162 ARM_MC::ParseARMTargetTuple(TargetTuple(TargetTriple), CPUString);
161 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
163162 if (!FS.empty()) {
164163 if (!ArchFS.empty())
165164 ArchFS = (Twine(ArchFS) + "," + FS).str();
778778
779779 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
780780 const MCRegisterInfo &MRI,
781 const TargetTuple &TT, StringRef CPU,
781 const Triple &TheTriple, StringRef CPU,
782782 bool isLittle) {
783 switch (TT.getObjectFormat()) {
783 switch (TheTriple.getObjectFormat()) {
784784 default:
785785 llvm_unreachable("unsupported object format");
786 case TargetTuple::MachO: {
787 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
788 return new ARMAsmBackendDarwin(T, TT, CS);
789 }
790 case TargetTuple::COFF:
791 assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
792 return new ARMAsmBackendWinCOFF(T, TT);
793 case TargetTuple::ELF:
794 assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
795 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
796 return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
786 case Triple::MachO: {
787 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
788 return new ARMAsmBackendDarwin(T, TheTriple, CS);
789 }
790 case Triple::COFF:
791 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
792 return new ARMAsmBackendWinCOFF(T, TheTriple);
793 case Triple::ELF:
794 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
795 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
796 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
797797 }
798798 }
799799
800800 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
801801 const MCRegisterInfo &MRI,
802 const TargetTuple &TT,
803 StringRef CPU) {
802 const Triple &TT, StringRef CPU) {
804803 return createARMAsmBackend(T, MRI, TT, CPU, true);
805804 }
806805
807806 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
808807 const MCRegisterInfo &MRI,
809 const TargetTuple &TT,
810 StringRef CPU) {
808 const Triple &TT, StringRef CPU) {
811809 return createARMAsmBackend(T, MRI, TT, CPU, false);
812810 }
813811
814812 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
815813 const MCRegisterInfo &MRI,
816 const TargetTuple &TT,
817 StringRef CPU) {
814 const Triple &TT, StringRef CPU) {
818815 return createARMAsmBackend(T, MRI, TT, CPU, true);
819816 }
820817
821818 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
822819 const MCRegisterInfo &MRI,
823 const TargetTuple &TT,
824 StringRef CPU) {
820 const Triple &TT, StringRef CPU) {
825821 return createARMAsmBackend(T, MRI, TT, CPU, false);
826822 }
2222 bool isThumbMode; // Currently emitting Thumb code.
2323 bool IsLittleEndian; // Big or little endian.
2424 public:
25 ARMAsmBackend(const Target &T, const TargetTuple &TT, bool IsLittle)
25 ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
2626 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
2727 isThumbMode(TT.getArchName().startswith("thumb")),
2828 IsLittleEndian(IsLittle) {}
1717 class ARMAsmBackendDarwin : public ARMAsmBackend {
1818 public:
1919 const MachO::CPUSubTypeARM Subtype;
20 ARMAsmBackendDarwin(const Target &T, const TargetTuple &TT,
20 ARMAsmBackendDarwin(const Target &T, const Triple &TT,
2121 MachO::CPUSubTypeARM st)
2222 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
2323 HasDataInCodeSupport = true;
1414 class ARMAsmBackendELF : public ARMAsmBackend {
1515 public:
1616 uint8_t OSABI;
17 ARMAsmBackendELF(const Target &T, const TargetTuple &TT, uint8_t OSABI,
17 ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
1818 bool IsLittle)
1919 : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
2020
1414 namespace {
1515 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
1616 public:
17 ARMAsmBackendWinCOFF(const Target &T, const TargetTuple &TT)
18 : ARMAsmBackend(T, TT, true) {}
17 ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
18 : ARMAsmBackend(T, TheTriple, true) {}
1919 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
2020 return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
2121 }
13601360
13611361 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
13621362 const MCSubtargetInfo &STI) {
1363 const TargetTuple &TT = STI.getTargetTuple();
1363 const Triple &TT = STI.getTargetTriple();
13641364 if (TT.isOSBinFormatELF())
13651365 return new ARMTargetELFStreamer(S);
13661366 return new ARMTargetStreamer(S);
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "ARMMCAsmInfo.h"
14 #include "llvm/ADT/TargetTuple.h"
14 #include "llvm/ADT/Triple.h"
1515 #include "llvm/Support/CommandLine.h"
1616
1717 using namespace llvm;
1818
1919 void ARMMCAsmInfoDarwin::anchor() { }
2020
21 ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) {
22 if ((TT.getArch() == TargetTuple::armeb) ||
23 (TT.getArch() == TargetTuple::thumbeb))
21 ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
22 if ((TheTriple.getArch() == Triple::armeb) ||
23 (TheTriple.getArch() == Triple::thumbeb))
2424 IsLittleEndian = false;
2525
2626 Data64bitsDirective = nullptr;
3939
4040 void ARMELFMCAsmInfo::anchor() { }
4141
42 ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) {
43 if ((TT.getArch() == TargetTuple::armeb) ||
44 (TT.getArch() == TargetTuple::thumbeb))
42 ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
43 if ((TheTriple.getArch() == Triple::armeb) ||
44 (TheTriple.getArch() == Triple::thumbeb))
4545 IsLittleEndian = false;
4646
4747 // ".comm align is in bytes but .align is pow-2."
5555 SupportsDebugInformation = true;
5656
5757 // Exceptions handling
58 switch (TT.getOS()) {
59 case TargetTuple::Bitrig:
60 case TargetTuple::NetBSD:
58 switch (TheTriple.getOS()) {
59 case Triple::Bitrig:
60 case Triple::NetBSD:
6161 ExceptionsType = ExceptionHandling::DwarfCFI;
6262 break;
6363 default:
1818 #include "llvm/MC/MCAsmInfoELF.h"
1919
2020 namespace llvm {
21 class TargetTuple;
21 class Triple;
2222
2323 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
2424 virtual void anchor();
2525
2626 public:
27 explicit ARMMCAsmInfoDarwin(const TargetTuple &TT);
27 explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
2828 };
2929
3030 class ARMELFMCAsmInfo : public MCAsmInfoELF {
3131 void anchor() override;
3232
3333 public:
34 explicit ARMELFMCAsmInfo(const TargetTuple &TT);
34 explicit ARMELFMCAsmInfo(const Triple &TT);
3535
3636 void setUseIntegratedAssembler(bool Value) override;
3737 };
5656 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
5757 }
5858 bool isTargetMachO(const MCSubtargetInfo &STI) const {
59 const TargetTuple &TT = STI.getTargetTuple();
59 const Triple &TT = STI.getTargetTriple();
6060 return TT.isOSBinFormatMachO();
6161 }
6262
1414 #include "ARMMCAsmInfo.h"
1515 #include "ARMMCTargetDesc.h"
1616 #include "InstPrinter/ARMInstPrinter.h"
17 #include "llvm/ADT/TargetTuple.h"
17 #include "llvm/ADT/Triple.h"
1818 #include "llvm/MC/MCCodeGenInfo.h"
1919 #include "llvm/MC/MCELFStreamer.h"
2020 #include "llvm/MC/MCInstrAnalysis.h"
129129 #define GET_SUBTARGETINFO_MC_DESC
130130 #include "ARMGenSubtargetInfo.inc"
131131
132 std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) {
133 bool isThumb = TT.getArch() == TargetTuple::thumb ||
134 TT.getArch() == TargetTuple::thumbeb;
132 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
133 bool isThumb =
134 TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
135135
136136 bool NoCPU = CPU == "generic" || CPU.empty();
137137 std::string ARMArchFeature;
138138 switch (TT.getSubArch()) {
139139 default:
140140 llvm_unreachable("invalid sub-architecture for ARM");
141 case TargetTuple::ARMSubArch_v8:
141 case Triple::ARMSubArch_v8:
142142 if (NoCPU)
143143 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
144144 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
149149 // Use CPU to figure out the exact features
150150 ARMArchFeature = "+v8";
151151 break;
152 case TargetTuple::ARMSubArch_v8_1a:
152 case Triple::ARMSubArch_v8_1a:
153153 if (NoCPU)
154154 // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
155155 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
160160 // Use CPU to figure out the exact features
161161 ARMArchFeature = "+v8.1a";
162162 break;
163 case TargetTuple::ARMSubArch_v7m:
163 case Triple::ARMSubArch_v7m:
164164 isThumb = true;
165165 if (NoCPU)
166166 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
169169 // Use CPU to figure out the exact features.
170170 ARMArchFeature = "+v7";
171171 break;
172 case TargetTuple::ARMSubArch_v7em:
172 case Triple::ARMSubArch_v7em:
173173 if (NoCPU)
174174 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
175175 // FeatureT2XtPk, FeatureMClass
178178 // Use CPU to figure out the exact features.
179179 ARMArchFeature = "+v7";
180180 break;
181 case TargetTuple::ARMSubArch_v7s:
181 case Triple::ARMSubArch_v7s:
182182 if (NoCPU)
183183 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
184184 // Swift
187187 // Use CPU to figure out the exact features.
188188 ARMArchFeature = "+v7";
189189 break;
190 case TargetTuple::ARMSubArch_v7:
190 case Triple::ARMSubArch_v7:
191191 // v7 CPUs have lots of different feature sets. If no CPU is specified,
192192 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
193193 // the "minimum" feature set and use CPU string to figure out the exact
199199 // Use CPU to figure out the exact features.
200200 ARMArchFeature = "+v7";
201201 break;
202 case TargetTuple::ARMSubArch_v6t2:
202 case Triple::ARMSubArch_v6t2:
203203 ARMArchFeature = "+v6t2";
204204 break;
205 case TargetTuple::ARMSubArch_v6k:
205 case Triple::ARMSubArch_v6k:
206206 ARMArchFeature = "+v6k";
207207 break;
208 case TargetTuple::ARMSubArch_v6m:
208 case Triple::ARMSubArch_v6m:
209209 isThumb = true;
210210 if (NoCPU)
211211 // v6m: FeatureNoARM, FeatureMClass
213213 else
214214 ARMArchFeature = "+v6";
215215 break;
216 case TargetTuple::ARMSubArch_v6:
216 case Triple::ARMSubArch_v6:
217217 ARMArchFeature = "+v6";
218218 break;
219 case TargetTuple::ARMSubArch_v5te:
219 case Triple::ARMSubArch_v5te:
220220 ARMArchFeature = "+v5te";
221221 break;
222 case TargetTuple::ARMSubArch_v5:
222 case Triple::ARMSubArch_v5:
223223 ARMArchFeature = "+v5t";
224224 break;
225 case TargetTuple::ARMSubArch_v4t:
225 case Triple::ARMSubArch_v4t:
226226 ARMArchFeature = "+v4t";
227227 break;
228 case TargetTuple::NoSubArch:
228 case Triple::NoSubArch:
229229 break;
230230 }
231231
246246 return ARMArchFeature;
247247 }
248248
249 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const TargetTuple &TT,
249 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
250250 StringRef CPU, StringRef FS) {
251 std::string ArchFS = ARM_MC::ParseARMTargetTuple(TT, CPU);
251 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
252252 if (!FS.empty()) {
253253 if (!ArchFS.empty())
254254 ArchFS = (Twine(ArchFS) + "," + FS).str();
265265 return X;
266266 }
267267
268 static MCRegisterInfo *createARMMCRegisterInfo(const TargetTuple &TT) {
268 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
269269 MCRegisterInfo *X = new MCRegisterInfo();
270270 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
271271 return X;
272272 }
273273
274274 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
275 const TargetTuple &TT) {
275 const Triple &TheTriple) {
276276 MCAsmInfo *MAI;
277 if (TT.isOSDarwin() || TT.isOSBinFormatMachO())
278 MAI = new ARMMCAsmInfoDarwin(TT);
279 else if (TT.isWindowsMSVCEnvironment())
277 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
278 MAI = new ARMMCAsmInfoDarwin(TheTriple);
279 else if (TheTriple.isWindowsMSVCEnvironment())
280280 MAI = new ARMCOFFMCAsmInfoMicrosoft();
281 else if (TT.isOSWindows())
281 else if (TheTriple.isOSWindows())
282282 MAI = new ARMCOFFMCAsmInfoGNU();
283283 else
284 MAI = new ARMELFMCAsmInfo(TT);
284 MAI = new ARMELFMCAsmInfo(TheTriple);
285285
286286 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
287287 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
289289 return MAI;
290290 }
291291
292 static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT,
293 Reloc::Model RM,
292 static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
294293 CodeModel::Model CM,
295294 CodeGenOpt::Level OL) {
296295 MCCodeGenInfo *X = new MCCodeGenInfo();
302301 return X;
303302 }
304303
305 static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
304 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
306305 MCAsmBackend &MAB, raw_pwrite_stream &OS,
307306 MCCodeEmitter *Emitter, bool RelaxAll) {
308307 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
309 TT.getArch() == TargetTuple::thumb);
308 T.getArch() == Triple::thumb);
310309 }
311310
312311 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
316315 return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
317316 }
318317
319 static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT,
318 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
320319 unsigned SyntaxVariant,
321320 const MCAsmInfo &MAI,
322321 const MCInstrInfo &MII,
326325 return nullptr;
327326 }
328327
329 static MCRelocationInfo *createARMMCRelocationInfo(const TargetTuple &TT,
328 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
330329 MCContext &Ctx) {
331330 if (TT.isOSBinFormatMachO())
332331 return createARMMachORelocationInfo(Ctx);
3131 class MCTargetStreamer;
3232 class StringRef;
3333 class Target;
34 class TargetTuple;
34 class Triple;
3535 class raw_ostream;
3636 class raw_pwrite_stream;
3737
3939 extern Target TheARMBETarget, TheThumbBETarget;
4040
4141 namespace ARM_MC {
42 std::string ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU);
42 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
4343
4444 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
4545 /// do not need to go through TargetRegistry.
46 MCSubtargetInfo *createARMMCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
46 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
4747 StringRef FS);
4848 }
4949
6464 MCContext &Ctx);
6565
6666 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
67 const TargetTuple &TT, StringRef CPU,
67 const Triple &TT, StringRef CPU,
6868 bool IsLittleEndian);
6969
7070 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 const TargetTuple &TT, StringRef CPU);
71 const Triple &TT, StringRef CPU);
7272
7373 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 const TargetTuple &TT, StringRef CPU);
74 const Triple &TT, StringRef CPU);
7575
7676 MCAsmBackend *createThumbLEAsmBackend(const Target &T,
7777 const MCRegisterInfo &MRI,
78 const TargetTuple &TT, StringRef CPU);
78 const Triple &TT, StringRef CPU);
7979
8080 MCAsmBackend *createThumbBEAsmBackend(const Target &T,
8181 const MCRegisterInfo &MRI,
82 const TargetTuple &TT, StringRef CPU);
82 const Triple &TT, StringRef CPU);
8383
8484 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
8585 // object file.
2626
2727 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
2828 const std::string &FS, const TargetMachine &TM)
29 : BPFGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(),
30 FrameLowering(*this), TLInfo(TM, *this) {}
29 : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
30 TLInfo(TM, *this) {}
9494
9595 MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
9696 const MCRegisterInfo &MRI,
97 const TargetTuple &TT, StringRef CPU) {
97 const Triple &TT, StringRef CPU) {
9898 return new BPFAsmBackend(/*IsLittleEndian=*/true);
9999 }
100100
101101 MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
102102 const MCRegisterInfo &MRI,
103 const TargetTuple &TT,
104 StringRef CPU) {
103 const Triple &TT, StringRef CPU) {
105104 return new BPFAsmBackend(/*IsLittleEndian=*/false);
106105 }
1515
1616 #include "llvm/ADT/StringRef.h"
1717 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/ADT/TargetTuple.h"
18 #include "llvm/ADT/Triple.h"
1919
2020 namespace llvm {
2121 class Target;
22 class Triple;
2223
2324 class BPFMCAsmInfo : public MCAsmInfo {
2425 public:
25 explicit BPFMCAsmInfo(const TargetTuple &TT) {
26 if (TT.getArch() == TargetTuple::bpfeb)
26 explicit BPFMCAsmInfo(const Triple &TT) {
27 if (TT.getArch() == Triple::bpfeb)
2728 IsLittleEndian = false;
2829
2930 PrivateGlobalPrefix = ".L";
3939 return X;
4040 }
4141
42 static MCRegisterInfo *createBPFMCRegisterInfo(const TargetTuple &TT) {
42 static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
4343 MCRegisterInfo *X = new MCRegisterInfo();
4444 InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
4545 return X;
4646 }
4747
48 static MCSubtargetInfo *createBPFMCSubtargetInfo(const TargetTuple &TT,
48 static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
4949 StringRef CPU, StringRef FS) {
5050 return createBPFMCSubtargetInfoImpl(TT, CPU, FS);
5151 }
5252
53 static MCCodeGenInfo *createBPFMCCodeGenInfo(const TargetTuple &TT,
54 Reloc::Model RM,
53 static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
5554 CodeModel::Model CM,
5655 CodeGenOpt::Level OL) {
5756 MCCodeGenInfo *X = new MCCodeGenInfo();
5958 return X;
6059 }
6160
62 static MCStreamer *createBPFMCStreamer(const TargetTuple &TT, MCContext &Ctx,
63 MCAsmBackend &MAB, raw_pwrite_stream &OS,
64 MCCodeEmitter *Emitter, bool RelaxAll) {
61 static MCStreamer *createBPFMCStreamer(const Triple &T,
62 MCContext &Ctx, MCAsmBackend &MAB,
63 raw_pwrite_stream &OS, MCCodeEmitter *Emitter,
64 bool RelaxAll) {
6565 return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
6666 }
6767
68 static MCInstPrinter *createBPFMCInstPrinter(const TargetTuple &TT,
68 static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
6969 unsigned SyntaxVariant,
7070 const MCAsmInfo &MAI,
7171 const MCInstrInfo &MII,
2626 class MCSubtargetInfo;
2727 class StringRef;
2828 class Target;
29 class TargetTuple;
29 class Triple;
3030 class raw_ostream;
3131 class raw_pwrite_stream;
3232
4242 MCContext &Ctx);
4343
4444 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
45 const TargetTuple &TT, StringRef CPU);
45 const Triple &TT, StringRef CPU);
4646 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
47 const TargetTuple &TT, StringRef CPU);
47 const Triple &TT, StringRef CPU);
4848
4949 MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
5050 uint8_t OSABI, bool IsLittleEndian);
7171
7272 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
7373 StringRef FS, const TargetMachine &TM)
74 : HexagonGenSubtargetInfo(TargetTuple(TT), CPU, FS), CPUString(CPU),
74 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
7575 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
7676 FrameLowering() {
7777
308308 namespace llvm {
309309 MCAsmBackend *createHexagonAsmBackend(Target const &T,
310310 MCRegisterInfo const & /*MRI*/,
311 const TargetTuple &TT, StringRef CPU) {
311 const Triple &TT, StringRef CPU) {
312312 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
313313 return new HexagonAsmBackend(T, OSABI, CPU);
314314 }
1717 // Pin the vtable to this file.
1818 void HexagonMCAsmInfo::anchor() {}
1919
20 HexagonMCAsmInfo::HexagonMCAsmInfo(const TargetTuple &TT) {
20 HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
2121 Data16bitsDirective = "\t.half\t";
2222 Data32bitsDirective = "\t.word\t";
2323 Data64bitsDirective = nullptr; // .xword is only supported by V9.
1717 #include "llvm/MC/MCAsmInfoELF.h"
1818
1919 namespace llvm {
20 class TargetTuple;
20 class Triple;
2121
2222 class HexagonMCAsmInfo : public MCAsmInfoELF {
2323 void anchor() override;
2424
2525 public:
26 explicit HexagonMCAsmInfo(const TargetTuple &TT);
26 explicit HexagonMCAsmInfo(const Triple &TT);
2727 };
2828
2929 } // namespace llvm
4545 return X;
4646 }
4747
48 static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) {
48 static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
4949 MCRegisterInfo *X = new MCRegisterInfo();
5050 InitHexagonMCRegisterInfo(X, Hexagon::R0);
5151 return X;
5252 }
5353
54 static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT,
55 StringRef CPU,
56 StringRef FS) {
54 static MCSubtargetInfo *
55 createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
5756 return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
5857 }
5958
138137 }
139138
140139 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
141 const TargetTuple &TT) {
140 const Triple &TT) {
142141 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
143142
144143 // VirtualFP = (R30 + #0).
149148 return MAI;
150149 }
151150
152 static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT,
151 static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
153152 Reloc::Model RM,
154153 CodeModel::Model CM,
155154 CodeGenOpt::Level OL) {
160159 return X;
161160 }
162161
163 static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT,
162 static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
164163 unsigned SyntaxVariant,
165164 const MCAsmInfo &MAI,
166165 const MCInstrInfo &MII,
178177 return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint);
179178 }
180179
181 static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context,
180 static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
182181 MCAsmBackend &MAB, raw_pwrite_stream &OS,
183182 MCCodeEmitter *Emitter, bool RelaxAll) {
184183 return createHexagonELFStreamer(Context, MAB, OS, Emitter);
2626 class MCRegisterInfo;
2727 class MCSubtargetInfo;
2828 class Target;
29 class TargetTuple;
29 class Triple;
3030 class StringRef;
3131 class raw_ostream;
3232 class raw_pwrite_stream;
4343
4444 MCAsmBackend *createHexagonAsmBackend(Target const &T,
4545 MCRegisterInfo const &MRI,
46 const TargetTuple &TT, StringRef CPU);
46 const Triple &TT, StringRef CPU);
4747
4848 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
4949 uint8_t OSABI, StringRef CPU);
1515
1616 void MSP430MCAsmInfo::anchor() { }
1717
18 MSP430MCAsmInfo::MSP430MCAsmInfo(const TargetTuple &TT) {
18 MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) {
1919 PointerSize = CalleeSaveStackSlotSize = 2;
2020
2121 CommentString = ";";
1616 #include "llvm/MC/MCAsmInfoELF.h"
1717
1818 namespace llvm {
19 class TargetTuple;
19 class Triple;
2020
2121 class MSP430MCAsmInfo : public MCAsmInfoELF {
2222 void anchor() override;
2323
2424 public:
25 explicit MSP430MCAsmInfo(const TargetTuple &TT);
25 explicit MSP430MCAsmInfo(const Triple &TT);
2626 };
2727
2828 } // namespace llvm
3636 return X;
3737 }
3838
39 static MCRegisterInfo *createMSP430MCRegisterInfo(const TargetTuple &TT) {
39 static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
4040 MCRegisterInfo *X = new MCRegisterInfo();
4141 InitMSP430MCRegisterInfo(X, MSP430::PC);
4242 return X;
4343 }
4444
45 static MCSubtargetInfo *createMSP430MCSubtargetInfo(const TargetTuple &TT,
46 StringRef CPU,
47 StringRef FS) {
45 static MCSubtargetInfo *
46 createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
4847 return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
4948 }
5049
51 static MCCodeGenInfo *createMSP430MCCodeGenInfo(const TargetTuple &TT,
50 static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT,
5251 Reloc::Model RM,
5352 CodeModel::Model CM,
5453 CodeGenOpt::Level OL) {
5756 return X;
5857 }
5958
60 static MCInstPrinter *createMSP430MCInstPrinter(const TargetTuple &T,
59 static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
6160 unsigned SyntaxVariant,
6261 const MCAsmInfo &MAI,
6362 const MCInstrInfo &MII,
3232
3333 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
3434 const std::string &FS, const TargetMachine &TM)
35 : MSP430GenSubtargetInfo(TargetTuple(TT), CPU, FS), FrameLowering(),
35 : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
3636 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}
374374 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
375375 const MCInstrInfo &MII, const MCTargetOptions &Options)
376376 : MCTargetAsmParser(Options), STI(sti),
377 ABI(MipsABIInfo::computeTargetABI(sti.getTargetTuple(), sti.getCPU(),
378 Options)) {
377 ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
378 sti.getCPU(), Options)) {
379379 MCAsmParserExtension::Initialize(parser);
380380
381381 parser.addAliasForDirective(".asciiz", ".asciz");
401401 IsPicEnabled =
402402 (getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_);
403403
404 const TargetTuple &TT = sti.getTargetTuple();
405 if ((TT.getArch() == TargetTuple::mips) ||
406 (TT.getArch() == TargetTuple::mips64))
404 Triple TheTriple(sti.getTargetTriple());
405 if ((TheTriple.getArch() == Triple::mips) ||
406 (TheTriple.getArch() == Triple::mips64))
407407 IsLittleEndian = false;
408408 else
409409 IsLittleEndian = true;
4646 llvm_unreachable("Unhandled ABI");
4747 }
4848
49 MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU,
49 MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
5050 const MCTargetOptions &Options) {
5151 if (Options.getABIName().startswith("o32"))
5252 return MipsABIInfo::O32();
6363 // used and not shared in a couple of other places. This needs unifying
6464 // at some level.
6565 if (CPU.empty() || CPU == "generic") {
66 if (TT.getArch() == TargetTuple::mips ||
67 TT.getArch() == TargetTuple::mipsel)
66 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
6867 CPU = "mips32";
6968 else
7069 CPU = "mips64";
1010 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
1111
1212 #include "llvm/ADT/ArrayRef.h"
13 #include "llvm/ADT/TargetTuple.h"
13 #include "llvm/ADT/Triple.h"
1414 #include "llvm/IR/CallingConv.h"
1515 #include "llvm/MC/MCRegisterInfo.h"
1616
3535 static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
3636 static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
3737 static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
38 static MipsABIInfo computeTargetABI(const TargetTuple &TT, StringRef CPU,
38 static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
3939 const MCTargetOptions &Options);
4040
4141 bool IsKnown() const { return ThisABI != ABI::Unknown; }
410410 // MCAsmBackend
411411 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
412412 const MCRegisterInfo &MRI,
413 const TargetTuple &TT,
414 StringRef CPU) {
413 const Triple &TT, StringRef CPU) {
415414 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
416415 /*Is64Bit*/ false);
417416 }
418417
419418 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
420419 const MCRegisterInfo &MRI,
421 const TargetTuple &TT,
422 StringRef CPU) {
420 const Triple &TT, StringRef CPU) {
423421 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
424422 /*Is64Bit*/ false);
425423 }
426424
427425 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
428426 const MCRegisterInfo &MRI,
429 const TargetTuple &TT,
430 StringRef CPU) {
427 const Triple &TT, StringRef CPU) {
431428 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
432429 }
433430
434431 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
435432 const MCRegisterInfo &MRI,
436 const TargetTuple &TT,
437 StringRef CPU) {
433 const Triple &TT, StringRef CPU) {
438434 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
439435 /*Is64Bit*/ true);
440436 }
1515 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
1616
1717 #include "MCTargetDesc/MipsFixupKinds.h"
18 #include "llvm/ADT/TargetTuple.h"
18 #include "llvm/ADT/Triple.h"
1919 #include "llvm/MC/MCAsmBackend.h"
2020
2121 namespace llvm {
2626 class MCObjectWriter;
2727
2828 class MipsAsmBackend : public MCAsmBackend {
29 TargetTuple::OSType OSType;
29 Triple::OSType OSType;
3030 bool IsLittle; // Big or little endian
3131 bool Is64Bit; // 32 or 64 bit words
3232
3333 public:
34 MipsAsmBackend(const Target &T, TargetTuple::OSType OSType, bool IsLittle,
34 MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
3535 bool Is64Bit)
3636 : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
3737
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "MipsMCAsmInfo.h"
14 #include "llvm/ADT/TargetTuple.h"
14 #include "llvm/ADT/Triple.h"
1515
1616 using namespace llvm;
1717
1818 void MipsMCAsmInfo::anchor() { }
1919
20 MipsMCAsmInfo::MipsMCAsmInfo(const TargetTuple &TT) {
21 if ((TT.getArch() == TargetTuple::mips) ||
22 (TT.getArch() == TargetTuple::mips64))
20 MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
21 if ((TheTriple.getArch() == Triple::mips) ||
22 (TheTriple.getArch() == Triple::mips64))
2323 IsLittleEndian = false;
2424
25 if ((TT.getArch() == TargetTuple::mips64el) ||
26 (TT.getArch() == TargetTuple::mips64)) {
25 if ((TheTriple.getArch() == Triple::mips64el) ||
26 (TheTriple.getArch() == Triple::mips64)) {
2727 PointerSize = CalleeSaveStackSlotSize = 8;
2828 }
2929
1616 #include "llvm/MC/MCAsmInfoELF.h"
1717
1818 namespace llvm {
19 class TargetTuple;
19 class Triple;
2020
2121 class MipsMCAsmInfo : public MCAsmInfoELF {
2222 void anchor() override;
2323
2424 public:
25 explicit MipsMCAsmInfo(const TargetTuple &TT);
25 explicit MipsMCAsmInfo(const Triple &TheTriple);
2626 };
2727
2828 } // namespace llvm
1616 #include "MipsMCNaCl.h"
1717 #include "MipsMCTargetDesc.h"
1818 #include "MipsTargetStreamer.h"
19 #include "llvm/ADT/TargetTuple.h"
19 #include "llvm/ADT/Triple.h"
2020 #include "llvm/MC/MCCodeGenInfo.h"
2121 #include "llvm/MC/MCELFStreamer.h"
2222 #include "llvm/MC/MCInstrInfo.h"
4242
4343 /// Select the Mips CPU for the given triple and cpu name.
4444 /// FIXME: Merge with the copy in MipsSubtarget.cpp
45 StringRef MIPS_MC::selectMipsCPU(const TargetTuple &TT, StringRef CPU) {
45 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
4646 if (CPU.empty() || CPU == "generic") {
47 if (TT.getArch() == TargetTuple::mips ||
48 TT.getArch() == TargetTuple::mipsel)
47 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
4948 CPU = "mips32";
5049 else
5150 CPU = "mips64";
5958 return X;
6059 }
6160
62 static MCRegisterInfo *createMipsMCRegisterInfo(const TargetTuple &TT) {
61 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
6362 MCRegisterInfo *X = new MCRegisterInfo();
6463 InitMipsMCRegisterInfo(X, Mips::RA);
6564 return X;
6665 }
6766
68 static MCSubtargetInfo *createMipsMCSubtargetInfo(const TargetTuple &TT,
67 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
6968 StringRef CPU, StringRef FS) {
7069 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
7170 return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
7271 }
7372
7473 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
75 const TargetTuple &TT) {
74 const Triple &TT) {
7675 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
7776
7877 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
8281 return MAI;
8382 }
8483
85 static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT,
86 Reloc::Model RM,
84 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
8785 CodeModel::Model CM,
8886 CodeGenOpt::Level OL) {
8987 MCCodeGenInfo *X = new MCCodeGenInfo();
9593 return X;
9694 }
9795
98 static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T,
96 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
9997 unsigned SyntaxVariant,
10098 const MCAsmInfo &MAI,
10199 const MCInstrInfo &MII,
103101 return new MipsInstPrinter(MAI, MII, MRI);
104102 }
105103
106 static MCStreamer *createMCStreamer(const TargetTuple &T, MCContext &Context,
104 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
107105 MCAsmBackend &MAB, raw_pwrite_stream &OS,
108106 MCCodeEmitter *Emitter, bool RelaxAll) {
109107 MCStreamer *S;
2525 class MCSubtargetInfo;
2626 class StringRef;
2727 class Target;
28 class TargetTuple;
28 class Triple;
2929 class raw_ostream;
3030 class raw_pwrite_stream;
3131
4343
4444 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
4545 const MCRegisterInfo &MRI,
46 const TargetTuple &TT, StringRef CPU);
46 const Triple &TT, StringRef CPU);
4747 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
4848 const MCRegisterInfo &MRI,
49 const TargetTuple &TT, StringRef CPU);
49 const Triple &TT, StringRef CPU);
5050 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
5151 const MCRegisterInfo &MRI,
52 const TargetTuple &TT, StringRef CPU);
52 const Triple &TT, StringRef CPU);
5353 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
5454 const MCRegisterInfo &MRI,
55 const TargetTuple &TT, StringRef CPU);
55 const Triple &TT, StringRef CPU);
5656
5757 MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
5858 bool IsLittleEndian, bool Is64Bit);
5959
6060 namespace MIPS_MC {
61 StringRef selectMipsCPU(const TargetTuple &TT, StringRef CPU);
61 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
6262 }
6363
6464 } // End llvm namespace
692692 // clean anyhow.
693693 // FIXME: For ifunc related functions we could iterate over and look
694694 // for a feature string that doesn't match the default one.
695 TargetTuple TT(TargetTuple(TM.getTargetTriple()));
695 const Triple &TT = TM.getTargetTriple();
696696 StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
697697 StringRef FS = TM.getTargetFeatureString();
698698 const MipsTargetMachine &MTM = static_cast(TM);
699 const MipsSubtarget STI(TM.getTargetTriple(), CPU, FS, MTM.isLittleEndian(),
700 MTM);
699 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
701700
702701 bool IsABICalls = STI.isABICalls();
703702 const MipsABIInfo &ABI = MTM.getABI();
6161 MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
6262 const std::string &FS, bool little,
6363 const MipsTargetMachine &TM)
64 : MipsGenSubtargetInfo(TargetTuple(TT), CPU, FS),
65 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
66 IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false),
67 UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
68 HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false),
69 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
70 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
71 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
72 AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
73 UseTCCInDIV(false), HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(),
64 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
65 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
66 NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
67 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
68 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
69 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
70 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
71 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
72 HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
73 TargetTriple(TT), TSInfo(),
7474 InstrInfo(
7575 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
7676 FrameLowering(MipsFrameLowering::create(*this)),
141141 MipsSubtarget &
142142 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
143143 const TargetMachine &TM) {
144 std::string CPUName =
145 MIPS_MC::selectMipsCPU(TargetTuple(TM.getTargetTriple()), CPU);
144 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
146145
147146 // Parse features string.
148147 ParseSubtargetFeatures(CPUName, FS);
4747 const TargetOptions &Options,
4848 bool isLittle) {
4949 std::string Ret = "";
50 MipsABIInfo ABI =
51 MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU, Options.MCOptions);
50 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
5251
5352 // There are both little and big endian mips.
5453 if (isLittle)
9089 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
9190 CPU, FS, Options, RM, CM, OL),
9291 isLittle(isLittle), TLOF(make_unique()),
93 ABI(MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU,
94 Options.MCOptions)),
92 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
9593 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
9694 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
9795 isLittle, *this),
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "NVPTXMCAsmInfo.h"
14 #include "llvm/ADT/TargetTuple.h"
14 #include "llvm/ADT/Triple.h"
1515 #include "llvm/Support/CommandLine.h"
1616
1717 using namespace llvm;
2424
2525 void NVPTXMCAsmInfo::anchor() {}
2626
27 NVPTXMCAsmInfo::NVPTXMCAsmInfo(const TargetTuple &TT) {
28 if (TT.getArch() == TargetTuple::nvptx64) {
27 NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) {
28 if (TheTriple.getArch() == Triple::nvptx64) {
2929 PointerSize = CalleeSaveStackSlotSize = 8;
3030 }
3131
1717
1818 namespace llvm {
1919 class Target;
20 class TargetTuple;
20 class Triple;
2121
2222 class NVPTXMCAsmInfo : public MCAsmInfo {
2323 virtual void anchor();
2424
2525 public:
26 explicit NVPTXMCAsmInfo(const TargetTuple &TT);
26 explicit NVPTXMCAsmInfo(const Triple &TheTriple);
2727 };
2828 } // namespace llvm
2929
3636 return X;
3737 }
3838
39 static MCRegisterInfo *createNVPTXMCRegisterInfo(const TargetTuple &TT) {
39 static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) {
4040 MCRegisterInfo *X = new MCRegisterInfo();
4141 // PTX does not have a return address register.
4242 InitNVPTXMCRegisterInfo(X, 0);
4444 }
4545
4646 static MCSubtargetInfo *
47 createNVPTXMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
47 createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
4848 return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
4949 }
5050
51 static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const TargetTuple &TT,
51 static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT,
5252 Reloc::Model RM,
5353 CodeModel::Model CM,
5454 CodeGenOpt::Level OL) {
6060 return X;
6161 }
6262
63 static MCInstPrinter *createNVPTXMCInstPrinter(const TargetTuple &T,
63 static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
6464 unsigned SyntaxVariant,
6565 const MCAsmInfo &MAI,
6666 const MCInstrInfo &MII,
4545 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
4646 const std::string &FS,
4747 const NVPTXTargetMachine &TM)
48 : NVPTXGenSubtargetInfo(TargetTuple(TT), CPU, FS), PTXVersion(0),
49 SmVersion(20), TM(TM), InstrInfo(),
50 TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), TSInfo(),
48 : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM),
49 InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
5150 FrameLowering() {}
5251
5352 bool NVPTXSubtarget::hasImageHandles() const {
294294 const MCTargetOptions &Options)
295295 : MCTargetAsmParser(Options), STI(STI), MII(MII) {
296296 // Check for 64-bit vs. 32-bit pointer mode.
297 const TargetTuple &TT = STI.getTargetTuple();
298 IsPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
299 TT.getArch() == TargetTuple::ppc64le);
300 IsDarwin = TT.isMacOSX();
297 Triple TheTriple(STI.getTargetTriple());
298 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
299 TheTriple.getArch() == Triple::ppc64le);
300 IsDarwin = TheTriple.isMacOSX();
301301 // Initialize the set of available features.
302302 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
303303 }
229229
230230 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
231231 const MCRegisterInfo &MRI,
232 const TargetTuple &TT, StringRef CPU) {
232 const Triple &TT, StringRef CPU) {
233233 if (TT.isOSDarwin())
234234 return new DarwinPPCAsmBackend(T);
235235
236236 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
237 bool IsLittleEndian = TT.getArch() == TargetTuple::ppc64le;
237 bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
238238 return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI);
239239 }
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "PPCMCAsmInfo.h"
14 #include "llvm/ADT/TargetTuple.h"
14 #include "llvm/ADT/Triple.h"
1515
1616 using namespace llvm;
1717
1818 void PPCMCAsmInfoDarwin::anchor() { }
1919
20 PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &TT) {
20 PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
2121 if (is64Bit) {
2222 PointerSize = CalleeSaveStackSlotSize = 8;
2323 }
3535 // The installed assembler for OSX < 10.6 lacks some directives.
3636 // FIXME: this should really be a check on the assembler characteristics
3737 // rather than OS version
38 if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6))
38 if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
3939 HasWeakDefCanBeHiddenDirective = false;
4040
4141 UseIntegratedAssembler = true;
4343
4444 void PPCELFMCAsmInfo::anchor() { }
4545
46 PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &TT) {
46 PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) {
4747 // FIXME: This is not always needed. For example, it is not needed in the
4848 // v2 abi.
4949 NeedsLocalForSize = true;
5151 if (is64Bit) {
5252 PointerSize = CalleeSaveStackSlotSize = 8;
5353 }
54 IsLittleEndian = TT.getArch() == TargetTuple::ppc64le;
54 IsLittleEndian = T.getArch() == Triple::ppc64le;
5555
5656 // ".comm align is in bytes but .align is pow-2."
5757 AlignmentIsInBytes = false;
1717 #include "llvm/MC/MCAsmInfoELF.h"
1818
1919 namespace llvm {
20 class TargetTuple;
20 class Triple;
2121
2222 class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
2323 virtual void anchor();
2424
2525 public:
26 explicit PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &);
26 explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &);
2727 };
2828
2929 class PPCELFMCAsmInfo : public MCAsmInfoELF {
3030 void anchor() override;
3131
3232 public:
33 explicit PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &);
33 explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &);
3434 };
3535
3636 } // namespace llvm
308308 // Return the thread-pointer register's encoding.
309309 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
310310 (MCFixupKind)PPC::fixup_ppc_nofixup));
311 const TargetTuple &TT = STI.getTargetTuple();
312 bool isPPC64 = TT.getArch() == TargetTuple::ppc64 ||
313 TT.getArch() == TargetTuple::ppc64le;
311 const Triple &TT = STI.getTargetTriple();
312 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
314313 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
315314 }
316315
5050 return X;
5151 }
5252
53 static MCRegisterInfo *createPPCMCRegisterInfo(const TargetTuple &TT) {
54 bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
55 TT.getArch() == TargetTuple::ppc64le);
53 static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
54 bool isPPC64 =
55 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
5656 unsigned Flavour = isPPC64 ? 0 : 1;
5757 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
5858
6161 return X;
6262 }
6363
64 static MCSubtargetInfo *createPPCMCSubtargetInfo(const TargetTuple &TT,
64 static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
6565 StringRef CPU, StringRef FS) {
6666 return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
6767 }
6868
6969 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
70 const TargetTuple &TT) {
71 bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 ||
72 TT.getArch() == TargetTuple::ppc64le);
70 const Triple &TheTriple) {
71 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
72 TheTriple.getArch() == Triple::ppc64le);
7373
7474 MCAsmInfo *MAI;
75 if (TT.isOSDarwin())
76 MAI = new PPCMCAsmInfoDarwin(isPPC64, TT);
75 if (TheTriple.isOSDarwin())
76 MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
7777 else
78 MAI = new PPCELFMCAsmInfo(isPPC64, TT);
78 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
7979
8080 // Initial state of the frame pointer is R1.
8181 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
8686 return MAI;
8787 }
8888
89 static MCCodeGenInfo *createPPCMCCodeGenInfo(const TargetTuple &TT,
90 Reloc::Model RM,
89 static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
9190 CodeModel::Model CM,
9291 CodeGenOpt::Level OL) {
9392 MCCodeGenInfo *X = new MCCodeGenInfo();
9998 RM = Reloc::Static;
10099 }
101100 if (CM == CodeModel::Default) {
102 if (!TT.isOSDarwin() && (TT.getArch() == TargetTuple::ppc64 ||
103 TT.getArch() == TargetTuple::ppc64le))
101 if (!TT.isOSDarwin() &&
102 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
104103 CM = CodeModel::Medium;
105104 }
106105 X->initMCCodeGenInfo(RM, CM, OL);
225224
226225 static MCTargetStreamer *
227226 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
228 const TargetTuple &TT = STI.getTargetTuple();
227 const Triple &TT = STI.getTargetTriple();
229228 if (TT.isOSBinFormatELF())
230229 return new PPCTargetELFStreamer(S);
231230 return new PPCTargetMachOStreamer(S);
232231 }
233232
234 static MCInstPrinter *createPPCMCInstPrinter(const TargetTuple &TT,
233 static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
235234 unsigned SyntaxVariant,
236235 const MCAsmInfo &MAI,
237236 const MCInstrInfo &MII,
238237 const MCRegisterInfo &MRI) {
239 return new PPCInstPrinter(MAI, MII, MRI, TT.isOSDarwin());
238 return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
240239 }
241240
242241 extern "C" void LLVMInitializePowerPCTargetMC() {
2828 class MCRegisterInfo;
2929 class MCSubtargetInfo;
3030 class Target;
31 class TargetTuple;
31 class Triple;
3232 class StringRef;
3333 class raw_pwrite_stream;
3434 class raw_ostream;
4242 MCContext &Ctx);
4343
4444 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
45 const TargetTuple &TT, StringRef CPU);
45 const Triple &TT, StringRef CPU);
4646
4747 /// Construct an PPC ELF object writer.
4848 MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
4848
4949 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
5050 const std::string &FS, const PPCTargetMachine &TM)
51 : PPCGenSubtargetInfo(TargetTuple(TT), CPU, FS), TargetTriple(TT),
51 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
5252 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
5353 TargetTriple.getArch() == Triple::ppc64le),
5454 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
7676 bool parseDirectiveWord(unsigned Size, SMLoc L);
7777
7878 bool is64Bit() const {
79 return STI.getTargetTuple().getArch() == TargetTuple::sparcv9;
79 return STI.getTargetTriple().getArch() == Triple::sparcv9;
8080 }
8181
8282 void expandSET(MCInst &Inst, SMLoc IDLoc,
266266 };
267267
268268 class ELFSparcAsmBackend : public SparcAsmBackend {
269 TargetTuple::OSType OSType;
270
269 Triple::OSType OSType;
271270 public:
272 ELFSparcAsmBackend(const Target &T, TargetTuple::OSType OSType)
273 : SparcAsmBackend(T), OSType(OSType) {}
271 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
272 SparcAsmBackend(T), OSType(OSType) { }
274273
275274 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
276275 uint64_t Value, bool IsPCRel) const override {
299298
300299 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
301300 const MCRegisterInfo &MRI,
302 const TargetTuple &TT,
303 StringRef CPU) {
301 const Triple &TT, StringRef CPU) {
304302 return new ELFSparcAsmBackend(T, TT.getOS());
305303 }
1212
1313 #include "SparcMCAsmInfo.h"
1414 #include "SparcMCExpr.h"
15 #include "llvm/ADT/TargetTuple.h"
15 #include "llvm/ADT/Triple.h"
1616 #include "llvm/MC/MCStreamer.h"
1717
1818 using namespace llvm;
1919
2020 void SparcELFMCAsmInfo::anchor() {}
2121
22 SparcELFMCAsmInfo::SparcELFMCAsmInfo(const TargetTuple &TT) {
23 bool isV9 = (TT.getArch() == TargetTuple::sparcv9);
24 IsLittleEndian = (TT.getArch() == TargetTuple::sparcel);
22 SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) {
23 bool isV9 = (TheTriple.getArch() == Triple::sparcv9);
24 IsLittleEndian = (TheTriple.getArch() == Triple::sparcel);
2525
2626 if (isV9) {
2727 PointerSize = CalleeSaveStackSlotSize = 8;
1616 #include "llvm/MC/MCAsmInfoELF.h"
1717
1818 namespace llvm {
19 class TargetTuple;
19 class Triple;
2020
2121 class SparcELFMCAsmInfo : public MCAsmInfoELF {
2222 void anchor() override;
2323
2424 public:
25 explicit SparcELFMCAsmInfo(const TargetTuple &TT);
25 explicit SparcELFMCAsmInfo(const Triple &TheTriple);
2626 const MCExpr*
2727 getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
2828 MCStreamer &Streamer) const override;
3333 #include "SparcGenRegisterInfo.inc"
3434
3535 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
36 const TargetTuple &TT) {
36 const Triple &TT) {
3737 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
3838 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
3939 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
4242 }
4343
4444 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
45 const TargetTuple &TT) {
45 const Triple &TT) {
4646 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
4747 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
4848 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
5656 return X;
5757 }
5858
59 static MCRegisterInfo *createSparcMCRegisterInfo(const TargetTuple &TT) {
59 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
6060 MCRegisterInfo *X = new MCRegisterInfo();
6161 InitSparcMCRegisterInfo(X, SP::O7);
6262 return X;
6363 }
6464
6565 static MCSubtargetInfo *
66 createSparcMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) {
66 createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
6767 if (CPU.empty())
68 CPU = (TT.getArch() == TargetTuple::sparcv9) ? "v9" : "v8";
68 CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
6969 return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
7070 }
7171
8080 //
8181 // All code models require that the text segment is smaller than 2GB.
8282
83 static MCCodeGenInfo *createSparcMCCodeGenInfo(const TargetTuple &TT,
83 static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT,
8484 Reloc::Model RM,
8585 CodeModel::Model CM,
8686 CodeGenOpt::Level OL) {
9898 return X;
9999 }
100100
101 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const TargetTuple &TT,
101 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT,
102102 Reloc::Model RM,
103103 CodeModel::Model CM,
104104 CodeGenOpt::Level OL) {
132132 return new SparcTargetAsmStreamer(S, OS);
133133 }
134134
135 static MCInstPrinter *createSparcMCInstPrinter(const TargetTuple &TT,
135 static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,