llvm.org GIT mirror llvm / 4776c1f
[GlobalISel] Accept multiple vregs in lowerFormalArgs Change the interface of CallLowering::lowerFormalArguments to accept several virtual registers for each formal argument, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660. lowerCall will be refactored in the same way in follow-up patches. With this change, we forward the virtual registers generated for aggregates to CallLowering. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. We also copy the pack/unpackRegs helpers to CallLowering to facilitate this. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was put into a s64 instead of a p0. Added a test-case which illustrates the problem more clearly (it crashes without this patch) and fixed the existing test-case to expect p0. AMDGPU has been updated to unpack into the virtual registers for kernels. I think the other code paths fall back for aggregates, so this should be NFC. Mips doesn't support aggregates yet, so it's also NFC. x86 seems to have code for dealing with aggregates, but I couldn't find the tests for it, so I just added a fallback to DAGISel if we get more than one virtual register for an argument. Differential Revision: https://reviews.llvm.org/D63549 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364510 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 1 year, 2 months ago
17 changed file(s) with 216 addition(s) and 157 deletion(s). Raw diff Collapse all Expand all
5151 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy{}, bool IsFixed = true)
5252 : Regs(Regs.begin(), Regs.end()), Ty(Ty), Flags(Flags),
5353 IsFixed(IsFixed) {
54 assert(Regs.size() == 1 && "Can't handle multiple regs yet");
55 assert((Ty->isVoidTy() == (Regs[0] == 0)) &&
54 // FIXME: We should have just one way of saying "no register".
55 assert((Ty->isVoidTy() == (Regs.empty() || Regs[0] == 0)) &&
5656 "only void types should have no register");
5757 }
5858 };
138138 void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL,
139139 const FuncInfoTy &FuncInfo) const;
140140
141 /// Generate instructions for packing \p SrcRegs into one big register
142 /// corresponding to the aggregate type \p PackedTy.
143 ///
144 /// \param SrcRegs should contain one virtual register for each base type in
145 /// \p PackedTy, as returned by computeValueLLTs.
146 ///
147 /// \return The packed register.
148 Register packRegs(ArrayRef SrcRegs, Type *PackedTy,
149 MachineIRBuilder &MIRBuilder) const;
150
151 /// Generate instructions for unpacking \p SrcReg into the \p DstRegs
152 /// corresponding to the aggregate type \p PackedTy.
153 ///
154 /// \param DstRegs should contain one virtual register for each base type in
155 /// \p PackedTy, as returned by computeValueLLTs.
156 void unpackRegs(ArrayRef DstRegs, Register SrcReg, Type *PackedTy,
157 MachineIRBuilder &MIRBuilder) const;
158
141159 /// Invoke Handler::assignArg on each of the given \p Args and then use
142160 /// \p Callback to move them to the assigned locations.
143161 ///
181199 return false;
182200 }
183201
184
185202 /// This hook must be implemented to lower the incoming (formal)
186 /// arguments, described by \p Args, for GlobalISel. Each argument
187 /// must end up in the related virtual register described by VRegs.
188 /// In other words, the first argument should end up in VRegs[0],
189 /// the second in VRegs[1], and so on.
203 /// arguments, described by \p VRegs, for GlobalISel. Each argument
204 /// must end up in the related virtual registers described by \p VRegs.
205 /// In other words, the first argument should end up in \c VRegs[0],
206 /// the second in \c VRegs[1], and so on. For each argument, there will be one
207 /// register for each non-aggregate type, as returned by \c computeValueLLTs.
190208 /// \p MIRBuilder is set to the proper insertion for the argument
191209 /// lowering.
192210 ///
193211 /// \return True if the lowering succeeded, false otherwise.
194212 virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder,
195213 const Function &F,
196 ArrayRef<Register> VRegs) const {
214 ArrayRef<ArrayRef> VRegs) const {
197215 return false;
198216 }
199217
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
14 #include "llvm/CodeGen/Analysis.h"
1415 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
1516 #include "llvm/CodeGen/MachineOperand.h"
1617 #include "llvm/CodeGen/MachineRegisterInfo.h"
113114 CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
114115 const DataLayout &DL,
115116 const CallInst &FuncInfo) const;
117
118 Register CallLowering::packRegs(ArrayRef SrcRegs, Type *PackedTy,
119 MachineIRBuilder &MIRBuilder) const {
120 assert(SrcRegs.size() > 1 && "Nothing to pack");
121
122 const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
123 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
124
125 LLT PackedLLT = getLLTForType(*PackedTy, DL);
126
127 SmallVector LLTs;
128 SmallVector Offsets;
129 computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
130 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch");
131
132 Register Dst = MRI->createGenericVirtualRegister(PackedLLT);
133 MIRBuilder.buildUndef(Dst);
134 for (unsigned i = 0; i < SrcRegs.size(); ++i) {
135 Register NewDst = MRI->createGenericVirtualRegister(PackedLLT);
136 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]);
137 Dst = NewDst;
138 }
139
140 return Dst;
141 }
142
143 void CallLowering::unpackRegs(ArrayRef DstRegs, Register SrcReg,
144 Type *PackedTy,
145 MachineIRBuilder &MIRBuilder) const {
146 assert(DstRegs.size() > 1 && "Nothing to unpack");
147
148 const DataLayout &DL = MIRBuilder.getMF().getDataLayout();
149
150 SmallVector LLTs;
151 SmallVector Offsets;
152 computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
153 assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
154
155 for (unsigned i = 0; i < DstRegs.size(); ++i)
156 MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);
157 }
116158
117159 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
118160 ArrayRef Args,
22732273 EntryBB->addSuccessor(&getMBB(F.front()));
22742274
22752275 // Lower the actual args into this basic block.
2276 SmallVector<Register, 8> VRegArgs;
2276 SmallVector<ArrayRef, 8> VRegArgs;
22772277 for (const Argument &Arg: F.args()) {
22782278 if (DL->getTypeStoreSize(Arg.getType()) == 0)
22792279 continue; // Don't handle zero sized types.
2280 VRegArgs.push_back(
2281 MRI->createGenericVirtualRegister(getLLTForType(*Arg.getType(), *DL)));
2282
2283 if (Arg.hasSwiftErrorAttr())
2284 SwiftError.setCurrentVReg(EntryBB, SwiftError.getFunctionArg(),
2285 VRegArgs.back());
2280 ArrayRef VRegs = getOrCreateVRegs(Arg);
2281 VRegArgs.push_back(VRegs);
2282
2283 if (Arg.hasSwiftErrorAttr()) {
2284 assert(VRegs.size() == 1 && "Too many vregs for Swift error");
2285 SwiftError.setCurrentVReg(EntryBB, SwiftError.getFunctionArg(), VRegs[0]);
2286 }
22862287 }
22872288
22882289 // We don't currently support translating swifterror or swiftself functions.
23032304 R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
23042305 reportTranslationError(*MF, *TPC, *ORE, R);
23052306 return false;
2306 }
2307
2308 auto ArgIt = F.arg_begin();
2309 for (auto &VArg : VRegArgs) {
2310 // If the argument is an unsplit scalar then don't use unpackRegs to avoid
2311 // creating redundant copies.
2312 if (!valueIsSplit(*ArgIt, VMap.getOffsets(*ArgIt))) {
2313 auto &VRegs = *VMap.getVRegs(cast(*ArgIt));
2314 assert(VRegs.empty() && "VRegs already populated?");
2315 VRegs.push_back(VArg);
2316 } else {
2317 unpackRegs(*ArgIt, VArg, *EntryBuilder.get());
2318 }
2319 ArgIt++;
23202307 }
23212308
23222309 // Need to visit defs before uses when translating instructions.
202202 SmallVector SplitVTs;
203203 SmallVector Offsets;
204204 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
205 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
206205
207206 if (SplitVTs.size() == 1) {
208207 // No splitting to do, but we want to replace the original type (e.g. [1 x
209208 // double] -> double).
210209 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
211210 OrigArg.Flags, OrigArg.IsFixed);
211 return;
212 }
213
214 if (OrigArg.Regs.size() > 1) {
215 // Create one ArgInfo for each virtual register in the original ArgInfo.
216 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
217
218 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
219 OrigArg.Ty, CallConv, false);
220 for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
221 Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
222 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags,
223 OrigArg.IsFixed);
224 if (NeedsRegBlock)
225 SplitArgs.back().Flags.setInConsecutiveRegs();
226 }
227
228 SplitArgs.back().Flags.setInConsecutiveRegsLast();
212229 return;
213230 }
214231
350367 return Success;
351368 }
352369
353 bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
354 const Function &F,
355 ArrayRef VRegs) const {
370 bool AArch64CallLowering::lowerFormalArguments(
371 MachineIRBuilder &MIRBuilder, const Function &F,
372 ArrayRef> VRegs) const {
356373 MachineFunction &MF = MIRBuilder.getMF();
357374 MachineBasicBlock &MBB = MIRBuilder.getMBB();
358375 MachineRegisterInfo &MRI = MF.getRegInfo();
363380 for (auto &Arg : F.args()) {
364381 if (DL.getTypeStoreSize(Arg.getType()) == 0)
365382 continue;
383
366384 ArgInfo OrigArg{VRegs[i], Arg.getType()};
367385 setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
368 bool Split = false;
369 LLT Ty = MRI.getType(VRegs[i]);
370 Register Dst = VRegs[i];
371386
372387 splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
373 [&](unsigned Reg, uint64_t Offset) {
374 if (!Split) {
375 Split = true;
376 Dst = MRI.createGenericVirtualRegister(Ty);
377 MIRBuilder.buildUndef(Dst);
378 }
379 unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
380 MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset);
381 Dst = Tmp;
388 [&](Register Reg, uint64_t Offset) {
389 llvm_unreachable("Args should already be split");
382390 });
383
384 if (Dst != VRegs[i])
385 MIRBuilder.buildCopy(VRegs[i], Dst);
386391 ++i;
387392 }
388393
3737 Register SwiftErrorVReg) const override;
3838
3939 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
40 ArrayRef<Register> VRegs) const override;
40 ArrayRef<ArrayRef> VRegs) const override;
4141
4242 bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
4343 const MachineOperand &Callee, const ArgInfo &OrigRet,
192192 }
193193 }
194194
195 bool AMDGPUCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
196 const Function &F,
197 ArrayRef VRegs) const {
195 bool AMDGPUCallLowering::lowerFormalArguments(
196 MachineIRBuilder &MIRBuilder, const Function &F,
197 ArrayRef> VRegs) const {
198198 // AMDGPU_GS and AMDGP_HS are not supported yet.
199199 if (F.getCallingConv() == CallingConv::AMDGPU_GS ||
200200 F.getCallingConv() == CallingConv::AMDGPU_HS)
274274 uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
275275 ExplicitArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + AllocSize;
276276
277 ArrayRef OrigArgRegs = VRegs[i];
278 Register ArgReg =
279 OrigArgRegs.size() == 1
280 ? OrigArgRegs[0]
281 : MRI.createGenericVirtualRegister(getLLTForType(*ArgTy, DL));
277282 unsigned Align = MinAlign(KernArgBaseAlign, ArgOffset);
278283 ArgOffset = alignTo(ArgOffset, DL.getABITypeAlignment(ArgTy));
279 lowerParameter(MIRBuilder, ArgTy, ArgOffset, Align, VRegs[i]);
284 lowerParameter(MIRBuilder, ArgTy, ArgOffset, Align, ArgReg);
285 if (OrigArgRegs.size() > 1)
286 unpackRegs(OrigArgRegs, ArgReg, ArgTy, MIRBuilder);
280287 ++i;
281288 }
282289
294301
295302 // We can only hanlde simple value types at the moment.
296303 ISD::ArgFlagsTy Flags;
297 ArgInfo OrigArg{VRegs[i], CurOrigArg->getType()};
304 assert(VRegs[i].size() == 1 && "Can't lower into more than one register");
305 ArgInfo OrigArg{VRegs[i][0], CurOrigArg->getType()};
298306 setArgFlags(OrigArg, i + 1, DL, F);
299307 Flags.setOrigAlign(DL.getABITypeAlignment(CurOrigArg->getType()));
300308
347355 OrigArgIdx != NumArgs && i != ArgLocs.size(); ++Arg, ++OrigArgIdx) {
348356 if (Skipped.test(OrigArgIdx))
349357 continue;
350 CCValAssign &VA = ArgLocs[i++];
351 MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx]);
352 MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
353 MIRBuilder.buildCopy(VRegs[OrigArgIdx], VA.getLocReg());
358 assert(VRegs[OrigArgIdx].size() == 1 &&
359 "Can't lower into more than 1 reg");
360 CCValAssign &VA = ArgLocs[i++];
361 MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx][0]);
362 MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
363 MIRBuilder.buildCopy(VRegs[OrigArgIdx][0], VA.getLocReg());
354364 }
355365
356366 allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), IsShader);
3434 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
3535 ArrayRef VRegs) const override;
3636 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
37 ArrayRef<Register> VRegs) const override;
37 ArrayRef<ArrayRef> VRegs) const override;
3838 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
3939 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
4040 };
194194
195195 SmallVector SplitVTs;
196196 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
197 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
198197
199198 if (SplitVTs.size() == 1) {
200199 // Even if there is no splitting to do, we still want to replace the
201200 // original type (e.g. pointer type -> integer).
201 assert(OrigArg.Regs.size() == 1 && "Regs / types mismatch");
202202 auto Flags = OrigArg.Flags;
203203 unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
204204 Flags.setOrigAlign(OriginalAlignment);
205205 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
206206 Flags, OrigArg.IsFixed);
207 return;
208 }
209
210 if (OrigArg.Regs.size() > 1) {
211 // Create one ArgInfo for each virtual register.
212 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
213 for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
214 EVT SplitVT = SplitVTs[i];
215 Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
216 auto Flags = OrigArg.Flags;
217
218 unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
219 Flags.setOrigAlign(OriginalAlignment);
220
221 bool NeedsConsecutiveRegisters =
222 TLI.functionArgumentNeedsConsecutiveRegisters(
223 SplitTy, F.getCallingConv(), F.isVarArg());
224 if (NeedsConsecutiveRegisters) {
225 Flags.setInConsecutiveRegs();
226 if (i == e - 1)
227 Flags.setInConsecutiveRegsLast();
228 }
229
230 // FIXME: We also want to split SplitTy further.
231 Register PartReg = OrigArg.Regs[i];
232 SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
233 }
234
207235 return;
208236 }
209237
423451
424452 } // end anonymous namespace
425453
426 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
427 const Function &F,
428 ArrayRef VRegs) const {
454 bool ARMCallLowering::lowerFormalArguments(
455 MachineIRBuilder &MIRBuilder, const Function &F,
456 ArrayRef> VRegs) const {
429457 auto &TLI = *getTLI();
430458 auto Subtarget = TLI.getSubtarget();
431459
456484 FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
457485 AssignFn);
458486
459 SmallVector ArgInfos;
460 SmallVector<Register, 4> SplitRegs;
487 SmallVector<ArgInfo, 8> SplitArgInfos;
461488 unsigned Idx = 0;
462489 for (auto &Arg : F.args()) {
463 ArgInfo AInfo(VRegs[Idx], Arg.getType());
464 setArgFlags(AInfo, Idx + AttributeList::FirstArgIndex, DL, F);
465
466 SplitRegs.clear();
467
468 splitToValueTypes(AInfo, ArgInfos, MF,
469 [&](Register Reg) { SplitRegs.push_back(Reg); });
470
471 if (!SplitRegs.empty())
472 MIRBuilder.buildMerge(VRegs[Idx], SplitRegs);
490 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
491 setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
492
493 splitToValueTypes(OrigArgInfo, SplitArgInfos, MF, [&](Register Reg) {
494 llvm_unreachable("Args should already be split");
495 });
473496
474497 Idx++;
475498 }
477500 if (!MBB.empty())
478501 MIRBuilder.setInstr(*MBB.begin());
479502
480 if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
503 if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
481504 return false;
482505
483506 // Move back to the end of the basic block.
3535 ArrayRef VRegs) const override;
3636
3737 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
38 ArrayRef<Register> VRegs) const override;
38 ArrayRef<ArrayRef> VRegs) const override;
3939
4040 bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
4141 const MachineOperand &Callee, const ArgInfo &OrigRet,
444444 return true;
445445 }
446446
447 bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
448 const Function &F,
449 ArrayRef VRegs) const {
447 bool MipsCallLowering::lowerFormalArguments(
448 MachineIRBuilder &MIRBuilder, const Function &F,
449 ArrayRef> VRegs) const {
450450
451451 // Quick exit if there aren't any args.
452452 if (F.arg_empty())
6565 ArrayRef VRegs) const override;
6666
6767 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
68 ArrayRef<Register> VRegs) const override;
68 ArrayRef<ArrayRef> VRegs) const override;
6969
7070 bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
7171 const MachineOperand &Callee, const ArgInfo &OrigRet,
319319
320320 } // end anonymous namespace
321321
322 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
323 const Function &F,
324 ArrayRef VRegs) const {
322 bool X86CallLowering::lowerFormalArguments(
323 MachineIRBuilder &MIRBuilder, const Function &F,
324 ArrayRef> VRegs) const {
325325 if (F.arg_empty())
326326 return true;
327327
343343 Arg.hasAttribute(Attribute::StructRet) ||
344344 Arg.hasAttribute(Attribute::SwiftSelf) ||
345345 Arg.hasAttribute(Attribute::SwiftError) ||
346 Arg.hasAttribute(Attribute::Nest))
346 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
347347 return false;
348348
349349 ArgInfo OrigArg(VRegs[Idx], Arg.getType());
350350 setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
351351 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
352352 [&](ArrayRef Regs) {
353 MIRBuilder.buildMerge(VRegs[Idx], Regs);
353 MIRBuilder.buildMerge(VRegs[Idx][0], Regs);
354354 }))
355355 return false;
356356 Idx++;
3131 ArrayRef VRegs) const override;
3232
3333 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
34 ArrayRef<Register> VRegs) const override;
34 ArrayRef<ArrayRef> VRegs) const override;
3535
3636 bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
3737 const MachineOperand &Callee, const ArgInfo &OrigRet,
859859 ret void
860860 }
861861
862 ; CHECK-LABEL: name: test_trivial_extract_ptr
863 ; CHECK: [[STRUCT:%[0-9]+]]:_(p0) = COPY $x0
864 ; CHECK: [[VAL32:%[0-9]+]]:_(s32) = COPY $w1
865 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_TRUNC [[VAL32]]
866 ; CHECK: G_STORE [[VAL]](s8), [[STRUCT]](p0)
867 define void @test_trivial_extract_ptr([1 x i8*] %s, i8 %val) {
868 %addr = extractvalue [1 x i8*] %s, 0
869 store i8 %val, i8* %addr
870 ret void
871 }
872
862873 ; CHECK-LABEL: name: test_insertvalue
863874 ; CHECK: %0:_(p0) = COPY $x0
864875 ; CHECK: %1:_(s32) = COPY $w1
897908
898909 define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
899910 ; CHECK-LABEL: name: test_trivial_insert_ptr
900 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY $x0
911 ; CHECK: [[STRUCT:%[0-9]+]]:_(p0) = COPY $x0
901912 ; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY $x1
902913 ; CHECK: $x0 = COPY [[VAL]]
903914 %res = insertvalue [1 x i8*] %s, i8* %val, 0
6464 ; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
6565 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
6666
67 ; CHECK: [[UNDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
68 ; CHECK: [[ARG0:%[0-9]+]]:_(s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
69 ; CHECK: [[ARG1:%[0-9]+]]:_(s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
70 ; CHECK: [[ARG2:%[0-9]+]]:_(s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
71 ; CHECK: [[ARG:%[0-9]+]]:_(s192) = COPY [[ARG2]]
72 ; CHECK: [[EXTA0:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s192), 0
73 ; CHECK: [[EXTA1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s192), 64
74 ; CHECK: [[EXTA2:%[0-9]+]]:_(s8) = G_EXTRACT [[ARG]](s192), 128
75 ; CHECK: G_STORE [[EXTA0]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr)
67 ; CHECK: G_STORE [[DBL]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr)
7668 ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
7769 ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST1]](s64)
78 ; CHECK: G_STORE [[EXTA1]](s64), [[GEP1]](p0) :: (store 8 into %ir.addr + 8)
70 ; CHECK: G_STORE [[I64]](s64), [[GEP1]](p0) :: (store 8 into %ir.addr + 8)
7971 ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
8072 ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST2]](s64)
81 ; CHECK: G_STORE [[EXTA2]](s8), [[GEP2]](p0) :: (store 1 into %ir.addr + 16, align 8)
73 ; CHECK: G_STORE [[I8]](s8), [[GEP2]](p0) :: (store 1 into %ir.addr + 16, align 8)
8274 ; CHECK: RET_ReallyLR
8375 define void @test_struct_formal({double, i64, i8} %in, {double, i64, i8}* %addr) {
8476 store {double, i64, i8} %in, {double, i64, i8}* %addr
674674 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
675675 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64)
676676 ; HSA-VI: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 16 from `{ i32, i64 } addrspace(4)* undef`, addrspace 4)
677 ; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s128), 0
678 ; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s128), 64
677679 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
678680 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64)
679681 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 16, addrspace 4)
680682 ; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
681683 ; HSA-VI: [[GEP2:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C2]](s64)
682684 ; HSA-VI: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[GEP2]](p4) :: (non-temporal invariant load 16 from `{ i32, i64 } addrspace(4)* undef`, align 8, addrspace 4)
683 ; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s128), 0
684 ; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s128), 64
685685 ; HSA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD2]](s128), 0
686686 ; HSA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD2]](s128), 64
687687 ; HSA-VI: S_ENDPGM
706706 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
707707 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64)
708708 ; HSA-VI: [[LOAD:%[0-9]+]]:_(s96) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 12 from `<{ i32, i64 }> addrspace(4)* undef`, align 16, addrspace 4)
709 ; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s96), 0
710 ; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s96), 32
709711 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
710712 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64)
711713 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 4, addrspace 4)
712714 ; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
713715 ; HSA-VI: [[GEP2:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C2]](s64)
714716 ; HSA-VI: [[LOAD2:%[0-9]+]]:_(s96) = G_LOAD [[GEP2]](p4) :: (non-temporal invariant load 12 from `<{ i32, i64 }> addrspace(4)* undef`, align 1, addrspace 4)
715 ; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s96), 0
716 ; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s96), 32
717717 ; HSA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD2]](s96), 0
718718 ; HSA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD2]](s96), 32
719719 ; HSA-VI: S_ENDPGM
201201 ; CHECK: liveins: $r0, $r1
202202 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
203203 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
204 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
205 ; CHECK: [[EXT1:%[0-9]+]]:_(s32) = G_EXTRACT [[ARG_ARR]](s64), 0
206 ; CHECK: [[EXT2:%[0-9]+]]:_(s32) = G_EXTRACT [[ARG_ARR]](s64), 32
207204 ; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
208 ; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[EXT1]](s32), 0
209 ; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[EXT2]](s32), 32
205 ; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[R0]](s32), 0
206 ; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[R1]](s32), 32
210207 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
211208 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)
212209 ; CHECK: $r0 = COPY [[R0]]
243240 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
244241 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
245242 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
246 ; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
247 ; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
248 ; CHECK: [[EXT1:%[0-9]+]]:_(s32) = G_EXTRACT [[ARG_ARR0]](s64), 0
249 ; CHECK: [[EXT2:%[0-9]+]]:_(s32) = G_EXTRACT [[ARG_ARR0]](s64), 32
250 ; CHECK: [[EXT3:%[0-9]+]]:_(s32) = G_EXTRACT [[ARG_ARR1]](s64), 0
251 ; CHECK: [[EXT4:%[0-9]+]]:_(s32) = G_EXTRACT [[ARG_ARR1]](s64), 32
252243 ; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
253 ; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[EXT1]](s32), 0
254 ; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[EXT2]](s32), 32
244 ; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[R0]](s32), 0
245 ; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[R1]](s32), 32
255246 ; CHECK: [[IMPDEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
256 ; CHECK: [[INS3:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF2]], [[EXT3]](s32), 0
257 ; CHECK: [[INS4:%[0-9]+]]:_(s64) = G_INSERT [[INS3]], [[EXT4]](s32), 32
247 ; CHECK: [[INS3:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF2]], [[R2]](s32), 0
248 ; CHECK: [[INS4:%[0-9]+]]:_(s64) = G_INSERT [[INS3]], [[R3]](s32), 32
258249 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
259250 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)
260251 ; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS4]](s64)
290281 ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
291282 ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
292283 ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
293 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
294 ; CHECK: [[INS:%[0-9]+]]:_(s640) = G_INSERT {{.*}}, {{.*}}(s32), 608
284 ; CHECK: [[IMPDEF:%[0-9]+]]:_(s640) = G_IMPLICIT_DEF
285 ; CHECK: [[INS1:%[0-9]+]]:_(s640) = G_INSERT [[IMPDEF]], [[R0]](s32), 0
286 ; CHECK: [[INS:%[0-9]+]]:_(s640) = G_INSERT {{.*}}, [[LAST_STACK_ELEMENT]](s32), 608
295287 ; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
296288 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS]](s640)
297289 ; CHECK: $r0 = COPY [[R0]]
335327 ; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
336328 ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
337329 ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
338 ; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
339 ; CHECK: [[EXT1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARR_MERGED]](s192), 0
340 ; CHECK: [[EXT2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARR_MERGED]](s192), 64
341 ; CHECK: [[EXT3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARR_MERGED]](s192), 128
342330 ; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
343 ; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[EXT1]](s64), 0
344 ; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[EXT2]](s64), 64
345 ; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[EXT3]](s64), 128
331 ; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[ARR0]](s64), 0
332 ; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[ARR1]](s64), 64
333 ; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[ARR2]](s64), 128
346334 ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
347335 ; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS3]](s192)
348336 ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
400388 ; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
401389 ; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
402390 ; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
403 ; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
404 ; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
405 ; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
406 ; CHECK: [[EXT1:%[0-9]+]]:_(s64) = G_EXTRACT [[X_ARR]](s192), 0
407 ; CHECK: [[EXT2:%[0-9]+]]:_(s64) = G_EXTRACT [[X_ARR]](s192), 64
408 ; CHECK: [[EXT3:%[0-9]+]]:_(s64) = G_EXTRACT [[X_ARR]](s192), 128
409 ; CHECK: [[EXT4:%[0-9]+]]:_(s32) = G_EXTRACT [[Y_ARR]](s96), 0
410 ; CHECK: [[EXT5:%[0-9]+]]:_(s32) = G_EXTRACT [[Y_ARR]](s96), 32
411 ; CHECK: [[EXT6:%[0-9]+]]:_(s32) = G_EXTRACT [[Y_ARR]](s96), 64
412 ; CHECK: [[EXT7:%[0-9]+]]:_(s64) = G_EXTRACT [[Z_ARR]](s256), 0
413 ; CHECK: [[EXT8:%[0-9]+]]:_(s64) = G_EXTRACT [[Z_ARR]](s256), 64
414 ; CHECK: [[EXT9:%[0-9]+]]:_(s64) = G_EXTRACT [[Z_ARR]](s256), 128
415 ; CHECK: [[EXT10:%[0-9]+]]:_(s64) = G_EXTRACT [[Z_ARR]](s256), 192
416391 ; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
417 ; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[EXT1]](s64), 0
418 ; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[EXT2]](s64), 64
419 ; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[EXT3]](s64), 128
392 ; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[X0]](s64), 0
393 ; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[X1]](s64), 64
394 ; CHECK: [[INS3:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[X2]](s64), 128
420395 ; CHECK: [[IMPDEF2:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
421 ; CHECK: [[INS4:%[0-9]+]]:_(s96) = G_INSERT [[IMPDEF2]], [[EXT4]](s32), 0
422 ; CHECK: [[INS5:%[0-9]+]]:_(s96) = G_INSERT [[INS4]], [[EXT5]](s32), 32
423 ; CHECK: [[INS6:%[0-9]+]]:_(s96) = G_INSERT [[INS5]], [[EXT6]](s32), 64
396 ; CHECK: [[INS4:%[0-9]+]]:_(s96) = G_INSERT [[IMPDEF2]], [[Y0]](s32), 0
397 ; CHECK: [[INS5:%[0-9]+]]:_(s96) = G_INSERT [[INS4]], [[Y1]](s32), 32
398 ; CHECK: [[INS6:%[0-9]+]]:_(s96) = G_INSERT [[INS5]], [[Y2]](s32), 64
424399 ; CHECK: [[IMPDEF3:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
425 ; CHECK: [[INS7:%[0-9]+]]:_(s256) = G_INSERT [[IMPDEF3]], [[EXT7]](s64), 0
426 ; CHECK: [[INS8:%[0-9]+]]:_(s256) = G_INSERT [[INS7]], [[EXT8]](s64), 64
427 ; CHECK: [[INS9:%[0-9]+]]:_(s256) = G_INSERT [[INS8]], [[EXT9]](s64), 128
428 ; CHECK: [[INS10:%[0-9]+]]:_(s256) = G_INSERT [[INS9]], [[EXT10]](s64), 192
400 ; CHECK: [[INS7:%[0-9]+]]:_(s256) = G_INSERT [[IMPDEF3]], [[Z0]](s64), 0
401 ; CHECK: [[INS8:%[0-9]+]]:_(s256) = G_INSERT [[INS7]], [[Z1]](s64), 64
402 ; CHECK: [[INS9:%[0-9]+]]:_(s256) = G_INSERT [[INS8]], [[Z2]](s64), 128
403 ; CHECK: [[INS10:%[0-9]+]]:_(s256) = G_INSERT [[INS9]], [[Z3]](s64), 192
429404 ; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
430405 ; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[INS3]](s192)
431406 ; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS6]](s96)
493468 ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
494469 ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
495470 ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
496 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
497 ; CHECK: [[INS:%[0-9]+]]:_(s768) = G_INSERT {{.*}}, {{.*}}(s32), 736
471 ; CHECK: [[INS:%[0-9]+]]:_(s768) = G_INSERT {{.*}}, [[LAST_STACK_ELEMENT]](s32), 736
498472 ; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
499473 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS]](s768)
500474 ; CHECK: $r0 = COPY [[R0]]
535509 ; CHECK: liveins: $r0, $r1
536510 ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
537511 ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
538 ; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
539 ; CHECK: [[EXT1:%[0-9]+]]:_(s32) = G_EXTRACT [[X]](s64), 0
540 ; CHECK: [[EXT2:%[0-9]+]]:_(s32) = G_EXTRACT [[X]](s64), 32
541512 ; CHECK: [[IMPDEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
542 ; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[EXT1]](s32), 0
543 ; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[EXT2]](s32), 32
513 ; CHECK: [[INS1:%[0-9]+]]:_(s64) = G_INSERT [[IMPDEF]], [[X0]](s32), 0
514 ; CHECK: [[INS2:%[0-9]+]]:_(s64) = G_INSERT [[INS1]], [[X1]](s32), 32
544515 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
545516 ; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INS2]](s64)
546517 ; CHECK-DAG: $r0 = COPY [[X0]](s32)