llvm.org GIT mirror llvm / 471e422
Add a parameter to CCState so that it can access the MachineFunction. No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 9 years ago
21 changed file(s) with 204 addition(s) and 187 deletion(s). Raw diff Collapse all Expand all
1515 #define LLVM_CODEGEN_CALLINGCONVLOWER_H
1616
1717 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/MachineFunction.h"
1819 #include "llvm/CodeGen/ValueTypes.h"
1920 #include "llvm/Target/TargetCallingConv.h"
2021 #include "llvm/CallingConv.h"
148149 class CCState {
149150 CallingConv::ID CallingConv;
150151 bool IsVarArg;
152 MachineFunction &MF;
151153 const TargetMachine &TM;
152154 const TargetRegisterInfo &TRI;
153155 SmallVector &Locs;
159161 bool FirstByValRegValid;
160162 ParmContext CallOrPrologue;
161163 public:
162 CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
164 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
165 const TargetMachine &TM,
163166 SmallVector &locs, LLVMContext &C);
164167
165168 void addLoc(const CCValAssign &V) {
168171
169172 LLVMContext &getContext() const { return Context; }
170173 const TargetMachine &getTarget() const { return TM; }
174 MachineFunction &getMachineFunction() const { return MF; }
171175 CallingConv::ID getCallingConv() const { return CallingConv; }
172176 bool isVarArg() const { return IsVarArg; }
173177
253253 /// to get to the smaller register. For illegal floating point types, this
254254 /// returns the integer type to transform to.
255255 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
256 return getTypeConversion(Context, VT).second;
256 return getTypeConversion(Context, VT).second;
257257 }
258258
259259 /// getTypeToExpandTo - For types supported by the target, this is an
12101210 /// return values described by the Outs array can fit into the return
12111211 /// registers. If false is returned, an sret-demotion is performed.
12121212 ///
1213 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1213 virtual bool CanLowerReturn(CallingConv::ID CallConv,
1214 MachineFunction &MF, bool isVarArg,
12141215 const SmallVectorImpl &Outs,
12151216 LLVMContext &Context) const
12161217 {
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "llvm/CodeGen/CallingConvLower.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
1516 #include "llvm/Support/Debug.h"
1617 #include "llvm/Support/ErrorHandling.h"
1718 #include "llvm/Support/raw_ostream.h"
2122 #include "llvm/Target/TargetLowering.h"
2223 using namespace llvm;
2324
24 CCState::CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm,
25 CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf,
26 const TargetMachine &tm,
2527 SmallVector &locs, LLVMContext &C)
26 : CallingConv(CC), IsVarArg(isVarArg), TM(tm),
28 : CallingConv(CC), IsVarArg(isVarArg), MF(mf), TM(tm),
2729 TRI(*TM.getRegisterInfo()), Locs(locs), Context(C),
2830 CallOrPrologue(Invalid) {
2931 // No stack is used.
3032 StackOffset = 0;
31
33
3234 clearFirstByValReg();
3335 UsedRegs.resize((TRI.getNumRegs()+31)/32);
3436 }
3537
36 // HandleByVal - Allocate a stack slot large enough to pass an argument by
37 // value. The size and alignment information of the argument is encoded in its
38 // parameter attribute.
38 // HandleByVal - Allocate space on the stack large enough to pass an argument
39 // by value. The size and alignment information of the argument is encoded in
40 // its parameter attribute.
3941 void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
4042 MVT LocVT, CCValAssign::LocInfo LocInfo,
4143 int MinSize, int MinAlign,
6666 SmallVector Outs;
6767 GetReturnInfo(Fn->getReturnType(),
6868 Fn->getAttributes().getRetAttributes(), Outs, TLI);
69 CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), Fn->isVarArg(),
69 CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), *MF,
70 Fn->isVarArg(),
7071 Outs, Fn->getContext());
7172
7273 // Initialize the mapping of values to registers. This is only set up for
320321 APInt Zero(BitWidth, 0);
321322 DestLOI.KnownZero = Zero;
322323 DestLOI.KnownOne = Zero;
323 return;
324 return;
324325 }
325326
326327 if (ConstantInt *CI = dyn_cast(V)) {
352353 /// setByValArgumentFrameIndex - Record frame index for the byval
353354 /// argument. This overrides previous frame index entry for this argument,
354355 /// if any.
355 void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A,
356 void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A,
356357 int FI) {
357358 assert (A->hasByValAttr() && "Argument does not have byval attribute!");
358359 ByValArgFrameIndexMap[A] = FI;
359360 }
360
361
361362 /// getByValArgumentFrameIndex - Get frame index for the byval argument.
362363 /// If the argument does not have any assigned frame index then 0 is
363364 /// returned.
364365 int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) {
365366 assert (A->hasByValAttr() && "Argument does not have byval attribute!");
366 DenseMap::iterator I =
367 DenseMap::iterator I =
367368 ByValArgFrameIndexMap.find(A);
368369 if (I != ByValArgFrameIndexMap.end())
369370 return I->second;
302302 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT,
303303 &NewOps[0], NewOps.size());
304304 }
305
305
306306 // Trivial bitcast if the types are the same size and the destination
307307 // vector type is legal.
308308 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
48834883 Outs, TLI, &Offsets);
48844884
48854885 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4886 FTy->isVarArg(), Outs, FTy->getContext());
4886 DAG.getMachineFunction(),
4887 FTy->isVarArg(), Outs,
4888 FTy->getContext());
48874889
48884890 SDValue DemoteStackSlot;
48894891 int DemoteStackIdx = -100;
57765778 // the addressing mode that the constraint wants. Also, this may take
57775779 // an additional register for the computation and we don't want that
57785780 // either.
5779
5781
57805782 // If the operand is a float, integer, or vector constant, spill to a
57815783 // constant pool entry to get its address.
57825784 const Value *OpVal = OpInfo.CallOperandVal;
442442 uint64_t Imm1, uint64_t Imm2) {
443443 unsigned ResultReg = createResultReg(RC);
444444 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
445
445
446446 if (II.getNumDefs() >= 1)
447447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
448448 .addImm(Imm1).addImm(Imm2));
449449 else {
450450 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
451451 .addImm(Imm1).addImm(Imm2));
452 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
452 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
453453 TII.get(TargetOpcode::COPY),
454454 ResultReg)
455455 .addReg(II.ImplicitDefs[0]));
15411541 CallingConv::ID CC,
15421542 unsigned &NumBytes) {
15431543 SmallVector ArgLocs;
1544 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1544 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
15451545 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
15461546
15471547 // Get a count of how many bytes are to be pushed on the stack.
16541654 // Now the return value.
16551655 if (RetVT != MVT::isVoid) {
16561656 SmallVector RVLocs;
1657 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1657 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
16581658 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
16591659
16601660 // Copy all of the result registers out of their specified physreg.
17101710
17111711 // Analyze operands of the call, assigning locations to each operand.
17121712 SmallVector ValLocs;
1713 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
1713 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, I->getContext());
17141714 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
17151715
17161716 const Value *RV = Ret->getOperand(0);
19891989 // any code.
19901990 UpdateValueMap(I, SrcReg);
19911991 return true;
1992 }
1992 }
19931993 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
19941994 return false;
19951995
10701070
10711071 // Assign locations to each value returned by this call.
10721072 SmallVector RVLocs;
1073 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1074 RVLocs, *DAG.getContext());
1073 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1074 getTargetMachine(), RVLocs, *DAG.getContext());
10751075 CCInfo.AnalyzeCallResult(Ins,
10761076 CCAssignFnForNode(CallConv, /* Return*/ true,
10771077 isVarArg));
12051205
12061206 // Analyze operands of the call, assigning locations to each operand.
12071207 SmallVector ArgLocs;
1208 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1209 *DAG.getContext());
1208 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1209 getTargetMachine(), ArgLocs, *DAG.getContext());
12101210 CCInfo.setCallOrPrologue(Call);
12111211 CCInfo.AnalyzeCallOperands(Outs,
12121212 CCAssignFnForNode(CallConv, /* Return*/ false,
16371637 // results are returned in the same way as what the caller expects.
16381638 if (!CCMatch) {
16391639 SmallVector RVLocs1;
1640 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1641 RVLocs1, *DAG.getContext());
1640 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1641 getTargetMachine(), RVLocs1, *DAG.getContext());
16421642 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
16431643
16441644 SmallVector RVLocs2;
1645 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1646 RVLocs2, *DAG.getContext());
1645 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1646 getTargetMachine(), RVLocs2, *DAG.getContext());
16471647 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
16481648
16491649 if (RVLocs1.size() != RVLocs2.size())
16691669 // Check if stack adjustment is needed. For now, do not do this if any
16701670 // argument is passed on the stack.
16711671 SmallVector ArgLocs;
1672 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1673 ArgLocs, *DAG.getContext());
1672 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1673 getTargetMachine(), ArgLocs, *DAG.getContext());
16741674 CCInfo.AnalyzeCallOperands(Outs,
16751675 CCAssignFnForNode(CalleeCC, false, isVarArg));
16761676 if (CCInfo.getNextStackOffset()) {
17291729 SmallVector RVLocs;
17301730
17311731 // CCState - Info about the registers and stack slots.
1732 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1733 *DAG.getContext());
1732 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1733 getTargetMachine(), RVLocs, *DAG.getContext());
17341734
17351735 // Analyze outgoing return values.
17361736 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
24232423
24242424 // Assign locations to all of the incoming arguments.
24252425 SmallVector ArgLocs;
2426 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2427 *DAG.getContext());
2426 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2427 getTargetMachine(), ArgLocs, *DAG.getContext());
24282428 CCInfo.setCallOrPrologue(Prologue);
24292429 CCInfo.AnalyzeFormalArguments(Ins,
24302430 CCAssignFnForNode(CallConv, /* Return*/ false,
25232523 if (index != lastInsIndex)
25242524 {
25252525 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2526 // FIXME: For now, all byval parameter objects are marked mutable.
2526 // FIXME: For now, all byval parameter objects are marked mutable.
25272527 // This can be changed with more analysis.
25282528 // In case of tail call optimization mark all arguments mutable.
25292529 // Since they could be overwritten by lowering of arguments in case of
73857385
73867386 // Currently only support length 1 constraints.
73877387 if (Constraint.length() != 1) return;
7388
7388
73897389 char ConstraintLetter = Constraint[0];
73907390 switch (ConstraintLetter) {
73917391 default: break;
229229
230230 // Analyze operands of the call, assigning locations to each operand.
231231 SmallVector ArgLocs;
232 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
233 ArgLocs, *DAG.getContext());
232 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
233 getTargetMachine(), ArgLocs, *DAG.getContext());
234234
235235 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
236236
343343
344344 // Assign locations to each value returned by this call.
345345 SmallVector RVLocs;
346 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
347 *DAG.getContext());
346 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
347 getTargetMachine(), RVLocs, *DAG.getContext());
348348
349349 CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha);
350350
170170 MachineFrameInfo *MFI = MF.getFrameInfo();
171171
172172 SmallVector ArgLocs;
173 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
174 ArgLocs, *DAG.getContext());
173 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
174 getTargetMachine(), ArgLocs, *DAG.getContext());
175175 CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
176176 CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
177177
228228 SmallVector RVLocs;
229229
230230 // CCState - Info about the registers and stack slot.
231 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
232 RVLocs, *DAG.getContext());
231 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
232 DAG.getTarget(), RVLocs, *DAG.getContext());
233233
234234 // Analize return values.
235235 CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
289289
290290 // Analyze operands of the call, assigning locations to each operand.
291291 SmallVector ArgLocs;
292 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
293 *DAG.getContext());
292 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
293 DAG.getTarget(), ArgLocs, *DAG.getContext());
294294 CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
295295 CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
296296
377377
378378 // Assign locations to each value returned by this call.
379379 SmallVector RVLocs;
380 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
381 *DAG.getContext());
380 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
381 DAG.getTarget(), RVLocs, *DAG.getContext());
382382
383383 RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
384384
11161116 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
11171117
11181118 SmallVector ArgLocs;
1119 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1120 *DAG.getContext());
1119 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1120 getTargetMachine(), ArgLocs, *DAG.getContext());
11211121 // FIXME: allow for other calling conventions
11221122 CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
11231123
12631263 unsigned StackSlotSize = SPUFrameLowering::stackSlotSize();
12641264
12651265 SmallVector ArgLocs;
1266 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1267 *DAG.getContext());
1266 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1267 getTargetMachine(), ArgLocs, *DAG.getContext());
12681268 // FIXME: allow for other calling conventions
12691269 CCInfo.AnalyzeCallOperands(Outs, CCC_SPU);
12701270
14241424
14251425 // Now handle the return value(s)
14261426 SmallVector RVLocs;
1427 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
1428 RVLocs, *DAG.getContext());
1427 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1428 getTargetMachine(), RVLocs, *DAG.getContext());
14291429 CCRetInfo.AnalyzeCallResult(Ins, CCC_SPU);
14301430
14311431
14511451 DebugLoc dl, SelectionDAG &DAG) const {
14521452
14531453 SmallVector RVLocs;
1454 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1455 RVLocs, *DAG.getContext());
1454 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1455 getTargetMachine(), RVLocs, *DAG.getContext());
14561456 CCInfo.AnalyzeReturn(Outs, RetCC_SPU);
14571457
14581458 // If this is the first return lowered for this function, add the regs to the
416416 // All atomic instructions on the Microblaze are implemented using the
417417 // load-linked / store-conditional style atomic instruction sequences.
418418 // Thus, all operations will look something like the following:
419 //
419 //
420420 // start:
421421 // lwx RV, RP, 0
422422 //
697697
698698 // Analyze operands of the call, assigning locations to each operand.
699699 SmallVector ArgLocs;
700 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
701 *DAG.getContext());
700 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
701 getTargetMachine(), ArgLocs, *DAG.getContext());
702702 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
703703
704704 // Get a count of how many bytes are to be pushed on the stack.
836836 SmallVectorImpl &InVals) const {
837837 // Assign locations to each value returned by this call.
838838 SmallVector RVLocs;
839 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
840 RVLocs, *DAG.getContext());
839 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
840 getTargetMachine(), RVLocs, *DAG.getContext());
841841
842842 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
843843
879879
880880 // Assign locations to all of the incoming arguments.
881881 SmallVector ArgLocs;
882 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
883 ArgLocs, *DAG.getContext());
882 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
883 getTargetMachine(), ArgLocs, *DAG.getContext());
884884
885885 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze);
886886 SDValue StackPtr;
10111011 SmallVector RVLocs;
10121012
10131013 // CCState - Info about the registers and stack slot.
1014 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1015 RVLocs, *DAG.getContext());
1014 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1015 getTargetMachine(), RVLocs, *DAG.getContext());
10161016
10171017 // Analize return values.
10181018 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
10421042
10431043 // If this function is using the interrupt_handler calling convention
10441044 // then use "rtid r14, 0" otherwise use "rtsd r15, 8"
1045 unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet
1045 unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet
10461046 : MBlazeISD::Ret;
1047 unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14
1047 unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14
10481048 : MBlaze::R15;
10491049 SDValue DReg = DAG.getRegister(Reg, MVT::i32);
10501050
311311
312312 // Assign locations to all of the incoming arguments.
313313 SmallVector ArgLocs;
314 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
315 ArgLocs, *DAG.getContext());
314 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
315 getTargetMachine(), ArgLocs, *DAG.getContext());
316316 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
317317
318318 assert(!isVarArg && "Varargs not supported yet");
394394 }
395395
396396 // CCState - Info about the registers and stack slot.
397 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
398 RVLocs, *DAG.getContext());
397 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
398 getTargetMachine(), RVLocs, *DAG.getContext());
399399
400400 // Analize return values.
401401 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
448448 SmallVectorImpl &InVals) const {
449449 // Analyze operands of the call, assigning locations to each operand.
450450 SmallVector ArgLocs;
451 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
452 ArgLocs, *DAG.getContext());
451 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
452 getTargetMachine(), ArgLocs, *DAG.getContext());
453453
454454 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
455455
571571
572572 // Assign locations to each value returned by this call.
573573 SmallVector RVLocs;
574 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
575 RVLocs, *DAG.getContext());
574 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
575 getTargetMachine(), RVLocs, *DAG.getContext());
576576
577577 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
578578
147147
148148 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
149149 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
150
150
151151 setOperationAction(ISD::VAARG, MVT::Other, Expand);
152152 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
153153 setOperationAction(ISD::VAEND, MVT::Other, Expand);
719719 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
720720 MachineBasicBlock *
721721 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
722 unsigned Size, unsigned BinOpcode,
722 unsigned Size, unsigned BinOpcode,
723723 bool Nand) const {
724724 assert(Size == 4 && "Unsupported size for EmitAtomicBinary.");
725725
15011501 }
15021502
15031503 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
1504 // FIXME:
1504 // FIXME:
15051505 // Use ext/ins instructions if target architecture is Mips32r2.
15061506 // Eliminate redundant mfc1 and mtc1 instructions.
15071507 unsigned LoIdx = 0, HiIdx = 1;
1508
1508
15091509 if (!isLittle)
15101510 std::swap(LoIdx, HiIdx);
15111511
17061706
17071707 // copy remaining part of byval arg to stack.
17081708 if (CurWord < LastWord) {
1709 unsigned SizeInBytes = (LastWord - CurWord) * 4;
1709 unsigned SizeInBytes = (LastWord - CurWord) * 4;
17101710 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
17111711 DAG.getConstant((CurWord - FirstWord) * 4,
17121712 MVT::i32));
17441744
17451745 // Analyze operands of the call, assigning locations to each operand.
17461746 SmallVector ArgLocs;
1747 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1748 *DAG.getContext());
1747 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1748 getTargetMachine(), ArgLocs, *DAG.getContext());
17491749
17501750 if (Subtarget->isABI_O32())
17511751 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
17661766 // Get the frame index of the stack frame object that points to the location
17671767 // of dynamically allocated area on the stack.
17681768 int DynAllocFI = MipsFI->getDynAllocFI();
1769
1769
17701770 // Update size of the maximum argument space.
17711771 // For O32, a minimum of four words (16 bytes) of argument space is
17721772 // allocated.
17801780
17811781 // Set the offsets relative to $sp of the $gp restore slot and dynamically
17821782 // allocated stack space. These offsets must be aligned to a boundary
1783 // determined by the stack alignment of the ABI.
1783 // determined by the stack alignment of the ABI.
17841784 unsigned StackAlignment = TFL->getStackAlignment();
1785 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
1785 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
17861786 StackAlignment * StackAlignment;
17871787
17881788 if (IsPIC)
17891789 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
1790
1790
17911791 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
17921792 }
17931793
17951795 SmallVector, 16> RegsToPass;
17961796 SmallVector MemOpChains;
17971797
1798 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
1798 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
17991799
18001800 // Walk the register/memloc assignments, inserting copies/loads.
18011801 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
18431843 // Register can't get to this point...
18441844 assert(VA.isMemLoc());
18451845
1846 // ByVal Arg.
1846 // ByVal Arg.
18471847 ISD::ArgFlagsTy Flags = Outs[i].Flags;
18481848 if (Flags.isByVal()) {
18491849 assert(Subtarget->isABI_O32() &&
18561856 }
18571857
18581858 // Create the frame index object for this incoming parameter
1859 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1859 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
18601860 VA.getLocMemOffset(), true);
18611861 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
18621862
19231923 } else
19241924 Callee = LoadValue;
19251925
1926 // Use chain output from LoadValue
1926 // Use chain output from LoadValue
19271927 Chain = LoadValue.getValue(1);
19281928 }
19291929
19851985 SmallVectorImpl &InVals) const {
19861986 // Assign locations to each value returned by this call.
19871987 SmallVector RVLocs;
1988 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1989 RVLocs, *DAG.getContext());
1988 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1989 getTargetMachine(), RVLocs, *DAG.getContext());
19901990
19911991 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
19921992
20502050
20512051 // Assign locations to all of the incoming arguments.
20522052 SmallVector ArgLocs;
2053 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2054 ArgLocs, *DAG.getContext());
2053 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2054 getTargetMachine(), ArgLocs, *DAG.getContext());
20552055
20562056 if (Subtarget->isABI_O32())
20572057 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
21642164
21652165 if (isVarArg && Subtarget->isABI_O32()) {
21662166 // Record the frame index of the first variable argument
2167 // which is a value necessary to VASTART.
2167 // which is a value necessary to VASTART.
21682168 unsigned NextStackOffset = CCInfo.getNextStackOffset();
21692169 assert(NextStackOffset % 4 == 0 &&
21702170 "NextStackOffset must be aligned to 4-byte boundaries.");
22162216 SmallVector RVLocs;
22172217
22182218 // CCState - Info about the registers and stack slot.
2219 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2220 RVLocs, *DAG.getContext());
2219 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2220 getTargetMachine(), RVLocs, *DAG.getContext());
22212221
22222222 // Analize return values.
22232223 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
15571557
15581558 // Assign locations to all of the incoming arguments.
15591559 SmallVector ArgLocs;
1560 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1561 *DAG.getContext());
1560 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1561 getTargetMachine(), ArgLocs, *DAG.getContext());
15621562
15631563 // Reserve space for the linkage area on the stack.
15641564 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
16181618 // Aggregates passed by value are stored in the local variable space of the
16191619 // caller's stack frame, right above the parameter list area.
16201620 SmallVector ByValArgLocs;
1621 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1622 ByValArgLocs, *DAG.getContext());
1621 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1622 getTargetMachine(), ByValArgLocs, *DAG.getContext());
16231623
16241624 // Reserve stack space for the allocations in CCInfo.
16251625 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
25902590 SmallVectorImpl &InVals) const {
25912591
25922592 SmallVector RVLocs;
2593 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2594 RVLocs, *DAG.getContext());
2593 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2594 getTargetMachine(), RVLocs, *DAG.getContext());
25952595 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
25962596
25972597 // Copy all of the result registers out of their specified physreg.
26402640 // to the liveout set for the function.
26412641 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
26422642 SmallVector RVLocs;
2643 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2644 *DAG.getContext());
2643 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2644 getTargetMachine(), RVLocs, *DAG.getContext());
26452645 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
26462646 for (unsigned i = 0; i != RVLocs.size(); ++i)
26472647 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
27542754
27552755 // Assign locations to all of the outgoing arguments.
27562756 SmallVector ArgLocs;
2757 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2758 ArgLocs, *DAG.getContext());
2757 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2758 getTargetMachine(), ArgLocs, *DAG.getContext());
27592759
27602760 // Reserve space for the linkage area on the stack.
27612761 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
27942794
27952795 // Assign locations to all of the outgoing aggregate by value arguments.
27962796 SmallVector ByValArgLocs;
2797 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2798 *DAG.getContext());
2797 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2798 getTargetMachine(), ByValArgLocs, *DAG.getContext());
27992799
28002800 // Reserve stack space for the allocations in CCInfo.
28012801 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
33023302 DebugLoc dl, SelectionDAG &DAG) const {
33033303
33043304 SmallVector RVLocs;
3305 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3306 RVLocs, *DAG.getContext());
3305 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3306 getTargetMachine(), RVLocs, *DAG.getContext());
33073307 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
33083308
33093309 // If this is the first return lowered for this function, add the regs to the
54385438
54395439 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
54405440 /// vector. If it is invalid, don't add anything to Ops.
5441 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5441 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
54425442 std::string &Constraint,
54435443 std::vector&Ops,
54445444 SelectionDAG &DAG) const {
54455445 SDValue Result(0,0);
5446
5446
54475447 // Only support length 1 constraints.
54485448 if (Constraint.length() > 1) return;
5449
5449
54505450 char Letter = Constraint[0];
54515451 switch (Letter) {
54525452 default: break;
9090 SmallVector RVLocs;
9191
9292 // CCState - Info about the registers and stack slot.
93 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
94 RVLocs, *DAG.getContext());
93 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
94 DAG.getTarget(), RVLocs, *DAG.getContext());
9595
9696 // Analize return values.
9797 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
138138 if (Flag.getNode())
139139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
140140 RetAddrOffsetNode, Flag);
141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
142142 RetAddrOffsetNode);
143143 }
144144
160160
161161 // Assign locations to all of the incoming arguments.
162162 SmallVector ArgLocs;
163 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
164 ArgLocs, *DAG.getContext());
163 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
164 getTargetMachine(), ArgLocs, *DAG.getContext());
165165 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
166166
167167 const unsigned StackOffset = 92;
359359
360360 // Analyze operands of the call, assigning locations to each operand.
361361 SmallVector ArgLocs;
362 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
363 *DAG.getContext());
362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
363 DAG.getTarget(), ArgLocs, *DAG.getContext());
364364 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
365365
366366 // Get the size of the outgoing arguments stack space requirement.
590590
591591 // Assign locations to each value returned by this call.
592592 SmallVector RVLocs;
593 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(),
594 RVLocs, *DAG.getContext());
593 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
594 DAG.getTarget(), RVLocs, *DAG.getContext());
595595
596596 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
597597
290290
291291 // Assign locations to all of the incoming arguments.
292292 SmallVector ArgLocs;
293 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
294 ArgLocs, *DAG.getContext());
293 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
294 getTargetMachine(), ArgLocs, *DAG.getContext());
295295 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
296296
297297 if (isVarArg)
383383
384384 // Analyze operands of the call, assigning locations to each operand.
385385 SmallVector ArgLocs;
386 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
387 ArgLocs, *DAG.getContext());
386 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
387 getTargetMachine(), ArgLocs, *DAG.getContext());
388388
389389 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
390390
512512
513513 // Assign locations to each value returned by this call.
514514 SmallVector RVLocs;
515 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
516 *DAG.getContext());
515 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
516 getTargetMachine(), RVLocs, *DAG.getContext());
517517
518518 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
519519
557557 SmallVector RVLocs;
558558
559559 // CCState - Info about the registers and stack slot.
560 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
561 RVLocs, *DAG.getContext());
560 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
561 getTargetMachine(), RVLocs, *DAG.getContext());
562562
563563 // Analize return values.
564564 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
400400 Disp += SL->getElementOffset(cast(Op)->getZExtValue());
401401 continue;
402402 }
403
403
404404 // A array/variable index is always of the form i*S where S is the
405405 // constant scale size. See if we can push the scale into immediates.
406406 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
468468 if (const GlobalVariable *GVar = dyn_cast(GV))
469469 if (GVar->isThreadLocal())
470470 return false;
471
471
472472 // RIP-relative addresses can't have additional register operands, so if
473473 // we've already folded stuff into the addressing mode, just force the
474474 // global value into its own register, which we can use as the basereg.
703703
704704 // Analyze operands of the call, assigning locations to each operand.
705705 SmallVector ValLocs;
706 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
706 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
707 I->getContext());
707708 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
708709
709710 const Value *RV = Ret->getOperand(0);
935936
936937 bool X86FastISel::X86SelectZExt(const Instruction *I) {
937938 // Handle zero-extension from i1 to i8, which is common.
938 if (!I->getOperand(0)->getType()->isIntegerTy(1))
939 if (!I->getOperand(0)->getType()->isIntegerTy(1))
939940 return false;
940941
941942 EVT DstVT = TLI.getValueType(I->getType());
10611062 if (OpReg == 0) return false;
10621063 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc))
10631064 .addReg(OpReg).addImm(1);
1064
1065
10651066 unsigned JmpOpc = X86::JNE_4;
10661067 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
10671068 std::swap(TrueMBB, FalseMBB);
10681069 JmpOpc = X86::JE_4;
10691070 }
1070
1071
10711072 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc))
10721073 .addMBB(TrueMBB);
10731074 FastEmitBranch(FalseMBB, DL);
13351336 return false;
13361337
13371338 uint64_t Len = cast(MCI.getLength())->getZExtValue();
1338
1339
13391340 // Get the address of the dest and source addresses.
13401341 X86AddressMode DestAM, SrcAM;
13411342 if (!X86SelectAddress(MCI.getRawDest(), DestAM) ||
13441345
13451346 return TryEmitSmallMemcpy(DestAM, SrcAM, Len);
13461347 }
1347
1348
13481349 case Intrinsic::stackprotector: {
13491350 // Emit code inline code to store the stack guard onto the stack.
13501351 EVT PtrTy = TLI.getPointerTy();
13781379 case Intrinsic::sadd_with_overflow:
13791380 case Intrinsic::uadd_with_overflow: {
13801381 // FIXME: Should fold immediates.
1381
1382
13821383 // Replace "add with overflow" intrinsics with an "add" instruction followed
13831384 // by a seto/setc instruction.
13841385 const Function *Callee = I.getCalledFunction();
14661467 GetReturnInfo(I->getType(), CS.getAttributes().getRetAttributes(),
14671468 Outs, TLI, &Offsets);
14681469 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
1469 FTy->isVarArg(), Outs, FTy->getContext());
1470 *FuncInfo.MF, FTy->isVarArg(),
1471 Outs, FTy->getContext());
14701472 if (!CanLowerReturn)
14711473 return false;
14721474
15341536 ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext()));
15351537 }
15361538 }
1537
1539
15381540 unsigned ArgReg;
1539
1541
15401542 // Passing bools around ends up doing a trunc to i1 and passing it.
15411543 // Codegen this as an argument + "and 1".
15421544 if (ArgVal->getType()->isIntegerTy(1) && isa(ArgVal) &&
15451547 ArgVal = cast(ArgVal)->getOperand(0);
15461548 ArgReg = getRegForValue(ArgVal);
15471549 if (ArgReg == 0) return false;
1548
1550
15491551 MVT ArgVT;
15501552 if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false;
1551
1553
15521554 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg,
15531555 ArgVal->hasOneUse(), 1);
15541556 } else {
15741576
15751577 // Analyze operands of the call, assigning locations to each operand.
15761578 SmallVector ArgLocs;
1577 CCState CCInfo(CC, isVarArg, TM, ArgLocs, I->getParent()->getContext());
1579 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs,
1580 I->getParent()->getContext());
15781581
15791582 // Allocate shadow area for Win64
15801583 if (Subtarget->isTargetWin64())
17891792 // Now handle call return values.
17901793 SmallVector UsedRegs;
17911794 SmallVector RVLocs;
1792 CCState CCRetInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1795 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs,
1796 I->getParent()->getContext());
17931797 unsigned ResultReg = FuncInfo.CreateRegs(I->getType());
17941798 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
17951799 for (unsigned i = 0; i != RVLocs.size(); ++i) {
19451949 if (AM.BaseType == X86AddressMode::RegBase &&
19461950 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0)
19471951 return AM.Base.Reg;
1948
1952
19491953 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
19501954 unsigned ResultReg = createResultReg(RC);
19511955 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
221221
222222 // X86 is weird, it always uses i8 for shift amounts and setcc results.
223223 setBooleanContents(ZeroOrOneBooleanContent);
224
224
225225 // For 64-bit since we have so many registers use the ILP scheduler, for
226226 // 32-bit code use the register pressure specific scheduling.
227227 if (Subtarget->is64Bit())
13191319 #include "X86GenCallingConv.inc"
13201320
13211321 bool
1322 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1322 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1323 MachineFunction &MF, bool isVarArg,
13231324 const SmallVectorImpl &Outs,
13241325 LLVMContext &Context) const {
13251326 SmallVector RVLocs;
1326 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1327 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
13271328 RVLocs, Context);
13281329 return CCInfo.CheckReturn(Outs, RetCC_X86);
13291330 }
13381339 X86MachineFunctionInfo *FuncInfo = MF.getInfo();
13391340
13401341 SmallVector RVLocs;
1341 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1342 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
13421343 RVLocs, *DAG.getContext());
13431344 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
13441345
14891490 // Assign locations to each value returned by this call.
14901491 SmallVector RVLocs;
14911492 bool Is64Bit = Subtarget->is64Bit();
1492 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1493 RVLocs, *DAG.getContext());
1493 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1494 getTargetMachine(), RVLocs, *DAG.getContext());
14941495 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
14951496
14961497 // Copy all of the result registers out of their specified physreg.
16791680
16801681 // Assign locations to all of the incoming arguments.
16811682 SmallVector ArgLocs;
1682 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1683 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
16831684 ArgLocs, *DAG.getContext());
16841685
16851686 // Allocate shadow area for Win64
20062007
20072008 // Analyze operands of the call, assigning locations to each operand.
20082009 SmallVector ArgLocs;
2009 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2010 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
20102011 ArgLocs, *DAG.getContext());
20112012
20122013 // Allocate shadow area for Win64
25442545 return false;
25452546
25462547 SmallVector ArgLocs;
2547 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2548 ArgLocs, *DAG.getContext());
2548 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2549 getTargetMachine(), ArgLocs, *DAG.getContext());
25492550
25502551 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
25512552 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
25652566 }
25662567 if (Unused) {
25672568 SmallVector RVLocs;
2568 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2569 RVLocs, *DAG.getContext());
2569 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2570 getTargetMachine(), RVLocs, *DAG.getContext());
25702571 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
25712572 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
25722573 CCValAssign &VA = RVLocs[i];
25792580 // results are returned in the same way as what the caller expects.
25802581 if (!CCMatch) {
25812582 SmallVector RVLocs1;
2582 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2583 RVLocs1, *DAG.getContext());
2583 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2584 getTargetMachine(), RVLocs1, *DAG.getContext());
25842585 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
25852586
25862587 SmallVector RVLocs2;
2587 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2588 RVLocs2, *DAG.getContext());
2588 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2589 getTargetMachine(), RVLocs2, *DAG.getContext());
25892590 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
25902591
25912592 if (RVLocs1.size() != RVLocs2.size())
26112612 // Check if stack adjustment is needed. For now, do not do this if any
26122613 // argument is passed on the stack.
26132614 SmallVector ArgLocs;
2614 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2615 ArgLocs, *DAG.getContext());
2615 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2616 getTargetMachine(), ArgLocs, *DAG.getContext());
26162617
26172618 // Allocate shadow area for Win64
26182619 if (Subtarget->isTargetWin64()) {
1270512706
1270612707 // Only support length 1 constraints for now.
1270712708 if (Constraint.length() > 1) return;
12708
12709
1270912710 char ConstraintLetter = Constraint[0];
1271012711 switch (ConstraintLetter) {
1271112712 default: break;
857857 ISD::NodeType ExtendKind) const;
858858
859859 virtual bool
860 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
861 const SmallVectorImpl &Outs,
862 LLVMContext &Context) const;
860 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
861 bool isVarArg,
862 const SmallVectorImpl &Outs,
863 LLVMContext &Context) const;
863864
864865 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl &Results,
865866 SelectionDAG &DAG, unsigned NewOp) const;
896896
897897 // Analyze operands of the call, assigning locations to each operand.
898898 SmallVector ArgLocs;
899 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
900 ArgLocs, *DAG.getContext());
899 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
900 getTargetMachine(), ArgLocs, *DAG.getContext());
901901
902902 // The ABI dictates there should be one stack slot available to the callee
903903 // on function entry (for saving lr).
10191019
10201020 // Assign locations to each value returned by this call.
10211021 SmallVector RVLocs;
1022 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1023 RVLocs, *DAG.getContext());
1022 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1023 getTargetMachine(), RVLocs, *DAG.getContext());
10241024
10251025 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
10261026
10791079
10801080 // Assign locations to all of the incoming arguments.
10811081 SmallVector ArgLocs;
1082 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1083 ArgLocs, *DAG.getContext());
1082 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1083 getTargetMachine(), ArgLocs, *DAG.getContext());
10841084
10851085 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
10861086
11841184 //===----------------------------------------------------------------------===//
11851185
11861186 bool XCoreTargetLowering::
1187 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1187 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1188 bool isVarArg,
11881189 const SmallVectorImpl &Outs,
11891190 LLVMContext &Context) const {
11901191 SmallVector RVLocs;
1191 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1192 RVLocs, Context);
1192 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
11931193 return CCInfo.CheckReturn(Outs, RetCC_XCore);
11941194 }
11951195
12051205 SmallVector RVLocs;
12061206
12071207 // CCState - Info about the registers and stack slot.
1208 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1209 RVLocs, *DAG.getContext());
1210
1211 // Analize return values.
1208 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1209 getTargetMachine(), RVLocs, *DAG.getContext());
1210
1211 // Analyze return values.
12121212 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
12131213
12141214 // If this is the first return lowered for this function, add
190190 DebugLoc dl, SelectionDAG &DAG) const;
191191
192192 virtual bool
193 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
193 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
194 bool isVarArg,
194195 const SmallVectorImpl &ArgsFlags,
195196 LLVMContext &Context) const;
196197 };