llvm.org GIT mirror llvm / 471850a
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 10 years ago
9 changed file(s) with 61 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
4747 STATISTIC(NumNoops, "Number of noops inserted");
4848 STATISTIC(NumStalls, "Number of pipeline stalls");
4949
50 // Post-RA scheduling is enabled with
51 // TargetSubtarget.enablePostRAScheduler(). This flag can be used to
52 // override the target.
53 static cl::opt
54 EnablePostRAScheduler("post-RA-scheduler",
55 cl::desc("Enable scheduling after register allocation"),
56 cl::init(false));
5057 static cl::opt
5158 EnableAntiDepBreaking("break-anti-dependencies",
5259 cl::desc("Break post-RA scheduling anti-dependencies"),
5360 cl::init(true), cl::Hidden);
54
5561 static cl::opt
5662 EnablePostRAHazardAvoidance("avoid-hazards",
5763 cl::desc("Enable exact hazard avoidance"),
214220 }
215221
216222 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
217 // Check that post-RA scheduling is enabled for this function
218 const TargetSubtarget &ST = Fn.getTarget().getSubtarget();
219 if (!ST.enablePostRAScheduler())
220 return true;
223 // Check for explicit enable/disable of post-ra scheduling.
224 if (EnablePostRAScheduler.getPosition() > 0) {
225 if (!EnablePostRAScheduler)
226 return true;
227 } else {
228 // Check that post-RA scheduling is enabled for this function
229 const TargetSubtarget &ST = Fn.getTarget().getSubtarget();
230 if (!ST.enablePostRAScheduler())
231 return true;
232 }
221233
222234 DEBUG(errs() << "PostRAScheduler\n");
223235
4242 def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
4343 "true",
4444 "Use NEON for single-precision FP">;
45 def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler",
46 "true",
47 "Use Post-Register-Allocation Scheduler">;
4845
4946 //===----------------------------------------------------------------------===//
5047 // ARM Processors supported.
107104
108105 // V7 Processors.
109106 def : Processor<"cortex-a8", CortexA8Itineraries,
110 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP,
111 FeaturePostRASched]>;
107 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
112108 def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
113109
114110 //===----------------------------------------------------------------------===//
9292
9393 if (isTargetDarwin())
9494 IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
95
96 // Set CPU specific features.
97 if (CPUString == "cortex-a8") {
98 PostRAScheduler = true;
99 }
95100 }
96101
97102 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
None ; RUN: llc < %s -march=arm -mattr=+vfp2,+postrasched -mcpu=cortex-a8
0 ; RUN: llc < %s -march=arm -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
0 ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
0 ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
None ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
0 ; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
11
22 ; ModuleID = ''
33 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
0 ; XFAIL: *
1 ; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched | FileCheck %s
1 ; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s
22
33
44 ; ModuleID = ''
0 ; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t
1 ; RUN: grep {%xmm0} %t | count 14
2 ; RUN: not grep {%xmm1} %t
3 ; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t
4 ; RUN: grep {%xmm0} %t | count 7
5 ; RUN: grep {%xmm1} %t | count 7
6
7 define void @goo(double* %r, double* %p, double* %q) nounwind {
8 entry:
9 %0 = load double* %p, align 8
10 %1 = fadd double %0, 1.100000e+00
11 %2 = fmul double %1, 1.200000e+00
12 %3 = fadd double %2, 1.300000e+00
13 %4 = fmul double %3, 1.400000e+00
14 %5 = fadd double %4, 1.500000e+00
15 %6 = fptosi double %5 to i32
16 %7 = load double* %r, align 8
17 %8 = fadd double %7, 7.100000e+00
18 %9 = fmul double %8, 7.200000e+00
19 %10 = fadd double %9, 7.300000e+00
20 %11 = fmul double %10, 7.400000e+00
21 %12 = fadd double %11, 7.500000e+00
22 %13 = fptosi double %12 to i32
23 %14 = icmp slt i32 %6, %13
24 br i1 %14, label %bb, label %return
25
26 bb:
27 store double 9.300000e+00, double* %q, align 8
28 ret void
29
30 return:
31 ret void
32 }