llvm.org GIT mirror llvm / 46d36be
Fix some doc and comment typos git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8 Alp Toker 6 years ago
20 changed file(s) with 27 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
112112 -----
113113
114114 * `The XMOS XS1 Architecture (ISA) `_
115 * `Tools Developement Guide (includes ABI) `_
115 * `Tools Development Guide (includes ABI) `_
116116
117117 Other relevant lists
118118 --------------------
69686968
69696969 On platforms with coherent instruction and data caches (e.g. x86), this
69706970 intrinsic is a nop. On platforms with non-coherent instruction and data
6971 cache (e.g. ARM, MIPS), the intrinsic is lowered either to appropiate
6971 cache (e.g. ARM, MIPS), the intrinsic is lowered either to appropriate
69726972 instructions or a system call, if cache flushing requires special
69736973 privileges.
69746974
2828 typedef unsigned NodeId;
2929 typedef unsigned EdgeId;
3030
31 /// \brief Returns a value representing an invalid (non-existant) node.
31 /// \brief Returns a value representing an invalid (non-existent) node.
3232 static NodeId invalidNodeId() {
3333 return std::numeric_limits::max();
3434 }
3535
36 /// \brief Returns a value representing an invalid (non-existant) edge.
36 /// \brief Returns a value representing an invalid (non-existent) edge.
3737 static EdgeId invalidEdgeId() {
3838 return std::numeric_limits::max();
3939 }
228228 /// Name of the input file associated with this diagnostic.
229229 const char *FileName;
230230
231 /// Line number where the diagnostic occured. If 0, no line number will
231 /// Line number where the diagnostic occurred. If 0, no line number will
232232 /// be emitted in the message.
233233 unsigned LineNum;
234234
4848 return this - getUser()->op_begin();
4949 }
5050
51 // Sets up the waymarking algoritm's tags for a series of Uses. See the
51 // Sets up the waymarking algorithm's tags for a series of Uses. See the
5252 // algorithm details here:
5353 //
5454 // http://www.llvm.org/docs/ProgrammersManual.html#UserLayout
5858
5959 // Floating Point MAC, Mul, Div, Sqrt
6060 // Most processors will simply send all of these down a dedicated pipe, but
61 // they're explicitly seperated here for flexibility of modeling later. May
61 // they're explicitly separated here for flexibility of modeling later. May
6262 // consider consolidating them into a single WriteFPXXXX type in the future.
6363 def WriteFPMAC : SchedWrite;
6464 def WriteFPMul : SchedWrite;
16741674 if (MF.getFunction()->isVarArg())
16751675 report_fatal_error("Segmented stacks do not support vararg functions.");
16761676 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1677 report_fatal_error("Segmented stacks not supported on this platfrom.");
1677 report_fatal_error("Segmented stacks not supported on this platform.");
16781678
16791679 MachineBasicBlock &prologueMBB = MF.front();
16801680 MachineFrameInfo *MFI = MF.getFrameInfo();
1313 //===----------------------------------------------------------------------===//
1414 // TODO: Graph based predicate heuristics.
1515 // Walking the instruction list linearly will get many, perhaps most, of
16 // the cases, but to do a truly throrough job of this, we need a more
16 // the cases, but to do a truly thorough job of this, we need a more
1717 // wholistic approach.
1818 //
1919 // This optimization is very similar in spirit to the register allocator's
7373 // instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
7474 bool isProfitableToTransform(const MachineInstr *MI) const;
7575
76 // tranformInstruction - Perform the transformation of an instruction
76 // transformInstruction - Perform the transformation of an instruction
7777 // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
7878 // to be the correct register class, minimizing cross-class copies.
7979 void transformInstruction(MachineInstr *MI);
251251 if (AllUsesAreCopies)
252252 --NumNewCopies;
253253
254 // If a tranform will not increase the number of cross-class copies required,
254 // If a transform will not increase the number of cross-class copies required,
255255 // return true.
256256 if (NumNewCopies <= NumRemovableCopies)
257257 return true;
272272 return MIB;
273273 }
274274
275 // tranformInstruction - Perform the transformation of an instruction
275 // transformInstruction - Perform the transformation of an instruction
276276 // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
277277 // to be the correct register class, minimizing cross-class copies.
278278 void ARM64AdvSIMDScalar::transformInstruction(MachineInstr *MI) {
458458 delete[] IT->second;
459459 }
460460
461 /// Reaching definiton algorithm.
461 /// Reaching definition algorithm.
462462 /// \param MF function on which the algorithm will operate.
463463 /// \param[out] ColorOpToReachedUses will contain the result of the reaching
464464 /// def algorithm.
465465 /// \param ADRPMode specify whether the reaching def algorithm should be tuned
466466 /// for ADRP optimization. \see initReachingDef for more details.
467467 /// \param DummyOp if not NULL, the algorithm will work at
468 /// basic block scope and will set for every exposed defintion a use to
468 /// basic block scope and will set for every exposed definition a use to
469469 /// @p DummyOp.
470470 /// \pre ColorOpToReachedUses is an array of at least number of registers of
471471 /// InstrToInstrs.
583583 return false;
584584 }
585585
586 /// Given the result of a reaching defintion algorithm in ColorOpToReachedUses,
586 /// Given the result of a reaching definition algorithm in ColorOpToReachedUses,
587587 /// Build the Use to Defs information and filter out obvious non-LOH candidates.
588588 /// In ADRPMode, non-LOH candidates are "uses" with non-ADRP definitions.
589589 /// In non-ADRPMode, non-LOH candidates are "uses" with several definition,
146146 /// else.
147147 MachineBasicBlock *Head;
148148
149 /// The block containing cmp+br.cond with a sucessor shared with Head.
149 /// The block containing cmp+br.cond with a successor shared with Head.
150150 MachineBasicBlock *CmpBB;
151151
152152 /// The common successor for Head and CmpBB.
419419 return false;
420420 }
421421
422 // Only CmpMI is alowed to clobber the flags.
422 // Only CmpMI is allowed to clobber the flags.
423423 if (&*I != CmpMI && I->modifiesRegister(ARM64::CPSR, TRI)) {
424424 DEBUG(dbgs() << "Clobbers flags: " << *I);
425425 return false;
645645
646646
647647 //---
648 // Sytem management
648 // System management
649649 //---
650650
651651 // Base encoding for system instruction operands.
7575 BitVector ARM64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
7676 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
7777
78 // FIXME: avoid re-calculating this everytime.
78 // FIXME: avoid re-calculating this every time.
7979 BitVector Reserved(getNumRegs());
8080 Reserved.set(ARM64::SP);
8181 Reserved.set(ARM64::XZR);
163163 X22, X23, X24, X25, X26,
164164 X27, X28)>;
165165
166 // GPR register classes for post increment ammount of vector load/store that
166 // GPR register classes for post increment amount of vector load/store that
167167 // has alternate printing when Rm=31 and prints a constant immediate value
168168 // equal to the total number of bytes transferred.
169169 def GPR64pi1 : RegisterOperand;
221221 "difference");
222222
223223 // ARM64 always uses external relocations. If there is no symbol to use as
224 // a base address (a local symbol with no preceeding non-local symbol),
224 // a base address (a local symbol with no preceding non-local symbol),
225225 // error out.
226226 //
227227 // FIXME: We should probably just synthesize an external symbol and use
314314 /// \brief Name of the profile file to load.
315315 StringRef Filename;
316316
317 /// \brief Flag indicating whether the profile input loaded succesfully.
317 /// \brief Flag indicating whether the profile input loaded successfully.
318318 bool ProfileIsValid;
319319 };
320320 }
55 define i32 @fct(i32 %i1, i32 %i2) {
66 ; CHECK: @fct
77 ; Sign extension is used more than once, thus it should not be folded.
8 ; CodeGenPrepare is not sharing sext accross uses, thus this is folded because
8 ; CodeGenPrepare is not sharing sext across uses, thus this is folded because
99 ; of that.
1010 ; _CHECK-NOT_: , sxtw]
1111 entry:
55 ; CHECK-LABEL: one_lane:
66 ; CHECK: dup.16b v[[REG:[0-9]+]], wzr
77 ; CHECK-NEXT: ins.b v[[REG]][0], w1
8 ; v and q are aliases, and str is prefered against st.16b when possible
8 ; v and q are aliases, and str is preferred against st.16b when possible
99 ; rdar://11246289
1010 ; CHECK: str q[[REG]], [x0]
1111 ; CHECK: ret
1313 ; }
1414 ;
1515 ; Test that we generate valid debug info for optimized code,
16 ; particularily variables that are described as constants and passed
16 ; particularly variables that are described as constants and passed
1717 ; by reference.
1818 ; rdar://problem/14874886
1919 ;
0 ; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
11
2 ; ARM64 uses a multi-character statment separator, "%%". Check that we lex
2 ; ARM64 uses a multi-character statement separator, "%%". Check that we lex
33 ; it properly and recognize the multiple assembly statements on the line.
44
55 ; To make sure the output assembly correctly handled the instructions,
11 # RUN: -mattr=+micromips 2>&1 -filetype=obj > %t.o
22 # RUN: llvm-objdump %t.o -triple mipsel -mattr=+micromips -d | FileCheck %s
33
4 # Check that fixup data is writen in the microMIPS specific little endian
4 # Check that fixup data is written in the microMIPS specific little endian
55 # byte order.
66
77 .text