llvm.org GIT mirror llvm / 46adf81
change the addressing mode of the str instruction to reg+imm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 14 years ago
4 changed file(s) with 13 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
2121 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
2222 }
2323
24 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
25 return &ARM::IntRegsRegClass;
26 }
27
2428 /// Return true if the instruction is a register to register move and
2529 /// leave the source and dest operands in the passed parameters.
2630 ///
3030 ///
3131 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
3232
33 /// getPointerRegClass - Return the register class to use to hold pointers.
34 /// This is used for addressing modes.
35 virtual const TargetRegisterClass *getPointerRegClass() const;
36
3337 /// Return true if the instruction is a register to register move and
3438 /// leave the source and dest operands in the passed parameters.
3539 ///
6666 "ldr $dst, $addr",
6767 [(set IntRegs:$dst, (load iaddr:$addr))]>;
6868
69 def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
70 "str $src, [$addr]",
71 [(store IntRegs:$src, IntRegs:$addr)]>;
69 def str : InstARM<(ops IntRegs:$src, memri:$addr),
70 "str $src, $addr",
71 [(store IntRegs:$src, iaddr:$addr)]>;
7272
7373 def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
7474 "mov $dst, $src", []>;
134134
135135 //sub sp, sp, #NumBytes
136136 BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
137 //add ip, sp, #NumBytes - 4
138 BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(NumBytes - 4);
139 //str lr, [ip]
140 BuildMI(MBB, MBBI, ARM::str, 1, ARM::R14).addReg(ARM::R12);
137 //str lr, [sp, #NumBytes - 4]
138 BuildMI(MBB, MBBI, ARM::str, 2, ARM::R14).addImm(NumBytes - 4).addReg(ARM::R13);
141139 }
142140
143141 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,