llvm.org GIT mirror llvm / 46995fa
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8 Eli Friedman 8 years ago
2 changed file(s) with 25 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
40554055 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
40564056 // A shuffle can only come from building a vector from various
40574057 // elements of other vectors.
4058 return SDValue();
4059 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4060 VT.getVectorElementType()) {
4061 // This code doesn't know how to handle shuffles where the vector
4062 // element types do not match (this happens because type legalization
4063 // promotes the return type of EXTRACT_VECTOR_ELT).
4064 // FIXME: It might be appropriate to extend this code to handle
4065 // mismatched types.
40584066 return SDValue();
40594067 }
40604068
132132 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32>
133133 ret <8 x i16> %tmp3
134134 }
135
136 ; PR11129
137 ; Make sure this doesn't crash
138 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
139 ; CHECK: test_elem_mismatch:
140 ; CHECK: vstr.64
141 %tmp0 = load <2 x i64>* %src, align 16
142 %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
143 %tmp2 = extractelement <4 x i32> %tmp1, i32 0
144 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
145 %tmp4 = trunc i32 %tmp2 to i16
146 %tmp5 = trunc i32 %tmp3 to i16
147 %tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0
148 %tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1
149 store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
150 ret void
151 }