llvm.org GIT mirror llvm / 468a2a4
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
8 changed file(s) with 1 addition(s) and 315 deletion(s). Raw diff Collapse all Expand all
2121 X86COFFMachineModuleInfo.cpp
2222 X86ELFWriterInfo.cpp
2323 X86FloatingPoint.cpp
24 X86FloatingPointRegKill.cpp
2524 X86ISelDAGToDAG.cpp
2625 X86ISelLowering.cpp
2726 X86InstrInfo.cpp
4848 /// crossings.
4949 FunctionPass *createSSEDomainFixPass();
5050
51 /// createX87FPRegKillInserterPass - This function returns a pass which
52 /// inserts FP_REG_KILL instructions where needed.
53 ///
54 FunctionPass *createX87FPRegKillInserterPass();
55
5651 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
5752 /// to the specified MCE object.
5853 FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
621621
622622 case TargetOpcode::IMPLICIT_DEF:
623623 case TargetOpcode::KILL:
624 case X86::FP_REG_KILL:
625624 break;
626625 case X86::MOVPC32r: {
627626 // This emits the "call" portion of this pseudo instruction.
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lib/Target/X86/X86FloatingPointRegKill.cpp less more
None //===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the pass which inserts FP_REG_KILL instructions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "x86-codegen"
14 #include "X86.h"
15 #include "X86InstrInfo.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/ADT/Statistic.h"
25 using namespace llvm;
26
27 STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added");
28
29 namespace {
30 struct FPRegKiller : public MachineFunctionPass {
31 static char ID;
32 FPRegKiller() : MachineFunctionPass(&ID) {}
33
34 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
35 AU.setPreservesCFG();
36 AU.addPreservedID(MachineLoopInfoID);
37 AU.addPreservedID(MachineDominatorsID);
38 MachineFunctionPass::getAnalysisUsage(AU);
39 }
40
41 virtual bool runOnMachineFunction(MachineFunction &MF);
42
43 virtual const char *getPassName() const {
44 return "X86 FP_REG_KILL inserter";
45 }
46 };
47 char FPRegKiller::ID = 0;
48 }
49
50 FunctionPass *llvm::createX87FPRegKillInserterPass() {
51 return new FPRegKiller();
52 }
53
54 /// isFPStackVReg - Return true if the specified vreg is from a fp stack
55 /// register class.
56 static bool isFPStackVReg(unsigned RegNo, const MachineRegisterInfo &MRI) {
57 if (!TargetRegisterInfo::isVirtualRegister(RegNo))
58 return false;
59
60 switch (MRI.getRegClass(RegNo)->getID()) {
61 default: return false;
62 case X86::RFP32RegClassID:
63 case X86::RFP64RegClassID:
64 case X86::RFP80RegClassID:
65 return true;
66 }
67 }
68
69
70 /// ContainsFPStackCode - Return true if the specific MBB has floating point
71 /// stack code, and thus needs an FP_REG_KILL.
72 static bool ContainsFPStackCode(MachineBasicBlock *MBB,
73 const MachineRegisterInfo &MRI) {
74 // Scan the block, looking for instructions that define or use fp stack vregs.
75 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
76 I != E; ++I) {
77 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
78 if (!I->getOperand(op).isReg())
79 continue;
80 if (unsigned Reg = I->getOperand(op).getReg())
81 if (isFPStackVReg(Reg, MRI))
82 return true;
83 }
84 }
85
86 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
87 // a copy of the input value in this block, which is a definition of the
88 // value.
89 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
90 E = MBB->succ_end(); SI != E; ++ SI) {
91 MachineBasicBlock *SuccBB = *SI;
92 for (MachineBasicBlock::iterator I = SuccBB->begin(), E = SuccBB->end();
93 I != E; ++I) {
94 // All PHI nodes are at the top of the block.
95 if (!I->isPHI()) break;
96
97 if (isFPStackVReg(I->getOperand(0).getReg(), MRI))
98 return true;
99 }
100 }
101
102 return false;
103 }
104
105 bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) {
106 // If we are emitting FP stack code, scan the basic block to determine if this
107 // block defines or uses any FP values. If so, put an FP_REG_KILL instruction
108 // before the terminator of the block.
109
110 // Note that FP stack instructions are used in all modes for long double,
111 // so we always need to do this check.
112 // Also note that it's possible for an FP stack register to be live across
113 // an instruction that produces multiple basic blocks (SSE CMOV) so we
114 // must check all the generated basic blocks.
115
116 // Scan all of the machine instructions in these MBBs, checking for FP
117 // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
118
119 // Fast-path: If nothing is using the x87 registers, we don't need to do
120 // any scanning.
121 const MachineRegisterInfo &MRI = MF.getRegInfo();
122 if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() &&
123 MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() &&
124 MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty())
125 return false;
126
127 bool Changed = false;
128 MachineFunction::iterator MBBI = MF.begin();
129 MachineFunction::iterator EndMBB = MF.end();
130 for (; MBBI != EndMBB; ++MBBI) {
131 MachineBasicBlock *MBB = MBBI;
132
133 // If this block returns, ignore it. We don't want to insert an FP_REG_KILL
134 // before the return.
135 if (!MBB->empty()) {
136 MachineBasicBlock::iterator EndI = MBB->end();
137 --EndI;
138 if (EndI->getDesc().isReturn())
139 continue;
140 }
141
142 // If we find any FP stack code, emit the FP_REG_KILL instruction.
143 if (ContainsFPStackCode(MBB, MRI)) {
144 BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc(),
145 MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
146 ++NumFPKill;
147 Changed = true;
148 }
149 }
150
151 return Changed;
152 }
107107 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
108108 }
109109
110 let isTerminator = 1 in
111 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
112 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
113
114110 // All FP Stack operations are represented with four instructions here. The
115111 // first three instructions, generated by the instruction selector, use "RFP32"
116112 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
16631663 return !isPredicated(MI);
16641664 }
16651665
1666 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1667 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1668 const X86InstrInfo &TII) {
1669 if (MI->getOpcode() == X86::FP_REG_KILL)
1670 return false;
1671 return TII.isUnpredicatedTerminator(MI);
1672 }
1673
16741666 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
16751667 MachineBasicBlock *&TBB,
16761668 MachineBasicBlock *&FBB,
16871679
16881680 // Working from the bottom, when we see a non-terminator instruction, we're
16891681 // done.
1690 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1682 if (!isUnpredicatedTerminator(I))
16911683 break;
16921684
16931685 // A terminator that isn't a branch can't easily be handled by this
33403332 break;
33413333 case TargetOpcode::IMPLICIT_DEF:
33423334 case TargetOpcode::KILL:
3343 case X86::FP_REG_KILL:
33443335 break;
33453336 case X86::MOVPC32r: {
33463337 // This emits the "call" portion of this pseudo instruction.
1818 #include "llvm/CodeGen/Passes.h"
1919 #include "llvm/MC/MCCodeEmitter.h"
2020 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/Support/CommandLine.h"
2221 #include "llvm/Support/FormattedStream.h"
2322 #include "llvm/Target/TargetOptions.h"
2423 #include "llvm/Target/TargetRegistry.h"
2524 using namespace llvm;
26
27 static cl::opt
28 LiveX87("live-x87", cl::desc("Allow live X87 registers across blocks"));
2925
3026 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
3127 Triple TheTriple(TT);
185181
186182 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
187183 CodeGenOpt::Level OptLevel) {
188 // Install a pass to insert x87 FP_REG_KILL instructions, as needed.
189 if (!LiveX87)
190 PM.add(createX87FPRegKillInserterPass());
191
192184 PM.add(createX86MaxStackAlignmentHeuristicPass());
193185 return false; // -print-machineinstr shouldn't print after this.
194186 }
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test/CodeGen/X86/2007-06-14-branchfold.ll less more
None ; RUN: llc < %s -march=x86 -mcpu=i686 | not grep jmp
1 ; check that branch folding understands FP_REG_KILL is not a branch
2
3 target triple = "i686-pc-linux-gnu"
4 %struct.FRAME.c34003a = type { float, float }
5 @report_E = global i8 0 ; [#uses=0]
6
7 define void @main() {
8 entry:
9 %FRAME.31 = alloca %struct.FRAME.c34003a, align 8 ; <%struct.FRAME.c34003a*> [#uses=4]
10 %tmp20 = call i32 @report__ident_int( i32 -50 ) ; [#uses=1]
11 %tmp2021 = sitofp i32 %tmp20 to float ; [#uses=5]
12 %tmp23 = fcmp ult float %tmp2021, 0xC7EFFFFFE0000000 ; [#uses=1]
13 %tmp26 = fcmp ugt float %tmp2021, 0x47EFFFFFE0000000 ; [#uses=1]
14 %bothcond = or i1 %tmp23, %tmp26 ; [#uses=1]
15 br i1 %bothcond, label %bb, label %bb30
16
17 bb: ; preds = %entry
18 unwind
19
20 bb30: ; preds = %entry
21 %tmp35 = call i32 @report__ident_int( i32 50 ) ; [#uses=1]
22 %tmp3536 = sitofp i32 %tmp35 to float ; [#uses=4]
23 %tmp38 = fcmp ult float %tmp3536, 0xC7EFFFFFE0000000 ; [#uses=1]
24 %tmp44 = fcmp ugt float %tmp3536, 0x47EFFFFFE0000000 ; [#uses=1]
25 %bothcond226 = or i1 %tmp38, %tmp44 ; [#uses=1]
26 br i1 %bothcond226, label %bb47, label %bb49
27
28 bb47: ; preds = %bb30
29 unwind
30
31 bb49: ; preds = %bb30
32 %tmp60 = fcmp ult float %tmp3536, %tmp2021 ; [#uses=1]
33 %tmp60.not = xor i1 %tmp60, true ; [#uses=1]
34 %tmp65 = fcmp olt float %tmp2021, 0xC7EFFFFFE0000000 ; [#uses=1]
35 %bothcond227 = and i1 %tmp65, %tmp60.not ; [#uses=1]
36 br i1 %bothcond227, label %cond_true68, label %cond_next70
37
38 cond_true68: ; preds = %bb49
39 unwind
40
41 cond_next70: ; preds = %bb49
42 %tmp71 = call i32 @report__ident_int( i32 -30 ) ; [#uses=1]
43 %tmp7172 = sitofp i32 %tmp71 to float ; [#uses=3]
44 %tmp74 = fcmp ult float %tmp7172, 0xC7EFFFFFE0000000 ; [#uses=1]
45 %tmp80 = fcmp ugt float %tmp7172, 0x47EFFFFFE0000000 ; [#uses=1]
46 %bothcond228 = or i1 %tmp74, %tmp80 ; [#uses=1]
47 br i1 %bothcond228, label %bb83, label %bb85
48
49 bb83: ; preds = %cond_next70
50 unwind
51
52 bb85: ; preds = %cond_next70
53 %tmp90 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 1 ; [#uses=3]
54 store float %tmp7172, float* %tmp90
55 %tmp92 = call i32 @report__ident_int( i32 30 ) ; [#uses=1]
56 %tmp9293 = sitofp i32 %tmp92 to float ; [#uses=7]
57 %tmp95 = fcmp ult float %tmp9293, 0xC7EFFFFFE0000000 ; [#uses=1]
58 %tmp101 = fcmp ugt float %tmp9293, 0x47EFFFFFE0000000 ; [#uses=1]
59 %bothcond229 = or i1 %tmp95, %tmp101 ; [#uses=1]
60 br i1 %bothcond229, label %bb104, label %bb106
61
62 bb104: ; preds = %bb85
63 unwind
64
65 bb106: ; preds = %bb85
66 %tmp111 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 0 ; [#uses=2]
67 store float %tmp9293, float* %tmp111
68 %tmp123 = load float* %tmp90 ; [#uses=4]
69 %tmp125 = fcmp ult float %tmp9293, %tmp123 ; [#uses=1]
70 br i1 %tmp125, label %cond_next147, label %cond_true128
71
72 cond_true128: ; preds = %bb106
73 %tmp133 = fcmp olt float %tmp123, %tmp2021 ; [#uses=1]
74 %tmp142 = fcmp ogt float %tmp9293, %tmp3536 ; [#uses=1]
75 %bothcond230 = or i1 %tmp133, %tmp142 ; [#uses=1]
76 br i1 %bothcond230, label %bb145, label %cond_next147
77
78 bb145: ; preds = %cond_true128
79 unwind
80
81 cond_next147: ; preds = %cond_true128, %bb106
82 %tmp157 = fcmp ugt float %tmp123, -3.000000e+01 ; [#uses=1]
83 %tmp165 = fcmp ult float %tmp9293, -3.000000e+01 ; [#uses=1]
84 %bothcond231 = or i1 %tmp157, %tmp165 ; [#uses=1]
85 br i1 %bothcond231, label %bb168, label %bb169
86
87 bb168: ; preds = %cond_next147
88 unwind
89
90 bb169: ; preds = %cond_next147
91 %tmp176 = fcmp ugt float %tmp123, 3.000000e+01 ; [#uses=1]
92 %tmp184 = fcmp ult float %tmp9293, 3.000000e+01 ; [#uses=1]
93 %bothcond232 = or i1 %tmp176, %tmp184 ; [#uses=1]
94 br i1 %bothcond232, label %bb187, label %bb188
95
96 bb187: ; preds = %bb169
97 unwind
98
99 bb188: ; preds = %bb169
100 %tmp192 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 3.000000e+01 ) ; [#uses=2]
101 %tmp194 = load float* %tmp90 ; [#uses=1]
102 %tmp196 = fcmp ugt float %tmp194, 0.000000e+00 ; [#uses=1]
103 br i1 %tmp196, label %bb207, label %cond_next200
104
105 cond_next200: ; preds = %bb188
106 %tmp202 = load float* %tmp111 ; [#uses=1]
107 %tmp204 = fcmp ult float %tmp202, 0.000000e+00 ; [#uses=1]
108 br i1 %tmp204, label %bb207, label %bb208
109
110 bb207: ; preds = %cond_next200, %bb188
111 unwind
112
113 bb208: ; preds = %cond_next200
114 %tmp212 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 0.000000e+00 ) ; [#uses=1]
115 %tmp214 = fcmp oge float %tmp212, %tmp192 ; [#uses=1]
116 %tmp217 = fcmp oge float %tmp192, 1.000000e+02 ; [#uses=1]
117 %tmp221 = or i1 %tmp214, %tmp217 ; [#uses=1]
118 br i1 %tmp221, label %cond_true224, label %UnifiedReturnBlock
119
120 cond_true224: ; preds = %bb208
121 call void @abort( ) noreturn
122 ret void
123
124 UnifiedReturnBlock: ; preds = %bb208
125 ret void
126 }
127
128 declare fastcc float @c34003a__ident.154(%struct.FRAME.c34003a* %CHAIN.32, float %x)
129
130 declare i32 @report__ident_int(i32 %x)
131
132 declare void @abort() noreturn