llvm.org GIT mirror llvm / 4664657
Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160235 91177308-0d34-0410-b5e6-96231b3b80d8 Nadav Rotem 8 years ago
3 changed file(s) with 18 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
515515 SDValue ScalarizeVecRes_InregOp(SDNode *N);
516516
517517 SDValue ScalarizeVecRes_BITCAST(SDNode *N);
518 SDValue ScalarizeVecRes_BUILD_VECTOR(SDNode *N);
518519 SDValue ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N);
519520 SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
520521 SDValue ScalarizeVecRes_FP_ROUND(SDNode *N);
4747
4848 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
4949 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
50 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
5151 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
5252 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
5353 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
151151 NewVT, N->getOperand(0));
152152 }
153153
154 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
155 EVT EltVT = N->getValueType(0).getVectorElementType();
156 SDValue InOp = N->getOperand(0);
157 if (InOp.getValueType() != EltVT)
158 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
159 return InOp;
160 }
161
154162 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
155163 EVT NewVT = N->getValueType(0).getVectorElementType();
156164 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
0 ; RUN: llc -mcpu=corei7 < %s
1 ; We don't care about the output, just that it doesn't crash
2
3 define <1 x i1> @buildvec_promote() {
4 %cmp = icmp ule <1 x i32> undef, undef
5 %sel = select i1 undef, <1 x i1> undef, <1 x i1> %cmp
6 ret <1 x i1> %sel
7 }