llvm.org GIT mirror llvm / 459a7c6
Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
5 changed file(s) with 177 addition(s) and 66 deletion(s). Raw diff Collapse all Expand all
6868 /// available, unset means the register is currently being used.
6969 BitVector RegsAvailable;
7070
71 /// ImplicitDefed - If bit is set that means the register is defined by an
72 /// implicit_def instructions. That means it can be clobbered at will.
73 BitVector ImplicitDefed;
74
7571 /// CurrDist - Distance from MBB entry to the current instruction MBBI.
7672 ///
7773 unsigned CurrDist;
116112 bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
117113 bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
118114
119 bool isImplicitlyDefined(unsigned Reg) const { return ImplicitDefed[Reg]; }
120
121115 /// getRegsUsed - return all registers currently in use in used.
122116 void getRegsUsed(BitVector &used, bool includeReserved);
123117
124118 /// setUsed / setUnused - Mark the state of one or a number of registers.
125119 ///
126 void setUsed(unsigned Reg, bool ImpDef = false);
127 void setUsed(BitVector &Regs, bool ImpDef = false) {
120 void setUsed(unsigned Reg);
121 void setUsed(BitVector &Regs) {
128122 RegsAvailable &= ~Regs;
129 if (ImpDef)
130 ImplicitDefed |= Regs;
131 else
132 ImplicitDefed &= ~Regs;
133123 }
134124 void setUnused(unsigned Reg, const MachineInstr *MI);
135125 void setUnused(BitVector &Regs) {
136126 RegsAvailable |= Regs;
137 ImplicitDefed &= ~Regs;
138127 }
139128
140129 /// FindUnusedReg - Find a unused register of the specified register class
123123 ImpDefMIs.push_back(MI);
124124 continue;
125125 }
126 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
126
127 bool ChangedToImpDef = false;
128 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
127129 MachineOperand& MO = MI->getOperand(i);
128130 if (!MO.isReg() || !MO.isUse())
129131 continue;
132134 continue;
133135 if (!ImpDefRegs.count(Reg))
134136 continue;
137 // Use is a copy, just turn it into an implicit_def.
138 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
139 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
140 Reg == SrcReg) {
141 bool isKill = MO.isKill();
142 MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
143 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
144 MI->RemoveOperand(j);
145 if (isKill)
146 ImpDefRegs.erase(Reg);
147 ChangedToImpDef = true;
148 break;
149 }
150
135151 MO.setIsUndef();
136152 if (MO.isKill() || MI->isRegTiedToDefOperand(i))
137153 ImpDefRegs.erase(Reg);
138154 }
139155
140 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
141 MachineOperand& MO = MI->getOperand(i);
142 if (!MO.isReg() || !MO.isDef())
143 continue;
144 ImpDefRegs.erase(MO.getReg());
156 if (ChangedToImpDef) {
157 // Backtrack to process this new implicit_def.
158 --I;
159 } else {
160 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
161 MachineOperand& MO = MI->getOperand(i);
162 if (!MO.isReg() || !MO.isDef())
163 continue;
164 ImpDefRegs.erase(MO.getReg());
165 }
145166 }
146167 }
147168
154175 continue;
155176 if (!ImpDefRegs.count(Reg))
156177 continue;
157 bool HasLocalUse = false;
158 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(Reg),
159 RE = mri_->reg_end(); RI != RE; ) {
160 MachineOperand &RMO = RI.getOperand();
161 MachineInstr *RMI = &*RI;
162 ++RI;
163 if (RMO.isDef()) {
164 // Don't expect another def of the same register.
165 assert(RMI == MI &&
166 "Register with multiple defs including an implicit_def?");
178
179 // If there are multiple defs of the same register and at least one
180 // is not an implicit_def, do not insert implicit_def's before the
181 // uses.
182 bool Skip = false;
183 for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
184 DE = mri_->def_end(); DI != DE; ++DI) {
185 if (DI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
186 Skip = true;
187 break;
188 }
189 }
190 if (Skip)
191 continue;
192
193 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
194 UE = mri_->use_end(); UI != UE; ) {
195 MachineOperand &RMO = UI.getOperand();
196 MachineInstr *RMI = &*UI;
197 ++UI;
198 MachineBasicBlock *RMBB = RMI->getParent();
199 if (RMBB == MBB)
167200 continue;
168 }
169 MachineBasicBlock *RMBB = RMI->getParent();
170 if (RMBB == MBB) {
171 HasLocalUse = true;
172 continue;
173 }
174201 const TargetRegisterClass* RC = mri_->getRegClass(Reg);
175202 unsigned NewVReg = mri_->createVirtualRegister(RC);
176 BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
177 tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
203 MachineInstrBuilder MIB =
204 BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
205 tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
206 (*MIB).getOperand(0).setIsUndef();
178207 RMO.setReg(NewVReg);
179208 RMO.setIsUndef();
180209 RMO.setIsKill();
181210 }
182 if (!HasLocalUse)
183 MI->eraseFromParent();
184211 }
185212 ImpDefRegs.clear();
186213 ImpDefMIs.clear();
5656 }
5757
5858 /// setUsed - Set the register and its sub-registers as being used.
59 void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
59 void RegScavenger::setUsed(unsigned Reg) {
6060 RegsAvailable.reset(Reg);
61 ImplicitDefed[Reg] = ImpDef;
6261
6362 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
64 unsigned SubReg = *SubRegs; ++SubRegs) {
63 unsigned SubReg = *SubRegs; ++SubRegs)
6564 RegsAvailable.reset(SubReg);
66 ImplicitDefed[SubReg] = ImpDef;
67 }
6865 }
6966
7067 /// setUnused - Set the register and its sub-registers as being unused.
7168 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
7269 RegsAvailable.set(Reg);
73 ImplicitDefed.reset(Reg);
7470
7571 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
7672 unsigned SubReg = *SubRegs; ++SubRegs)
77 if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
73 if (!RedefinesSuperRegPart(MI, Reg, TRI))
7874 RegsAvailable.set(SubReg);
79 ImplicitDefed.reset(SubReg);
80 }
8175 }
8276
8377 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
9387 if (!MBB) {
9488 NumPhysRegs = TRI->getNumRegs();
9589 RegsAvailable.resize(NumPhysRegs);
96 ImplicitDefed.resize(NumPhysRegs);
9790
9891 // Create reserved registers bitvector.
9992 ReservedRegs = TRI->getReservedRegs(MF);
112105 ScavengeRestore = NULL;
113106 CurrDist = 0;
114107 DistanceMap.clear();
115 ImplicitDefed.reset();
116108
117109 // All registers started out unused.
118110 RegsAvailable.set();
194186 ScavengeRestore = NULL;
195187 }
196188
197 bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
189 #if 0
190 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
191 return;
192 #endif
198193
199194 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
200195 SmallVector, 4> UseMOs;
220215
221216 assert(isUsed(Reg) && "Using an undefined register!");
222217
223 // Kill of implicit_def defined registers are ignored. e.g.
224 // entry: 0x2029ab8, LLVM BB @0x1b06080, ID#0:
225 // Live Ins: %R0
226 // %R0 = IMPLICIT_DEF
227 // %R0 = IMPLICIT_DEF
228 // STR %R0, %R0, %reg0, 0, 14, %reg0, Mem:ST(4,4) [0x1b06510 + 0]
229 // %R1 = LDR %R0, %reg0, 24, 14, %reg0, Mem:LD(4,4) [0x1b065bc + 0]
230 if (MO.isKill() && !isReserved(Reg) && !isImplicitlyDefined(Reg)) {
218 if (MO.isKill() && !isReserved(Reg)) {
231219 KillRegs.set(Reg);
232220
233221 // Mark sub-registers as used.
277265 // Implicit def is allowed to "re-define" any register. Similarly,
278266 // implicitly defined registers can be clobbered.
279267 assert((isReserved(Reg) || isUnused(Reg) ||
280 IsImpDef || isImplicitlyDefined(Reg) ||
281268 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
282269 "Re-defining a live register!");
283 setUsed(Reg, IsImpDef);
270 setUsed(Reg);
284271 }
285272 }
286273
26682668 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
26692669 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
26702670 CopyMI->RemoveOperand(i);
2671 CopyMI->getOperand(0).setIsUndef();
26712672 bool NoUse = mri_->use_empty(SrcReg);
26722673 if (NoUse) {
2673 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2674 E = mri_->reg_end(); I != E; ) {
2675 assert(I.getOperand().isDef());
2676 MachineInstr *DefMI = &*I;
2677 ++I;
2674 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
2675 RE = mri_->reg_end(); RI != RE; ) {
2676 assert(RI.getOperand().isDef());
2677 MachineInstr *DefMI = &*RI;
2678 ++RI;
26782679 // The implicit_def source has no other uses, delete it.
26792680 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
26802681 li_->RemoveMachineInstrFromMaps(DefMI);
26812682 DefMI->eraseFromParent();
26822683 }
26832684 }
2685
2686 // Mark uses of implicit_def isUndef.
2687 for (MachineRegisterInfo::use_iterator RI = mri_->use_begin(DstReg),
2688 RE = mri_->use_end(); RI != RE; ++RI) {
2689 assert((*RI).getParent() == MBB);
2690 RI.getOperand().setIsUndef();
2691 }
2692
26842693 ++I;
26852694 return true;
26862695 }
0 ; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9
1
2 @XX = external global i32* ; [#uses=1]
3
4 define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
5 entry:
6 br i1 undef, label %bb5, label %bb
7
8 bb: ; preds = %bb, %entry
9 br label %bb
10
11 bb5: ; preds = %entry
12 br i1 undef, label %bb6, label %bb8
13
14 bb6: ; preds = %bb6, %bb5
15 br i1 undef, label %bb8, label %bb6
16
17 bb8: ; preds = %bb6, %bb5
18 br label %bb15
19
20 bb9: ; preds = %bb15
21 br i1 undef, label %bb10, label %bb11
22
23 bb10: ; preds = %bb9
24 unreachable
25
26 bb11: ; preds = %bb9
27 br i1 undef, label %bb15, label %bb12
28
29 bb12: ; preds = %bb11
30 %0 = load i32** @XX, align 4 ; [#uses=0]
31 br label %bb228.i
32
33 bb74.i: ; preds = %bb228.i
34 br i1 undef, label %bb138.i, label %bb145.i
35
36 bb138.i: ; preds = %bb74.i
37 br label %bb145.i
38
39 bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
40 br i1 undef, label %bb146.i, label %bb151.i
41
42 bb146.i: ; preds = %bb145.i
43 br i1 undef, label %bb228.i, label %bb151.i
44
45 bb151.i: ; preds = %bb146.i, %bb145.i
46 br i1 undef, label %bb153.i, label %bb228.i
47
48 bb153.i: ; preds = %bb151.i
49 br i1 undef, label %bb220.i, label %bb.nph.i98
50
51 bb.nph.i98: ; preds = %bb153.i
52 br label %bb158.i
53
54 bb158.i: ; preds = %bb218.i, %bb.nph.i98
55 %1 = sub i32 undef, undef ; [#uses=4]
56 %2 = sub i32 undef, undef ; [#uses=1]
57 br i1 undef, label %bb168.i, label %bb160.i
58
59 bb160.i: ; preds = %bb158.i
60 br i1 undef, label %bb161.i, label %bb168.i
61
62 bb161.i: ; preds = %bb160.i
63 br i1 undef, label %bb168.i, label %bb163.i
64
65 bb163.i: ; preds = %bb161.i
66 br i1 undef, label %bb167.i, label %bb168.i
67
68 bb167.i: ; preds = %bb163.i
69 br label %bb168.i
70
71 bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
72 %f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; [#uses=1]
73 %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1]
74 store i32 %c.14.i, i32* undef, align 4
75 store i32 undef, i32* null, align 4
76 br i1 undef, label %bb211.i, label %bb218.i
77
78 bb211.i: ; preds = %bb168.i
79 br label %bb218.i
80
81 bb218.i: ; preds = %bb211.i, %bb168.i
82 br i1 undef, label %bb220.i, label %bb158.i
83
84 bb220.i: ; preds = %bb218.i, %bb153.i
85 br i1 undef, label %bb221.i, label %bb228.i
86
87 bb221.i: ; preds = %bb220.i
88 br label %bb228.i
89
90 bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
91 br i1 undef, label %bb74.i, label %bb145.i
92
93 bb15: ; preds = %bb11, %bb8
94 br i1 undef, label %return, label %bb9
95
96 return: ; preds = %bb15
97 ret void
98 }