llvm.org GIT mirror llvm / 4552c9a
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 9 years ago
34 changed file(s) with 262 addition(s) and 279 deletion(s). Raw diff Collapse all Expand all
None ##===- lib/Target/Mips/Makefile ---------------------------*- Makefile -*-===##
0 ##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
11 #
22 # The LLVM Compiler Infrastructure
33 #
44 # This file is distributed under the University of Illinois Open Source
55 # License. See LICENSE.TXT for details.
66 #
7 ##===---------------------------------------------------------------------===##
7 ##===----------------------------------------------------------------------===##
88
99 LEVEL = ../../..
1010 LIBRARYNAME = LLVMMipsCodeGen
None //===-- Mips.h - Top-level interface for Mips representation ---*- C++ -*-===//
0 //===-- Mips.h - Top-level interface for Mips representation ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the entry points for global functions defined in
1010 // the LLVM Mips back-end.
1111 //
12 //===---------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
1313
1414 #ifndef TARGET_MIPS_H
1515 #define TARGET_MIPS_H
None //===- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
0 //===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 // This is the top level entry point for the Mips target.
9 //===---------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
1010
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212 // Target-independent interfaces
13 //===---------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
1414
1515 include "llvm/Target/Target.td"
1616
17 //===---------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
1818 // Register File, Calling Conv, Instruction Descriptions
19 //===---------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
2020
2121 include "MipsRegisterInfo.td"
2222 include "MipsSchedule.td"
2525
2626 def MipsInstrInfo : InstrInfo;
2727
28 //===---------------------------------------------------------------------===//
29 // Mips Subtarget features //
30 //===---------------------------------------------------------------------===//
28 //===----------------------------------------------------------------------===//
29 // Mips Subtarget features //
30 //===----------------------------------------------------------------------===//
3131
3232 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
3333 "General Purpose Registers are 64-bit wide.">;
3434 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
3535 "Support 64-bit FP registers.">;
3636 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
37 "true",
38 "Only supports single precision float">;
37 "true", "Only supports single precision float">;
3938 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
4039 "Enable o32 ABI">;
4140 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
5857 "Mips1 ISA Support">;
5958 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
6059 "Mips2 ISA Support">;
61 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion",
62 "Mips32", "Mips32 ISA Support",
60 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
61 "Mips32 ISA Support",
6362 [FeatureCondMov, FeatureBitCount]>;
6463 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
6564 "Mips32r2", "Mips32r2 ISA Support",
6665 [FeatureMips32, FeatureSEInReg]>;
6766
68 //===---------------------------------------------------------------------===//
67 //===----------------------------------------------------------------------===//
6968 // Mips processors supported.
70 //===---------------------------------------------------------------------===//
69 //===----------------------------------------------------------------------===//
7170
7271 class Proc Features>
7372 : Processor;
None //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer -------------------===//
0 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains a printer that converts from our internal representation
1010 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
1111 //
12 //===---------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
1313
1414 #define DEBUG_TYPE "mips-asm-printer"
1515 #include "Mips.h"
6767 const char *getCurrentABIString() const;
6868 void emitFrameDirective();
6969
70 void printInstruction(const MachineInstr *MI,
71 raw_ostream &O); // autogen'd.
70 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
7271 void EmitInstruction(const MachineInstr *MI) {
7372 SmallString<128> Str;
7473 raw_svector_ostream OS(Str);
7776 }
7877 virtual void EmitFunctionBodyStart();
7978 virtual void EmitFunctionBodyEnd();
80 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock
81 *MBB) const;
79 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
80 MBB) const;
8281 static const char *getRegisterName(unsigned RegNo);
8382
8483 virtual void EmitFunctionEntryLabel();
8887
8988 #include "MipsGenAsmWriter.inc"
9089
91 //===---------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
9291 //
9392 // Mips Asm Directives
9493 //
117116 // stack pointer subtration, the first register in the mask (RA) will be
118117 // saved at address 48-8=40.
119118 //
120 //===---------------------------------------------------------------------===//
121
122 //===---------------------------------------------------------------------===//
119 //===----------------------------------------------------------------------===//
120
121 //===----------------------------------------------------------------------===//
123122 // Mask directives
124 //===---------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125124
126125 // Create a bitmask with all callee saved registers for CPU or Floating Point
127126 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
173172 O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
174173 }
175174
176 //===---------------------------------------------------------------------===//
175 //===----------------------------------------------------------------------===//
177176 // Frame and Set directives
178 //===---------------------------------------------------------------------===//
177 //===----------------------------------------------------------------------===//
179178
180179 /// Frame Directive
181180 void MipsAsmPrinter::emitFrameDirective() {
237236 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
238237 /// exactly one predecessor and the control transfer mechanism between
239238 /// the predecessor and this block is a fall-through.
240 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock
241 *MBB) const {
239 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
240 MBB) const {
242241 // The predecessor has to be immediately before this block.
243242 const MachineBasicBlock *Pred = *MBB->pred_begin();
244243
391390 // FIXME: Use SwitchSection.
392391
393392 // Tell the assembler which ABI we are using
394 OutStreamer.EmitRawText("\t.section .mdebug." +
395 Twine(getCurrentABIString()));
393 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
396394
397395 // TODO: handle O64 ABI
398396 if (Subtarget->isABI_EABI()) {
None //===- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
0 //===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 // This describes the calling conventions for Mips architecture.
9 //===---------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
1010
1111 /// CCIfSubtarget - Match if the current subtarget has a feature F.
1212 class CCIfSubtarget:
1313 CCIf().", F), A>;
1414
15 //===---------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
1616 // Mips O32 Calling Convention
17 //===---------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
1818
1919 // Only the return rules are defined here for O32. The rules for argument
2020 // passing are defined in MipsISelLowering.cpp.
2929 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
3030 ]>;
3131
32 //===---------------------------------------------------------------------===//
32 //===----------------------------------------------------------------------===//
3333 // Mips EABI Calling Convention
34 //===---------------------------------------------------------------------===//
34 //===----------------------------------------------------------------------===//
3535
3636 def CC_MipsEABI : CallingConv<[
3737 // Promote i8/i16 arguments to i32.
7171 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
7272 ]>;
7373
74 //===---------------------------------------------------------------------===//
74 //===----------------------------------------------------------------------===//
7575 // Mips Calling Convention Dispatch
76 //===---------------------------------------------------------------------===//
76 //===----------------------------------------------------------------------===//
7777
7878 def CC_Mips : CallingConv<[
7979 CCIfSubtarget<"isABI_EABI()", CCDelegateTo>
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // Simple pass to fills delay slots with NOPs.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #define DEBUG_TYPE "delay-slot-filler"
1414
None //===-- MipsExpandPseudo.cpp - Expand pseudo instructions ---------------===//
0 //===-- MipsExpandPseudo.cpp - Expand pseudo instructions ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
9 // This pass expands pseudo instructions into target instructions after
10 // register allocation but before post-RA scheduling.
9 // This pass expands pseudo instructions into target instructions after register
10 // allocation but before post-RA scheduling.
1111 //
12 //===---------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
1313
1414 #define DEBUG_TYPE "mips-expand-pseudo"
1515
8585 void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
8686 MachineBasicBlock::iterator I) {
8787 unsigned DstReg = I->getOperand(0).getReg();
88 unsigned LoReg = I->getOperand(1).getReg();
89 unsigned HiReg = I->getOperand(2).getReg();
88 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
9089 const TargetInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
9190 DebugLoc dl = I->getDebugLoc();
9291 const unsigned* SubReg =
None //=======- MipsFrameLowering.cpp - Mips Frame Information -----*- C++ -*-====//
0 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the Mips implementation of TargetFrameLowering class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #include "MipsFrameLowering.h"
1414 #include "MipsInstrInfo.h"
2626 using namespace llvm;
2727
2828
29 //===---------------------------------------------------------------------===//
29 //===----------------------------------------------------------------------===//
3030 //
3131 // Stack Frame Processing methods
3232 // +----------------------------+
7676 // possible to detect those references and the offsets are adjusted to
7777 // their real location.
7878 //
79 //===---------------------------------------------------------------------===//
79 //===----------------------------------------------------------------------===//
8080
8181 // hasFP - Return true if the specified function should have a dedicated frame
82 // pointer register. This is true if the function has variable sized allocas
83 // or if frame pointer elimination is disabled.
82 // pointer register. This is true if the function has variable sized allocas or
83 // if frame pointer elimination is disabled.
8484 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
8585 const MachineFrameInfo *MFI = MF.getFrameInfo();
8686 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
202202 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
203203 }
204204
205
205206 // expand pair of register and immediate if the immediate doesn't fit in the
206207 // 16-bit offset field.
207208 // e.g.
227228 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
228229 DebugLoc DL = I->getDebugLoc();
229230 int ImmLo = OrigImm & 0xffff;
230 int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
231 int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
231232 ((OrigImm & 0x8000) != 0);
232233
233234 // FIXME: change this when mips goes MC".
None //==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*--===//
0 //==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*---===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 //
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPS_FRAMEINFO_H
1414 #define MIPS_FRAMEINFO_H
None //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips -------===//
0 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file defines an instruction selector for the MIPS target.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #define DEBUG_TYPE "mips-isel"
1414 #include "Mips.h"
3333 #include "llvm/Support/raw_ostream.h"
3434 using namespace llvm;
3535
36 //===---------------------------------------------------------------------===//
36 //===----------------------------------------------------------------------===//
3737 // Instruction Selector Implementation
38 //===---------------------------------------------------------------------===//
39
40 //===---------------------------------------------------------------------===//
38 //===----------------------------------------------------------------------===//
39
40 //===----------------------------------------------------------------------===//
4141 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
4242 // instructions for SelectionDAG operations.
43 //===---------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
4444 namespace {
4545
4646 class MipsDAGToDAGISel : public SelectionDAGISel {
None //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation ----------===//
0 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the interfaces that Mips uses to lower LLVM code into a
1010 // selection DAG.
1111 //
12 //===---------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
1313
1414 #define DEBUG_TYPE "mips-lower"
1515 #include "MipsISelLowering.h"
220220 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
221221 // of the values of MultNode, in which case MultNode will be removed in later
222222 // phases.
223 // If there exist users other than ADDENode or ADDCNode, this function
224 // returns here, which will result in MultNode being mapped to a single MULT
223 // If there exist users other than ADDENode or ADDCNode, this function returns
224 // here, which will result in MultNode being mapped to a single MULT
225225 // instruction node rather than a pair of MULT and MADD instructions being
226226 // produced.
227227 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
294294 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
295295 // of the values of MultNode, in which case MultNode will be removed in later
296296 // phases.
297 // If there exist users other than SUBENode or SUBCNode, this function
298 // returns here, which will result in MultNode being mapped to a single MULT
297 // If there exist users other than SUBENode or SUBCNode, this function returns
298 // here, which will result in MultNode being mapped to a single MULT
299299 // instruction node rather than a pair of MULT and MSUB instructions being
300300 // produced.
301301 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
519519 return SDValue();
520520 }
521521
522 //===---------------------------------------------------------------------===//
522 //===----------------------------------------------------------------------===//
523523 // Lower helper functions
524 //===---------------------------------------------------------------------===//
524 //===----------------------------------------------------------------------===//
525525
526526 // AddLiveIn - This helper function adds the specified physical register to the
527527 // MachineFunction as a live in value. It also creates a corresponding
652652 return BB;
653653 }
654654
655 //===---------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
656656 // Misc Lower Operation implementation
657 //===---------------------------------------------------------------------===//
657 //===----------------------------------------------------------------------===//
658658
659659 SDValue MipsTargetLowering::
660660 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
879879
880880 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
881881 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
882 N->getOffset(),
883 MipsII::MO_ABS_HI);
882 N->getOffset(), MipsII::MO_ABS_HI);
884883 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
885 N->getOffset(),
886 MipsII::MO_ABS_LO);
884 N->getOffset(), MipsII::MO_ABS_LO);
887885 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
888886 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
889887 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
894892 CP, MachinePointerInfo::getConstantPool(),
895893 false, false, 0);
896894 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
897 N->getOffset(),
898 MipsII::MO_ABS_LO);
895 N->getOffset(), MipsII::MO_ABS_LO);
899896 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
900897 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
901898 }
919916 false, false, 0);
920917 }
921918
922 //===---------------------------------------------------------------------===//
919 //===----------------------------------------------------------------------===//
923920 // Calling Convention Implementation
924 //===---------------------------------------------------------------------===//
921 //===----------------------------------------------------------------------===//
925922
926923 #include "MipsGenCallingConv.inc"
927924
928 //===---------------------------------------------------------------------===//
925 //===----------------------------------------------------------------------===//
929926 // TODO: Implement a generic logic using tblgen that can support this.
930927 // Mips O32 ABI rules:
931928 // ---
936933 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
937934 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
938935 // go to stack.
939 //===---------------------------------------------------------------------===//
936 //===----------------------------------------------------------------------===//
940937
941938 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
942939 MVT LocVT, CCValAssign::LocInfo LocInfo,
960957 // This must be the first arg of the call if no regs have been allocated.
961958 // Initialize IntRegUsed in that case.
962959 if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
963 F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] ==
964 Mips::F12 &&
960 F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
965961 F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
966962 IntRegUsed = false;
967963
10741070 return false; // CC must always match
10751071 }
10761072
1077 //===---------------------------------------------------------------------===//
1073 //===----------------------------------------------------------------------===//
10781074 // Call Calling Convention Implementation
1079 //===---------------------------------------------------------------------===//
1075 //===----------------------------------------------------------------------===//
10801076
10811077 /// LowerCall - functions arguments are copied from virtual regs to
10821078 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
11381134 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
11391135 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
11401136 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1141 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl,
1142 MVT::i32, Arg,
1143 DAG.getConstant(0, MVT::i32));
1137 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1138 Arg, DAG.getConstant(0, MVT::i32));
11441139 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
11451140 Arg, DAG.getConstant(1, MVT::i32));
11461141 if (!Subtarget->isLittle())
13471342 return Chain;
13481343 }
13491344
1350 //===---------------------------------------------------------------------===//
1345 //===----------------------------------------------------------------------===//
13511346 // Formal Arguments Calling Convention Implementation
1352 //===---------------------------------------------------------------------===//
1347 //===----------------------------------------------------------------------===//
13531348
13541349 /// LowerFormalArguments - transform physical registers into virtual registers
13551350 /// and generate load operations for arguments places on the stack.
13611356 &Ins,
13621357 DebugLoc dl, SelectionDAG &DAG,
13631358 SmallVectorImpl &InVals)
1364 const {
1359 const {
13651360
13661361 MachineFunction &MF = DAG.getMachineFunction();
13671362 MachineFrameInfo *MFI = MF.getFrameInfo();
14621457 // be used on emitPrologue) to avoid mis-calc of the first stack
14631458 // offset on PEI::calculateFrameObjectOffsets.
14641459 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1465 LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() +
1466 ArgSize;
1460 LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() + ArgSize;
14671461 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
14681462 MipsFI->recordLoadArgsFI(FI, -(4 +
14691463 (FirstStackArgLoc + VA.getLocMemOffset())));
15521546 return Chain;
15531547 }
15541548
1555 //===---------------------------------------------------------------------===//
1549 //===----------------------------------------------------------------------===//
15561550 // Return Value Calling Convention Implementation
1557 //===---------------------------------------------------------------------===//
1551 //===----------------------------------------------------------------------===//
15581552
15591553 SDValue
15601554 MipsTargetLowering::LowerReturn(SDValue Chain,
15791573 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
15801574 for (unsigned i = 0; i != RVLocs.size(); ++i)
15811575 if (RVLocs[i].isRegLoc())
1582 DAG.getMachineFunction().getRegInfo()
1583 .addLiveOut(RVLocs[i].getLocReg());
1576 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
15841577 }
15851578
15861579 SDValue Flag;
16241617 Chain, DAG.getRegister(Mips::RA, MVT::i32));
16251618 }
16261619
1627 //===---------------------------------------------------------------------===//
1620 //===----------------------------------------------------------------------===//
16281621 // Mips Inline Assembly Support
1629 //===---------------------------------------------------------------------===//
1622 //===----------------------------------------------------------------------===//
16301623
16311624 /// getConstraintType - Given a constraint letter, return the type of
16321625 /// constraint it is for this target.
None //===-- MipsISelLowering.h - Mips DAG Lowering Interface -------*- C++ -*-===//
0 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the interfaces that Mips uses to lower LLVM code into a
1010 // selection DAG.
1111 //
12 //===---------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
1313
1414 #ifndef MipsISELLOWERING_H
1515 #define MipsISELLOWERING_H
7070 };
7171 }
7272
73 //===-------------------------------------------------------------------===//
73 //===--------------------------------------------------------------------===//
7474 // TargetLowering Implementation
75 //===-------------------------------------------------------------------===//
75 //===--------------------------------------------------------------------===//
7676
7777 class MipsTargetLowering : public TargetLowering {
7878 public:
147147 // Inline asm support
148148 ConstraintType getConstraintType(const std::string &Constraint) const;
149149
150 /// Examine constraint string and operand type and determine a weight
151 /// value. The operand object must already have been set up with the
152 /// operand type.
150 /// Examine constraint string and operand type and determine a weight value.
151 /// The operand object must already have been set up with the operand type.
153152 ConstraintWeight getSingleConstraintMatchWeight(
154153 AsmOperandInfo &info, const char *constraint) const;
155154
None //===- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
0 //===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the Mips implementation of the TargetInstrInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
12
13 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
12
13 //===----------------------------------------------------------------------===//
1414 // Floating Point Instructions
1515 // ------------------------
1616 // * 64bit fp:
2020 // * 32bit fp:
2121 // - 16 even 32-bit registers - single and double (aliased)
2222 // - 32 32-bit registers (within single-only mode)
23 //===---------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
2424
2525 // Floating Point Compare and Branch
2626 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
5050 let PrintMethod = "printFCCOperand" in
5151 def condcode : Operand;
5252
53 //===---------------------------------------------------------------------===//
53 //===----------------------------------------------------------------------===//
5454 // Feature predicates.
55 //===---------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
5656
5757 def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
5858 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
5959 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
6060 def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
6161
62 //===---------------------------------------------------------------------===//
62 //===----------------------------------------------------------------------===//
6363 // Instruction Class Templates
6464 //
6565 // A set of multiclasses is used to address the register usage.
7171 // D64 - double precision in 32 64bit fp registers (In64BitMode)
7272 //
7373 // Only S32 and D32 are supported right now.
74 //===---------------------------------------------------------------------===//
74 //===----------------------------------------------------------------------===//
7575
7676 multiclass FFR1_1 funct, string asmstr>
7777 {
9090
9191 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
9292 !strconcat(asmstr, ".d $fd, $fs"),
93 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>,
94 Requires<[In32BitMode]>;
93 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
9594 }
9695
9796 class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc,
113112 Requires<[In32BitMode]>;
114113 }
115114
116 //===---------------------------------------------------------------------===//
115 //===----------------------------------------------------------------------===//
117116 // Floating Point Instructions
118 //===---------------------------------------------------------------------===//
117 //===----------------------------------------------------------------------===//
119118
120119 let ft = 0 in {
121120 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
199198 // LWC1 and SWC1 can always be emitted with odd registers.
200199 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
201200 [(set FGR32:$ft, (load addr:$addr))]>;
202 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr),
203 "swc1 $ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
201 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
202 [(store FGR32:$ft, addr:$addr)]>;
204203
205204 /// Floating-point Aritmetic
206205 defm FADD : FFR1_4<0x10, "add", fadd>;
208207 defm FMUL : FFR1_4<0x02, "mul", fmul>;
209208 defm FSUB : FFR1_4<0x01, "sub", fsub>;
210209
211 //===---------------------------------------------------------------------===//
210 //===----------------------------------------------------------------------===//
212211 // Floating Point Branch Codes
213 //===---------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
214213 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
215214 // They must be kept in synch.
216215 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
229228 def BC1FL : FBRANCH;
230229 def BC1TL : FBRANCH;
231230
232 //===---------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
233232 // Floating Point Flag Conditions
234 //===---------------------------------------------------------------------===//
233 //===----------------------------------------------------------------------===//
235234 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
236235 // They must be kept in synch.
237236 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
265264
266265
267266 // Conditional moves:
268 // These instructions are expanded in
267 // These instructions are expanded in
269268 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
270269 // conditional move instructions.
271270 // flag:int, data:float
316315 def MOVF_D : CondMovFPFP;
317316 }
318317
319 //===---------------------------------------------------------------------===//
318 //===----------------------------------------------------------------------===//
320319 // Floating Point Pseudo-Instructions
321 //===---------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
322321 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
323322 "# MOVCCRToCCR", []>;
324323
339338 [(set CPURegs:$dst,
340339 (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
341340
342 //===---------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343342 // Floating Point Patterns
344 //===---------------------------------------------------------------------===//
343 //===----------------------------------------------------------------------===//
345344 def fpimm0 : PatLeaf<(fpimm), [{
346345 return N->isExactlyValue(+0.0);
347346 }]>;
None //===- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
0 //===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
8
9 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
1010 // Describe MIPS instructions format
1111 //
1212 // CPU INSTRUCTION FORMATS
1818 // shamt - only used on shift instructions, contains the shift amount.
1919 // funct - combined with opcode field give us an operation code.
2020 //
21 //===---------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
2222
2323 // Generic Mips Format
2424 class MipsInst pattern,
4545 class MipsPseudo pattern>:
4646 MipsInst;
4747
48 //===---------------------------------------------------------------------===//
48 //===----------------------------------------------------------------------===//
4949 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
50 //===---------------------------------------------------------------------===//
50 //===----------------------------------------------------------------------===//
5151
5252 class FR op, bits<6> _funct, dag outs, dag ins, string asmstr,
5353 list pattern, InstrItinClass itin>:
6969 let Inst{5-0} = funct;
7070 }
7171
72 //===---------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
7373 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
74 //===---------------------------------------------------------------------===//
74 //===----------------------------------------------------------------------===//
7575
7676 class FI op, dag outs, dag ins, string asmstr, list pattern,
7777 InstrItinClass itin>: MipsInst
8787 let Inst{15-0} = imm16;
8888 }
8989
90 //===---------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
9191 // Format J instruction class in Mips : <|opcode|address|>
92 //===---------------------------------------------------------------------===//
92 //===----------------------------------------------------------------------===//
9393
9494 class FJ op, dag outs, dag ins, string asmstr, list pattern,
9595 InstrItinClass itin>: MipsInst
101101 let Inst{25-0} = addr;
102102 }
103103
104 //===---------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
105105 //
106106 // FLOATING POINT INSTRUCTION FORMATS
107107 //
112112 // fmt - double or single precision.
113113 // funct - combined with opcode field give us an operation code.
114114 //
115 //===---------------------------------------------------------------------===//
116
117 //===---------------------------------------------------------------------===//
115 //===----------------------------------------------------------------------===//
116
117 //===----------------------------------------------------------------------===//
118118 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
119 //===---------------------------------------------------------------------===//
119 //===----------------------------------------------------------------------===//
120120
121121 class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
122122 string asmstr, list pattern> :
139139 let Inst{5-0} = funct;
140140 }
141141
142 //===---------------------------------------------------------------------===//
142 //===----------------------------------------------------------------------===//
143143 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
144 //===---------------------------------------------------------------------===//
144 //===----------------------------------------------------------------------===//
145145
146146 class FFI op, dag outs, dag ins, string asmstr, list pattern>:
147147 MipsInst
157157 let Inst{15-0} = imm16;
158158 }
159159
160 //===---------------------------------------------------------------------===//
160 //===----------------------------------------------------------------------===//
161161 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
162 //===---------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163163
164164 class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> :
165165 MipsInst
None //===- MipsInstrInfo.cpp - Mips Instruction Information --------*- C++ -*-===//
0 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the Mips implementation of the TargetInstrInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #include "MipsInstrInfo.h"
1414 #include "MipsTargetMachine.h"
160160
161161 if (RC == Mips::CPURegsRegisterClass)
162162 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
163 .addImm(0).addFrameIndex(FI);
163 .addImm(0).addFrameIndex(FI);
164164 else if (RC == Mips::FGR32RegisterClass)
165 BuildMI(MBB, I, DL, get(Mips::SWC1))
166 .addReg(SrcReg, getKillRegState(isKill)).addImm(0).addFrameIndex(FI);
165 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
166 .addImm(0).addFrameIndex(FI);
167167 else if (RC == Mips::AFGR64RegisterClass) {
168168 if (!TM.getSubtarget().isMips1()) {
169169 BuildMI(MBB, I, DL, get(Mips::SDC1))
199199 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
200200 else if (RC == Mips::AFGR64RegisterClass) {
201201 if (!TM.getSubtarget().isMips1()) {
202 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg)
203 .addImm(0).addFrameIndex(FI);
202 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
204203 } else {
205204 const TargetRegisterInfo *TRI =
206205 MBB.getParent()->getTarget().getRegisterInfo();
214213 llvm_unreachable("Register class not handled!");
215214 }
216215
217 //===---------------------------------------------------------------------===//
216 //===----------------------------------------------------------------------===//
218217 // Branch Analysis
219 //===---------------------------------------------------------------------===//
218 //===----------------------------------------------------------------------===//
220219
221220 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
222221 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
None //===- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
0 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the Mips implementation of the TargetInstrInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPSINSTRUCTIONINFO_H
1414 #define MIPSINSTRUCTIONINFO_H
123123 namespace MipsII {
124124 /// Target Operand Flag enum.
125125 enum TOF {
126 //===-----------------------------------------------------------------===//
126 //===------------------------------------------------------------------===//
127127 // Mips Specific MachineOperand flags.
128128
129129 MO_NO_FLAG,
199199 bool KillSrc) const;
200200 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
201201 MachineBasicBlock::iterator MBBI,
202 unsigned SrcReg, bool isKill,
203 int FrameIndex,
202 unsigned SrcReg, bool isKill, int FrameIndex,
204203 const TargetRegisterClass *RC,
205204 const TargetRegisterInfo *TRI) const;
206205
None //===- MipsInstrInfo.td - Mips Register defs --------------*- tablegen -*-===//
0 //===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
8
9 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
1010 // Instruction format superclass
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 include "MipsInstrFormats.td"
1414
15 //===---------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
1616 // Mips profiles and nodes
17 //===---------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
1818
1919 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
2020 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
7070 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
7171 [SDNPOutGlue]>;
7272
73 //===---------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
7474 // Mips Instruction Predicate Definitions.
75 //===---------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
7676 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
7777 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
7878 def HasSwap : Predicate<"Subtarget.hasSwap()">;
8080 def IsMips32 : Predicate<"Subtarget.isMips32()">;
8181 def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
8282
83 //===---------------------------------------------------------------------===//
83 //===----------------------------------------------------------------------===//
8484 // Mips Operand, Complex Patterns and Transformations Definitions.
85 //===---------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
8686
8787 // Instruction operand types
8888 def brtarget : Operand;
135135 // since load and store instructions from stack used it.
136136 def addr : ComplexPattern;
137137
138 //===---------------------------------------------------------------------===//
138 //===----------------------------------------------------------------------===//
139139 // Instructions specific format
140 //===---------------------------------------------------------------------===//
140 //===----------------------------------------------------------------------===//
141141
142142 // Arithmetic 3 register operands
143143 let isCommutable = 1 in
337337 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
338338 [], NoItinerary>;
339339
340 //===---------------------------------------------------------------------===//
340 //===----------------------------------------------------------------------===//
341341 // Pseudo instructions
342 //===---------------------------------------------------------------------===//
342 //===----------------------------------------------------------------------===//
343343
344344 // As stack alignment is always done with addiu, we need a 16-bit immediate
345345 let Defs = [SP], Uses = [SP] in {
368368 // are used, we have the same behavior, but get also a bunch of warnings
369369 // from the assembler.
370370 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
371 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc),
372 ".cprestore\t$loc\n", []>;
373
374 //===---------------------------------------------------------------------===//
371 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
372
373 //===----------------------------------------------------------------------===//
375374 // Instruction definition
376 //===---------------------------------------------------------------------===//
377
378 //===---------------------------------------------------------------------===//
375 //===----------------------------------------------------------------------===//
376
377 //===----------------------------------------------------------------------===//
379378 // MipsI Instructions
380 //===---------------------------------------------------------------------===//
379 //===----------------------------------------------------------------------===//
381380
382381 /// Arithmetic Instructions (ALU Immediate)
383382 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
525524 // it is a real instruction.
526525 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>;
527526
528 //===---------------------------------------------------------------------===//
527 //===----------------------------------------------------------------------===//
529528 // Arbitrary patterns that map to one or more instructions
530 //===---------------------------------------------------------------------===//
529 //===----------------------------------------------------------------------===//
531530
532531 // Small immediates
533532 def : Pat<(i32 immSExt16:$in),
676675 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
677676 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
678677
679 //===---------------------------------------------------------------------===//
678 //===----------------------------------------------------------------------===//
680679 // Floating Point Support
681 //===---------------------------------------------------------------------===//
680 //===----------------------------------------------------------------------===//
682681
683682 include "MipsInstrFPU.td"
683
None //===-- MipsMCAsmInfo.cpp - Mips asm properties --------------------------===//
0 //===-- MipsMCAsmInfo.cpp - Mips asm properties ---------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the declarations of the MipsMCAsmInfo properties.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #include "MipsMCAsmInfo.h"
1414 using namespace llvm;
None //=====-- MipsMCAsmInfo.h - Mips asm properties --------------*- C++ -*--====//
0 //=====-- MipsMCAsmInfo.h - Mips asm properties ---------------*- C++ -*--====//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the declaration of the MipsMCAsmInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPSTARGETASMINFO_H
1414 #define MIPSTARGETASMINFO_H
None //===-- MipsMachineFunctionInfo.h - Private data used for Mips ---*- C++ -*-=//
0 //===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file declares the Mips specific subclass of MachineFunctionInfo.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPS_MACHINE_FUNCTION_INFO_H
1414 #define MIPS_MACHINE_FUNCTION_INFO_H
None //===- MipsRegisterInfo.cpp - MIPS Register Information -== ----*- C++ -*-===//
0 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the MIPS implementation of the TargetRegisterInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #define DEBUG_TYPE "mips-reg-info"
1414
8787
8888 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
8989
90 //===---------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
9191 // Callee Saved Registers methods
92 //===---------------------------------------------------------------------===//
92 //===----------------------------------------------------------------------===//
9393
9494 /// Mips Callee Saved Registers
9595 const unsigned* MipsRegisterInfo::
None //===- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
0 //===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the Mips implementation of the TargetRegisterInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPSREGISTERINFO_H
1414 #define MIPSREGISTERINFO_H
None //===- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
0 //===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
8
9 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
1010 // Declarations that describe the MIPS register file
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 // We have banks of 32 registers each.
1414 class MipsReg : Register {
4343 let SubRegIndices = [sub_fpeven, sub_fpodd];
4444 }
4545
46 //===---------------------------------------------------------------------===//
46 //===----------------------------------------------------------------------===//
4747 // Registers
48 //===---------------------------------------------------------------------===//
48 //===----------------------------------------------------------------------===//
4949
5050 let Namespace = "Mips" in {
5151
144144 def FCR31 : Register<"31">;
145145 }
146146
147 //===---------------------------------------------------------------------===//
147 //===----------------------------------------------------------------------===//
148148 // Register Classes
149 //===---------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
150150
151151 def CPURegs : RegisterClass<"Mips", [i32], 32,
152152 // Return Values and Arguments
None //===- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
0 //===- MipsSchedule.td - Mips Scheduling Definitions -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88
9 //===---------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
1010 // Functional units across Mips chips sets. Based on GCC/Mips backend files.
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212 def ALU : FuncUnit;
1313 def IMULDIV : FuncUnit;
1414
15 //===---------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
1616 // Instruction Itinerary classes used for Mips
17 //===---------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
1818 def IIAlu : InstrItinClass;
1919 def IILoad : InstrItinClass;
2020 def IIStore : InstrItinClass;
3636 def IIFrecipFsqrtStep : InstrItinClass;
3737 def IIPseudo : InstrItinClass;
3838
39 //===---------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
4040 // Mips Generic instruction itineraries.
41 //===---------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
4242 def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
4343 InstrItinData]>,
4444 InstrItinData]>,
None //===-- MipsSelectionDAGInfo.cpp - Mips SelectionDAG Info ----------------===//
0 //===-- MipsSelectionDAGInfo.cpp - Mips SelectionDAG Info -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file implements the MipsSelectionDAGInfo class.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #define DEBUG_TYPE "mips-selectiondag-info"
1414 #include "MipsTargetMachine.h"
None //===-- MipsSelectionDAGInfo.h - Mips SelectionDAG Info --------*- C++ -*-===//
0 //===-- MipsSelectionDAGInfo.h - Mips SelectionDAG Info ---------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the Mips subclass for TargetSelectionDAGInfo.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPSSELECTIONDAGINFO_H
1414 #define MIPSSELECTIONDAGINFO_H
None //===- MipsSubtarget.cpp - Mips Subtarget Information ----------*- C++ -*-===//
0 //===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file implements the Mips specific subclass of TargetSubtarget.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #include "MipsSubtarget.h"
1414 #include "Mips.h"
None //=====-- MipsSubtarget.h - Define Subtarget for the Mips ----*- C++ -*--====//
0 //=====-- MipsSubtarget.h - Define Subtarget for the Mips -----*- C++ -*--====//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file declares the Mips specific subclass of TargetSubtarget.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPSSUBTARGET_H
1414 #define MIPSSUBTARGET_H
None //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips ------------===//
0 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // Implements the info about Mips target spec.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #include "Mips.h"
1414 #include "MipsMCAsmInfo.h"
3333 // an easier handling.
3434 // Using CodeModel::Large enables different CALL behavior.
3535 MipsTargetMachine::
36 MipsTargetMachine(const Target &T, const std::string &TT,
37 const std::string &FS, bool isLittle=false) :
36 MipsTargetMachine(const Target &T, const std::string &TT, const std::string &FS,
37 bool isLittle=false):
3838 LLVMTargetMachine(T, TT),
3939 Subtarget(TT, FS, isLittle),
4040 DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") :
None //===-- MipsTargetMachine.h - Define TargetMachine for Mips -00-*- C++ -*-===//
0 //===-- MipsTargetMachine.h - Define TargetMachine for Mips -00--*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file declares the Mips specific subclass of TargetMachine.
1010 //
11 //===---------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 #ifndef MIPSTARGETMACHINE_H
1414 #define MIPSTARGETMACHINE_H
None //===-- MipsTargetObjectFile.cpp - Mips object files ---------------------===//
0 //===-- MipsTargetObjectFile.cpp - Mips object files ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88
99 #include "MipsTargetObjectFile.h"
1010 #include "MipsSubtarget.h"
4646 }
4747
4848 bool MipsTargetObjectFile::IsGlobalInSmallSection(const GlobalValue *GV,
49 const TargetMachine &TM)
50 const {
49 const TargetMachine &TM) const {
5150 if (GV->isDeclaration() || GV->hasAvailableExternallyLinkage())
5251 return false;
5352
9897 return SmallDataSection;
9998
10099 // Otherwise, we work the same as ELF.
101 return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang,
102 TM);
100 return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang,TM);
103101 }
None //===-- llvm/Target/MipsTargetObjectFile.h - Mips Object Info --*- C++ -*-===//
0 //===-- llvm/Target/MipsTargetObjectFile.h - Mips Object Info ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88
99 #ifndef LLVM_TARGET_MIPS_TARGETOBJECTFILE_H
1010 #define LLVM_TARGET_MIPS_TARGETOBJECTFILE_H
2424 /// IsGlobalInSmallSection - Return true if this global address should be
2525 /// placed into small data/bss section.
2626 bool IsGlobalInSmallSection(const GlobalValue *GV,
27 const TargetMachine &TM,
28 SectionKind Kind) const;
27 const TargetMachine &TM, SectionKind Kind)const;
2928 bool IsGlobalInSmallSection(const GlobalValue *GV,
3029 const TargetMachine &TM) const;
3130
None ##===- lib/Target/Mips/TargetInfo/Makefile ----------------*- Makefile -*-===##
0 ##===- lib/Target/Mips/TargetInfo/Makefile -----------------*- Makefile -*-===##
11 #
22 # The LLVM Compiler Infrastructure
33 #
44 # This file is distributed under the University of Illinois Open Source
55 # License. See LICENSE.TXT for details.
66 #
7 ##===---------------------------------------------------------------------===##
7 ##===----------------------------------------------------------------------===##
88 LEVEL = ../../../..
99 LIBRARYNAME = LLVMMipsInfo
1010
None //===-- MipsTargetInfo.cpp - Mips Target Implementation ------------------===//
0 //===-- MipsTargetInfo.cpp - Mips Target Implementation -------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===---------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88
99 #include "Mips.h"
1010 #include "llvm/Module.h"