llvm.org GIT mirror llvm / 452fd43
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320795 91177308-0d34-0410-b5e6-96231b3b80d8 Roger Ferrer Ibanez 2 years ago
4 changed file(s) with 411 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc -mtriple=arm-eabi < %s | FileCheck %s
11
22 define i1 @t1(i64 %x) {
3 ; CHECK-LABEL: t1:
4 ; CHECK: lsr r0, r1, #31
35 %B = icmp slt i64 %x, 0
46 ret i1 %B
57 }
68
79 define i1 @t2(i64 %x) {
10 ; CHECK-LABEL: t2:
11 ; CHECK: mov r0, #0
12 ; CHECK: cmp r1, #0
13 ; CHECK: moveq r0, #1
814 %tmp = icmp ult i64 %x, 4294967296
915 ret i1 %tmp
1016 }
1117
1218 define i1 @t3(i32 %x) {
19 ; CHECK-LABEL: t3:
20 ; CHECK: mov r0, #0
1321 %tmp = icmp ugt i32 %x, -1
1422 ret i1 %tmp
1523 }
1624
17 ; CHECK: cmp
1825 ; CHECK-NOT: cmp
1926
22 ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
33 ; RUN: | FileCheck %s --check-prefix=ARMT2
44
5 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -o - \
6 ; RUN: | FileCheck %s --check-prefix=THUMB1
7
58 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
69 ; RUN: | FileCheck %s --check-prefix=THUMB2
10
11 ; RUN: llc -mtriple=thumbv8m.base-eabi %s -o - \
12 ; RUN: | FileCheck %s --check-prefix=V8MBASE
713
814 define i32 @t1(i32 %c) nounwind readnone {
915 entry:
1622 ; ARMT2: movw [[R:r[0-1]]], #357
1723 ; ARMT2: movwgt [[R]], #123
1824
25 ; THUMB1-LABEL: t1:
26 ; THUMB1: mov r1, r0
27 ; THUMB1: movs r2, #255
28 ; THUMB1: adds r2, #102
29 ; THUMB1: movs r0, #123
30 ; THUMB1: cmp r1, #1
31 ; THUMB1: bgt
32
1933 ; THUMB2-LABEL: t1:
2034 ; THUMB2: movw [[R:r[0-1]]], #357
2135 ; THUMB2: movgt [[R]], #123
3650 ; ARMT2: mov [[R:r[0-1]]], #123
3751 ; ARMT2: movwgt [[R]], #357
3852
53 ; THUMB1-LABEL: t2:
54 ; THUMB1: cmp r{{[0-9]+}}, #1
55 ; THUMB1: bgt
56
3957 ; THUMB2-LABEL: t2:
4058 ; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
4159 ; THUMB2: movwgt [[R]], #357
5472 ; ARMT2-LABEL: t3:
5573 ; ARMT2: mov [[R:r[0-1]]], #0
5674 ; ARMT2: movweq [[R]], #1
75
76 ; THUMB1-LABEL: t3:
77 ; THUMB1: mov r1, r0
78 ; THUMB1: movs r0, #1
79 ; THUMB1: movs r2, #0
80 ; THUMB1: cmp r1, #160
81 ; THUMB1: beq
5782
5883 ; THUMB2-LABEL: t3:
5984 ; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0
7398 ; ARMT2: movwlt [[R0:r[0-9]+]], #65365
7499 ; ARMT2: movtlt [[R0]], #65365
75100
101 ; THUMB1-LABEL: t4:
102 ; THUMB1: cmp r{{[0-9]+}}, r{{[0-9]+}}
103 ; THUMB1: b{{lt|ge}}
104
76105 ; THUMB2-LABEL: t4:
77106 ; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
78107 %0 = icmp slt i32 %a, %b
88117 ; ARM: cmp r0, #1
89118 ; ARM-NOT: mov
90119 ; ARM: movne r0, #0
120
121 ; THUMB1-LABEL: t5:
122 ; THUMB1: mov r1, r0
123 ; THUMB1: movs r0, #0
124 ; THUMB1: cmp r1, #1
125 ; THUMB1: bne
91126
92127 ; THUMB2-LABEL: t5:
93128 ; THUMB2-NOT: mov
106141 ; ARM: cmp r0, #0
107142 ; ARM: movne r0, #1
108143
144 ; THUMB1-LABEL: t6:
145 ; THUMB1: cmp r{{[0-9]+}}, #0
146 ; THUMB1: bne
147
109148 ; THUMB2-LABEL: t6:
110149 ; THUMB2-NOT: mov
111150 ; THUMB2: cmp r0, #0
115154 %lnot.ext = zext i1 %tobool to i32
116155 ret i32 %lnot.ext
117156 }
157
158 define i32 @t7(i32 %a, i32 %b) nounwind readnone {
159 entry:
160 ; ARM-LABEL: t7:
161 ; ARM: mov r2, #0
162 ; ARM: cmp r0, r1
163 ; ARM: movne r2, #1
164 ; ARM: lsl r0, r2, #2
165
166 ; ARMT2-LABEL: t7:
167 ; ARMT2: mov r2, #0
168 ; ARMT2: cmp r0, r1
169 ; ARMT2: movwne r2, #1
170 ; ARMT2: lsl r0, r2, #2
171
172 ; THUMB1-LABEL: t7:
173 ; THUMB1: movs r2, #1
174 ; THUMB1: movs r3, #0
175 ; THUMB1: cmp r0, r1
176 ; THUMB1: bne .LBB6_2
177 ; THUMB1: mov r2, r3
178 ; THUMB1: .LBB6_2:
179 ; THUMB1: lsls r0, r2, #2
180
181 ; THUMB2-LABEL: t7:
182 ; THUMB2: movs r2, #0
183 ; THUMB2: cmp r0, r1
184 ; THUMB2: it ne
185 ; THUMB2: movne r2, #1
186 ; THUMB2: lsls r0, r2, #2
187 %0 = icmp ne i32 %a, %b
188 %1 = select i1 %0, i32 4, i32 0
189 ret i32 %1
190 }
191
192 define void @t8(i32 %a) {
193 entry:
194
195 ; ARM scheduler emits icmp/zext before both calls, so isn't relevant
196
197 ; ARMT2-LABEL: t8:
198 ; ARMT2: mov r1, r0
199 ; ARMT2: mov r0, #9
200 ; ARMT2: mov r4, #0
201 ; ARMT2: cmp r1, #5
202 ; ARMT2: movweq r4, #1
203 ; ARMT2: bl t7
204
205 ; THUMB1-LABEL: t8:
206 ; THUMB1: mov r1, r0
207 ; THUMB1: movs r4, #1
208 ; THUMB1: movs r0, #0
209 ; THUMB1: cmp r1, #5
210 ; THUMB1: beq .LBB7_2
211 ; THUMB1: mov r4, r0
212
213 ; THUMB2-LABEL: t8:
214 ; THUMB2: mov r1, r0
215 ; THUMB2: movs r4, #0
216 ; THUMB2: cmp r1, #5
217 ; THUMB2: it eq
218 ; THUMB2: moveq r4, #1
219 %cmp = icmp eq i32 %a, 5
220 %conv = zext i1 %cmp to i32
221 %call = tail call i32 @t7(i32 9, i32 %a)
222 tail call i32 @t7(i32 %conv, i32 %call)
223 ret void
224 }
225
226 define void @t9(i8* %a, i8 %b) {
227 entry:
228
229 ; ARM scheduler emits icmp/zext before both calls, so isn't relevant
230
231 ; ARMT2-LABEL: t9:
232 ; ARMT2: cmp r4, r4
233 ; ARMT2: movweq r0, #1
234
235 ; THUMB1-LABEL: t9:
236 ; THUMB1: cmp r4, r4
237 ; THUMB1: beq .LBB8_2
238 ; THUMB1: mov r0, r1
239
240 ; THUMB2-LABEL: t9:
241 ; THUMB2: cmp r4, r4
242 ; THUMB2: it eq
243 ; THUMB2: moveq r0, #1
244
245 %0 = load i8, i8* %a
246 %conv = sext i8 %0 to i32
247 %conv119 = zext i8 %0 to i32
248 %conv522 = and i32 %conv, 255
249 %cmp723 = icmp eq i32 %conv522, %conv119
250 tail call void @f(i1 zeroext %cmp723)
251 br i1 %cmp723, label %while.body, label %while.end
252
253 while.body: ; preds = %entry, %while.body
254 %ref.025 = phi i8 [ %inc9, %while.body ], [ %0, %entry ]
255 %in.024 = phi i32 [ %inc, %while.body ], [ %conv, %entry ]
256 %inc = add i32 %in.024, 1
257 %inc9 = add i8 %ref.025, 1
258 %conv1 = zext i8 %inc9 to i32
259 %cmp = icmp slt i32 %conv1, %conv119
260 %conv5 = and i32 %inc, 255
261 br i1 %cmp, label %while.body, label %while.end
262
263 while.end:
264 ret void
265 }
266
267 declare void @f(i1 zeroext)
268
269
270 define i1 @t10() {
271 entry:
272 %q = alloca i32
273 %p = alloca i32
274 store i32 -3, i32* %q
275 store i32 -8, i32* %p
276 %0 = load i32, i32* %q
277 %1 = load i32, i32* %p
278 %div = sdiv i32 %0, %1
279 %mul = mul nsw i32 %div, %1
280 %rem = srem i32 %0, %1
281 %add = add nsw i32 %mul, %rem
282 %cmp = icmp eq i32 %add, %0
283 ret i1 %cmp
284
285 ; ARM-LABEL: t10:
286 ; ARM: mov r0, #0
287 ; ARM: cmn r1, #3
288 ; ARM: moveq r0, #1
289
290 ; ARMT2-LABEL: t10:
291 ; ARMT2: mov r0, #0
292 ; ARMT2: cmn r1, #3
293 ; ARMT2: movweq r0, #1
294
295 ; THUMB1-LABEL: t10:
296 ; THUMB1: movs r0, #1
297 ; THUMB1: movs r1, #0
298 ; THUMB1: cmp r2, r5
299 ; THUMB1: beq .LBB9_2
300 ; THUMB1: mov r0, r1
301
302 ; THUMB2-LABEL: t10:
303 ; THUMB2: adds r0, #3
304 ; THUMB2: mov.w r0, #0
305 ; THUMB2: it eq
306 ; THUMB2: moveq r0, #1
307
308 ; V8MBASE-LABEL: t10:
309 ; V8MBASE-NOT: movs r0, #0
310 ; V8MBASE: movs r0, #7
311 }
312
313 define i1 @t11() {
314 entry:
315 %bit = alloca i32
316 %load = load i32, i32* %bit
317 %clear = and i32 %load, -4096
318 %set = or i32 %clear, 33
319 store i32 %set, i32* %bit
320 %load1 = load i32, i32* %bit
321 %clear2 = and i32 %load1, -33550337
322 %set3 = or i32 %clear2, 40960
323 %clear5 = and i32 %set3, 4095
324 %rem = srem i32 %clear5, 10
325 %clear9 = and i32 %set3, -4096
326 %set10 = or i32 %clear9, %rem
327 store i32 %set10, i32* %bit
328 %clear12 = and i32 %set10, 4095
329 %cmp = icmp eq i32 %clear12, 3
330 ret i1 %cmp
331
332 ; ARM-LABEL: t11:
333 ; ARM: mov r0, #0
334 ; ARM: cmp r1, #3
335 ; ARM: moveq r0, #1
336
337 ; ARMT2-LABEL: t11:
338 ; ARMT2: mov r0, #0
339 ; ARMT2: cmp r1, #3
340 ; ARMT2: movweq r0, #1
341
342 ; THUMB1-LABEL: t11:
343 ; THUMB1-NOT: movs r0, #0
344 ; THUMB1: movs r0, #5
345
346 ; THUMB2-LABEL: t11:
347 ; THUMB2: movs r0, #0
348 ; THUMB2: cmp r1, #3
349 ; THUMB2: it eq
350 ; THUMB2: moveq r0, #1
351
352 ; V8MBASE-LABEL: t11:
353 ; V8MBASE-NOT: movs r0, #0
354 ; V8MBASE: movw r0, #40960
355 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s
2
3 define i32 @test1a(i32 %a, i32 %b) {
4 ; CHECK-LABEL: test1a:
5 ; CHECK: @ %bb.0: @ %entry
6 ; CHECK-NEXT: mov r2, r0
7 ; CHECK-NEXT: movs r0, #1
8 ; CHECK-NEXT: movs r3, #0
9 ; CHECK-NEXT: cmp r2, r1
10 ; CHECK-NEXT: bne .LBB0_2
11 ; CHECK-NEXT: @ %bb.1: @ %entry
12 ; CHECK-NEXT: mov r0, r3
13 ; CHECK-NEXT: .LBB0_2: @ %entry
14 ; CHECK-NEXT: bx lr
15 entry:
16 %cmp = icmp ne i32 %a, %b
17 %cond = zext i1 %cmp to i32
18 ret i32 %cond
19 }
20
21 define i32 @test1b(i32 %a, i32 %b) {
22 ; CHECK-LABEL: test1b:
23 ; CHECK: @ %bb.0: @ %entry
24 ; CHECK-NEXT: mov r2, r0
25 ; CHECK-NEXT: movs r0, #1
26 ; CHECK-NEXT: movs r3, #0
27 ; CHECK-NEXT: cmp r2, r1
28 ; CHECK-NEXT: beq .LBB1_2
29 ; CHECK-NEXT: @ %bb.1: @ %entry
30 ; CHECK-NEXT: mov r0, r3
31 ; CHECK-NEXT: .LBB1_2: @ %entry
32 ; CHECK-NEXT: bx lr
33 entry:
34 %cmp = icmp eq i32 %a, %b
35 %cond = zext i1 %cmp to i32
36 ret i32 %cond
37 }
38
39 define i32 @test2a(i32 %a, i32 %b) {
40 ; CHECK-LABEL: test2a:
41 ; CHECK: @ %bb.0: @ %entry
42 ; CHECK-NEXT: mov r2, r0
43 ; CHECK-NEXT: movs r0, #1
44 ; CHECK-NEXT: movs r3, #0
45 ; CHECK-NEXT: cmp r2, r1
46 ; CHECK-NEXT: beq .LBB2_2
47 ; CHECK-NEXT: @ %bb.1: @ %entry
48 ; CHECK-NEXT: mov r0, r3
49 ; CHECK-NEXT: .LBB2_2: @ %entry
50 ; CHECK-NEXT: bx lr
51 entry:
52 %cmp = icmp eq i32 %a, %b
53 %cond = zext i1 %cmp to i32
54 ret i32 %cond
55 }
56
57 define i32 @test2b(i32 %a, i32 %b) {
58 ; CHECK-LABEL: test2b:
59 ; CHECK: @ %bb.0: @ %entry
60 ; CHECK-NEXT: mov r2, r0
61 ; CHECK-NEXT: movs r0, #1
62 ; CHECK-NEXT: movs r3, #0
63 ; CHECK-NEXT: cmp r2, r1
64 ; CHECK-NEXT: bne .LBB3_2
65 ; CHECK-NEXT: @ %bb.1: @ %entry
66 ; CHECK-NEXT: mov r0, r3
67 ; CHECK-NEXT: .LBB3_2: @ %entry
68 ; CHECK-NEXT: bx lr
69 entry:
70 %cmp = icmp ne i32 %a, %b
71 %cond = zext i1 %cmp to i32
72 ret i32 %cond
73 }
74
75 define i32 @test3a(i32 %a, i32 %b) {
76 ; CHECK-LABEL: test3a:
77 ; CHECK: @ %bb.0: @ %entry
78 ; CHECK-NEXT: mov r2, r0
79 ; CHECK-NEXT: movs r0, #0
80 ; CHECK-NEXT: movs r3, #4
81 ; CHECK-NEXT: cmp r2, r1
82 ; CHECK-NEXT: beq .LBB4_2
83 ; CHECK-NEXT: @ %bb.1: @ %entry
84 ; CHECK-NEXT: mov r0, r3
85 ; CHECK-NEXT: .LBB4_2: @ %entry
86 ; CHECK-NEXT: bx lr
87 entry:
88 %cmp = icmp eq i32 %a, %b
89 %cond = select i1 %cmp, i32 0, i32 4
90 ret i32 %cond
91 }
92
93 define i32 @test3b(i32 %a, i32 %b) {
94 ; CHECK-LABEL: test3b:
95 ; CHECK: @ %bb.0: @ %entry
96 ; CHECK-NEXT: movs r2, #1
97 ; CHECK-NEXT: movs r3, #0
98 ; CHECK-NEXT: cmp r0, r1
99 ; CHECK-NEXT: beq .LBB5_2
100 ; CHECK-NEXT: @ %bb.1: @ %entry
101 ; CHECK-NEXT: mov r2, r3
102 ; CHECK-NEXT: .LBB5_2: @ %entry
103 ; CHECK-NEXT: lsls r0, r2, #2
104 ; CHECK-NEXT: bx lr
105 entry:
106 %cmp = icmp eq i32 %a, %b
107 %cond = select i1 %cmp, i32 4, i32 0
108 ret i32 %cond
109 }
110
111 ; FIXME: This one hasn't changed actually
112 ; but could look like test3b
113 define i32 @test4a(i32 %a, i32 %b) {
114 ; CHECK-LABEL: test4a:
115 ; CHECK: @ %bb.0: @ %entry
116 ; CHECK-NEXT: mov r2, r0
117 ; CHECK-NEXT: movs r0, #0
118 ; CHECK-NEXT: movs r3, #4
119 ; CHECK-NEXT: cmp r2, r1
120 ; CHECK-NEXT: bne .LBB6_2
121 ; CHECK-NEXT: @ %bb.1: @ %entry
122 ; CHECK-NEXT: mov r0, r3
123 ; CHECK-NEXT: .LBB6_2: @ %entry
124 ; CHECK-NEXT: bx lr
125 entry:
126 %cmp = icmp ne i32 %a, %b
127 %cond = select i1 %cmp, i32 0, i32 4
128 ret i32 %cond
129 }
130
131 define i32 @test4b(i32 %a, i32 %b) {
132 ; CHECK-LABEL: test4b:
133 ; CHECK: @ %bb.0: @ %entry
134 ; CHECK-NEXT: movs r2, #1
135 ; CHECK-NEXT: movs r3, #0
136 ; CHECK-NEXT: cmp r0, r1
137 ; CHECK-NEXT: bne .LBB7_2
138 ; CHECK-NEXT: @ %bb.1: @ %entry
139 ; CHECK-NEXT: mov r2, r3
140 ; CHECK-NEXT: .LBB7_2: @ %entry
141 ; CHECK-NEXT: lsls r0, r2, #2
142 ; CHECK-NEXT: bx lr
143 entry:
144 %cmp = icmp ne i32 %a, %b
145 %cond = select i1 %cmp, i32 4, i32 0
146 ret i32 %cond
147 }
148
0 ; RUN: llc -mtriple=thumb-eabi < %s | FileCheck %s
11
22 define i1 @t1(i64 %x) {
3 %B = icmp slt i64 %x, 0
4 ret i1 %B
3 ; CHECK-LABEL: t1:
4 ; CHECK: lsrs r0, r1, #31
5 %B = icmp slt i64 %x, 0
6 ret i1 %B
57 }
68
79 define i1 @t2(i64 %x) {
8 %tmp = icmp ult i64 %x, 4294967296
9 ret i1 %tmp
10 ; CHECK-LABEL: t2:
11 ; CHECK: movs r0, #1
12 ; CHECK: movs r2, #0
13 ; CHECK: cmp r1, #0
14 ; CHECK: beq .LBB1_2
15 %tmp = icmp ult i64 %x, 4294967296
16 ret i1 %tmp
1017 }
1118
1219 define i1 @t3(i32 %x) {
13 %tmp = icmp ugt i32 %x, -1
14 ret i1 %tmp
20 ; CHECK-LABEL: t3:
21 ; CHECK: movs r0, #0
22 %tmp = icmp ugt i32 %x, -1
23 ret i1 %tmp
1524 }
1625
17 ; CHECK: cmp
26
1827 ; CHECK-NOT: cmp
19
20
21