llvm.org GIT mirror llvm / 4512044
[AMDGPU][mc] Fix memory corruption uncovered by AddressSanitizer during coverage/smoke Gfx7/8 testing. Coverage/smoke Gfx7/8 tests were committed r292922 but then reverted by r292974 due to AddressSanitizer failure, which is fixed by this patch. Tests to be re-committed soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293338 91177308-0d34-0410-b5e6-96231b3b80d8 Artem Tamazov 3 years ago
2 changed file(s) with 4 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
23722372 }
23732373
23742374 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
2375 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
2376
23772375 if (!GDSOnly) {
23782376 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
23792377 }
334334 }
335335
336336 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
337 assert(OpNo <= Desc.NumOperands);
337338 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
338339 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
339340 OpType <= AMDGPU::OPERAND_SRC_LAST;
340341 }
341342
342343 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
344 assert(OpNo <= Desc.NumOperands);
343345 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
344346 switch (OpType) {
345347 case AMDGPU::OPERAND_REG_IMM_FP32:
355357 }
356358
357359 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
360 assert(OpNo <= Desc.NumOperands);
358361 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
359362 return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
360363 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
398401
399402 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
400403 unsigned OpNo) {
404 assert(OpNo <= Desc.NumOperands);
401405 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
402406 return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
403407 }