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ARM: Mark double-precision instructions as such This prevents us from silently accepting invalid instructions on (for example) Cortex-M4 with just single-precision VFP support. No tests for the extra Pat Requires because they're essentially assertions: the affected code should have been lowered to libcalls before ISel. rdar://problem/15302004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
5 changed file(s) with 266 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
246246 : InstAlias, Requires<[IsThumb2]>;
247247 class VFP2InstAlias
248248 : InstAlias, Requires<[HasVFP2]>;
249 class VFP2DPInstAlias
250 : InstAlias, Requires<[HasVFP2,HasDPVFP]>;
249251 class VFP3InstAlias
250252 : InstAlias, Requires<[HasVFP3]>;
251253 class NEONInstAlias
15691571 let Inst{8} = 1; // Double precision
15701572 let Inst{7-6} = opcod4;
15711573 let Inst{4} = opcod5;
1574
1575 let Predicates = [HasVFP2, HasDPVFP];
15721576 }
15731577
15741578 // Double precision, unary, not-predicated
16211625 let Inst{8} = 1; // Double precision
16221626 let Inst{6} = op6;
16231627 let Inst{4} = op4;
1628
1629 let Predicates = [HasVFP2, HasDPVFP];
16241630 }
16251631
16261632 // FP, binary, not predicated
16501656 let Inst{8} = 1; // double precision
16511657 let Inst{6} = opcod3;
16521658 let Inst{4} = 0;
1659
1660 let Predicates = [HasVFP2, HasDPVFP];
16531661 }
16541662
16551663 // Single precision, unary, predicated
211211 AssemblerPredicate<"FeatureVFP3", "VFP3">;
212212 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
213213 AssemblerPredicate<"FeatureVFP4", "VFP4">;
214 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
215 AssemblerPredicate<"!FeatureVFPOnlySP",
216 "double precision VFP">;
214217 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
215218 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
216219 def HasNEON : Predicate<"Subtarget->hasNEON()">,
345345 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
346346 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
347347 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
348 Requires<[HasFPARMv8]>;
348 Requires<[HasFPARMv8, HasDPVFP]>;
349349 }
350350 }
351351
367367 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
368368 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
369369 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
370 Requires<[HasFPARMv8]>;
370 Requires<[HasFPARMv8, HasDPVFP]>;
371371 }
372372 }
373373
376376
377377 // Match reassociated forms only if not sign dependent rounding.
378378 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
379 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
379 (VNMULD DPR:$a, DPR:$b)>,
380 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
380381 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
381382 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
382383
507508 let Inst{11-8} = 0b1011;
508509 let Inst{7-6} = 0b11;
509510 let Inst{4} = 0;
511
512 let Predicates = [HasVFP2, HasDPVFP];
510513 }
511514
512515 // Between half, single and double-precision. For disassembly only.
537540 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
538541 (outs DPR:$Dd), (ins SPR:$Sm),
539542 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
540 []>, Requires<[HasFPARMv8]> {
543 []>, Requires<[HasFPARMv8, HasDPVFP]> {
541544 // Instruction operands.
542545 bits<5> Sm;
543546
549552 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
550553 (outs SPR:$Sd), (ins DPR:$Dm),
551554 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
552 []>, Requires<[HasFPARMv8]> {
555 []>, Requires<[HasFPARMv8, HasDPVFP]> {
553556 // Instruction operands.
554557 bits<5> Sd;
555558 bits<5> Dm;
564567 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
565568 (outs DPR:$Dd), (ins SPR:$Sm),
566569 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
567 []>, Requires<[HasFPARMv8]> {
570 []>, Requires<[HasFPARMv8, HasDPVFP]> {
568571 // Instruction operands.
569572 bits<5> Sm;
570573
576579 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
577580 (outs SPR:$Sd), (ins DPR:$Dm),
578581 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
579 []>, Requires<[HasFPARMv8]> {
582 []>, Requires<[HasFPARMv8, HasDPVFP]> {
580583 // Instruction operands.
581584 bits<5> Sd;
582585 bits<5> Dm;
607610 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
608611 (outs SPR:$Sd), (ins DPR:$Dm),
609612 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
610 []>, Requires<[HasFPARMv8]> {
613 []>, Requires<[HasFPARMv8, HasDPVFP]> {
611614 bits<5> Dm;
612615
613616 let Inst{17-16} = rm;
621624 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
622625 (outs SPR:$Sd), (ins DPR:$Dm),
623626 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
624 []>, Requires<[HasFPARMv8]> {
627 []>, Requires<[HasFPARMv8, HasDPVFP]> {
625628 bits<5> Dm;
626629
627630 let Inst{17-16} = rm;
664667 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
665668 (outs DPR:$Dd), (ins DPR:$Dm),
666669 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
667 []>, Requires<[HasFPARMv8]> {
670 []>, Requires<[HasFPARMv8, HasDPVFP]> {
668671 let Inst{7} = op2;
669672 let Inst{16} = op;
670673 }
674677 Requires<[HasFPARMv8]>;
675678 def : InstAlias
676679 (!cast(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
677 Requires<[HasFPARMv8]>;
680 Requires<[HasFPARMv8,HasDPVFP]>;
678681 }
679682
680683 defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
692695 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
693696 (outs DPR:$Dd), (ins DPR:$Dm),
694697 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
695 []>, Requires<[HasFPARMv8]> {
698 []>, Requires<[HasFPARMv8, HasDPVFP]> {
696699 let Inst{17-16} = rm;
697700 }
698701 }
702705 Requires<[HasFPARMv8]>;
703706 def : InstAlias
704707 (!cast(NAME#"D") DPR:$Dd, DPR:$Dm)>,
705 Requires<[HasFPARMv8]>;
708 Requires<[HasFPARMv8,HasDPVFP]>;
706709 }
707710
708711 defm VRINTA : vrint_inst_anpm<"a", 0b00>;
899902 let Inst{5} = Sm{0};
900903 let Inst{15-12} = Dd{3-0};
901904 let Inst{22} = Dd{4};
905
906 let Predicates = [HasVFP2, HasDPVFP];
902907 }
903908
904909 class AVConv1InSs_Encode opcod1, bits<2> opcod2, bits<4> opcod3,
970975 let Inst{5} = Dm{4};
971976 let Inst{15-12} = Sd{4-1};
972977 let Inst{22} = Sd{0};
978
979 let Predicates = [HasVFP2, HasDPVFP];
973980 }
974981
975982 class AVConv1InsS_Encode opcod1, bits<2> opcod2, bits<4> opcod3,
10911098 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
10921099 let Inst{22} = dst{4};
10931100 let Inst{15-12} = dst{3-0};
1101
1102 let Predicates = [HasVFP2, HasDPVFP];
10941103 }
10951104
10961105 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
12031212 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
12041213 (f64 DPR:$Ddin)))]>,
12051214 RegConstraint<"$Ddin = $Dd">,
1206 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1215 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12071216
12081217 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
12091218 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
12191228
12201229 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
12211230 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1222 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1231 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12231232 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
12241233 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
12251234 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
12301239 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
12311240 (f64 DPR:$Ddin)))]>,
12321241 RegConstraint<"$Ddin = $Dd">,
1233 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1242 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12341243
12351244 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
12361245 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
12461255
12471256 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
12481257 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1249 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1258 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12501259 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
12511260 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
12521261 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
12571266 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
12581267 (f64 DPR:$Ddin)))]>,
12591268 RegConstraint<"$Ddin = $Dd">,
1260 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1269 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12611270
12621271 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
12631272 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
12731282
12741283 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
12751284 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1276 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1285 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12771286 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
12781287 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
12791288 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
12841293 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
12851294 (f64 DPR:$Ddin)))]>,
12861295 RegConstraint<"$Ddin = $Dd">,
1287 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1296 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
12881297
12891298 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
12901299 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
12991308
13001309 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
13011310 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1302 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1311 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
13031312 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
13041313 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
13051314 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
13131322 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
13141323 (f64 DPR:$Ddin)))]>,
13151324 RegConstraint<"$Ddin = $Dd">,
1316 Requires<[HasVFP4,UseFusedMAC]>;
1325 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
13171326
13181327 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
13191328 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
13281337
13291338 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
13301339 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1331 Requires<[HasVFP4,UseFusedMAC]>;
1340 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
13321341 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
13331342 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
13341343 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
13371346 // (fma x, y, z) -> (vfms z, x, y)
13381347 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
13391348 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1340 Requires<[HasVFP4]>;
1349 Requires<[HasVFP4,HasDPVFP]>;
13411350 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
13421351 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
13431352 Requires<[HasVFP4]>;
13481357 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
13491358 (f64 DPR:$Ddin)))]>,
13501359 RegConstraint<"$Ddin = $Dd">,
1351 Requires<[HasVFP4,UseFusedMAC]>;
1360 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
13521361
13531362 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
13541363 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
13631372
13641373 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
13651374 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1366 Requires<[HasVFP4,UseFusedMAC]>;
1375 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
13671376 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
13681377 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
13691378 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
13721381 // (fma (fneg x), y, z) -> (vfms z, x, y)
13731382 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
13741383 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1375 Requires<[HasVFP4]>;
1384 Requires<[HasVFP4,HasDPVFP]>;
13761385 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
13771386 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
13781387 Requires<[HasVFP4]>;
13791388 // (fma x, (fneg y), z) -> (vfms z, x, y)
13801389 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
13811390 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1382 Requires<[HasVFP4]>;
1391 Requires<[HasVFP4,HasDPVFP]>;
13831392 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
13841393 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
13851394 Requires<[HasVFP4]>;
13901399 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
13911400 (f64 DPR:$Ddin)))]>,
13921401 RegConstraint<"$Ddin = $Dd">,
1393 Requires<[HasVFP4,UseFusedMAC]>;
1402 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
13941403
13951404 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
13961405 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
14051414
14061415 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
14071416 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1408 Requires<[HasVFP4,UseFusedMAC]>;
1417 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
14091418 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
14101419 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
14111420 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
14141423 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
14151424 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
14161425 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1417 Requires<[HasVFP4]>;
1426 Requires<[HasVFP4,HasDPVFP]>;
14181427 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
14191428 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
14201429 Requires<[HasVFP4]>;
14211430 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
14221431 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
14231432 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1424 Requires<[HasVFP4]>;
1433 Requires<[HasVFP4,HasDPVFP]>;
14251434 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
14261435 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
14271436 Requires<[HasVFP4]>;
14321441 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
14331442 (f64 DPR:$Ddin)))]>,
14341443 RegConstraint<"$Ddin = $Dd">,
1435 Requires<[HasVFP4,UseFusedMAC]>;
1444 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
14361445
14371446 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
14381447 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
14461455
14471456 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
14481457 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1449 Requires<[HasVFP4,UseFusedMAC]>;
1458 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
14501459 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
14511460 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
14521461 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
14561465 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
14571466 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
14581467 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1459 Requires<[HasVFP4]>;
1468 Requires<[HasVFP4,HasDPVFP]>;
14601469 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
14611470 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
14621471 Requires<[HasVFP4]>;
14631472 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
14641473 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
14651474 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1466 Requires<[HasVFP4]>;
1475 Requires<[HasVFP4,HasDPVFP]>;
14671476 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
14681477 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
14691478 Requires<[HasVFP4]>;
14701479 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
14711480 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
14721481 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1473 Requires<[HasVFP4]>;
1482 Requires<[HasVFP4,HasDPVFP]>;
14741483 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
14751484 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
14761485 Requires<[HasVFP4]>;
14841493 IIC_fpUNA64,
14851494 [(set (f64 DPR:$Dd),
14861495 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1487 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2]>;
1496 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
14881497
14891498 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
14901499 IIC_fpUNA32,
15891598 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
15901599 VFPMiscFrm, IIC_fpUNA64,
15911600 "vmov", ".f64\t$Dd, $imm",
1592 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1601 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1602 Requires<[HasVFP3,HasDPVFP]> {
15931603 bits<5> Dd;
15941604 bits<8> imm;
15951605
16711681 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
16721682
16731683 // Be friendly and accept the old form of zero-compare
1674 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1684 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
16751685 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
16761686
16771687
16781688 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
16791689 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
16801690 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1681 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1682 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1691 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1692 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
16831693 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
16841694 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1685 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1686 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1695 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1696 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
16871697
16881698 // No need for the size suffix on VSQRT. It's implied by the register classes.
16891699 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1690 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1700 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
16911701
16921702 // VLDR/VSTR accept an optional type suffix.
16931703 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
0 @ RUN: not llvm-mc < %s -triple thumbv8-unknown-unknown -show-encoding -mattr=+fp-only-sp,-neon 2> %t > %t2
1 @ RUN: FileCheck %s < %t --check-prefix=CHECK-ERRORS
2 @ RUN: FileCheck %s < %t2
3
4 vadd.f64 d0, d1, d2
5 vsub.f64 d2, d3, d4
6 vdiv.f64 d4, d5, d6
7 vmul.f64 d6, d7, d8
8 vnmul.f64 d8, d9, d10
9 @ CHECK-ERRORS: error: instruction requires: double precision VFP
10 @ CHECK-ERRORS-NEXT: vadd.f64 d0, d1, d2
11 @ CHECK-ERRORS: error: instruction requires: double precision VFP
12 @ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
13 @ CHECK-ERRORS: error: instruction requires: double precision VFP
14 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
15 @ CHECK-ERRORS: error: instruction requires: double precision VFP
16 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
17 @ CHECK-ERRORS: error: instruction requires: double precision VFP
18 @ CHECK-ERRORS-NEXT: vnmul.f64 d8, d9, d10
19
20 vmla.f64 d11, d10, d9
21 vmls.f64 d8, d7, d6
22 vnmla.f64 d5, d4, d3
23 vnmls.f64 d2, d1, d0
24 vfma.f64 d1, d2, d3
25 vfms.f64 d4, d5, d6
26 vfnma.f64 d7, d8, d9
27 vfnms.f64 d10, d11, d12
28 @ CHECK-ERRORS: error: instruction requires: double precision VFP
29 @ CHECK-ERRORS-NEXT: vmla.f64 d11, d10, d9
30 @ CHECK-ERRORS: error: instruction requires: double precision VFP
31 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
32 @ CHECK-ERRORS: error: instruction requires: double precision VFP
33 @ CHECK-ERRORS-NEXT: vnmla.f64 d5, d4, d3
34 @ CHECK-ERRORS: error: instruction requires: double precision VFP
35 @ CHECK-ERRORS-NEXT: vnmls.f64 d2, d1, d0
36 @ CHECK-ERRORS: error: instruction requires: double precision VFP
37 @ CHECK-ERRORS-NEXT: vfma.f64 d1, d2, d3
38 @ CHECK-ERRORS: error: instruction requires: double precision VFP
39 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
40 @ CHECK-ERRORS: error: instruction requires: double precision VFP
41 @ CHECK-ERRORS-NEXT: vfnma.f64 d7, d8, d9
42 @ CHECK-ERRORS: error: instruction requires: double precision VFP
43 @ CHECK-ERRORS-NEXT: vfnms.f64 d10, d11, d12
44
45 vneg.f64 d15, d14
46 vsqrt.f64 d13, d12
47 vsqrt d13, d14
48 @ CHECK-ERRORS: error: instruction requires: double precision VFP
49 @ CHECK-ERRORS-NEXT: vneg.f64 d15, d14
50 @ CHECK-ERRORS: error: instruction requires: double precision VFP
51 @ CHECK-ERRORS-NEXT: vsqrt.f64 d13, d12
52 @ CHECK-ERRORS: error: instruction requires: double precision VFP
53 @ CHECK-ERRORS-NEXT: vsqrt d13, d14
54
55 vcmpe.f64 d0, d1
56 vcmp.f64 d2, d3
57 vabs.f64 d4, d5
58 vcmpe.f64 d5, #0
59 vcmp.f64 d6, #0
60 @ CHECK-ERRORS: error: instruction requires: double precision VFP
61 @ CHECK-ERRORS-NEXT: vcmpe.f64 d0, d1
62 @ CHECK-ERRORS: error: instruction requires: double precision VFP
63 @ CHECK-ERRORS-NEXT: vcmp.f64 d2, d3
64 @ CHECK-ERRORS: error: instruction requires: double precision VFP
65 @ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
66 @ CHECK-ERRORS: error: instruction requires: double precision VFP
67 @ CHECK-ERRORS-NEXT: vcmpe.f64 d5, #0
68 @ CHECK-ERRORS: error: instruction requires: double precision VFP
69 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
70
71 vmov.f64 d11, d10
72 @ CHECK-ERRORS: error: instruction requires: NEON
73 @ CHECK-ERRORS-NEXT: vmov.f64 d11, d10
74
75 vcvt.f64.s32 d9, s8
76 vcvt.f64.u32 d7, s6
77 vcvt.s32.f64 s5, d4
78 vcvt.u32.f64 s3, d2
79 vcvtr.s32.f64 s1, d0
80 vcvtr.u32.f64 s1, d2
81 vcvt.s16.f64 d3, d4, #1
82 vcvt.u16.f64 d5, d6, #2
83 vcvt.s32.f64 d7, d8, #3
84 vcvt.u32.f64 d9, d10, #4
85 vcvt.f64.s16 d11, d12, #3
86 vcvt.f64.u16 d13, d14, #2
87 vcvt.f64.s32 d15, d14, #1
88 vcvt.f64.u32 d13, d12, #1
89 @ CHECK-ERRORS: error: instruction requires: double precision VFP
90 @ CHECK-ERRORS-NEXT: vcvt.f64.s32 d9, s8
91 @ CHECK-ERRORS: error: instruction requires: double precision VFP
92 @ CHECK-ERRORS-NEXT: vcvt.f64.u32 d7, s6
93 @ CHECK-ERRORS: error: instruction requires: double precision VFP
94 @ CHECK-ERRORS-NEXT: vcvt.s32.f64 s5, d4
95 @ CHECK-ERRORS: error: instruction requires: double precision VFP
96 @ CHECK-ERRORS-NEXT: vcvt.u32.f64 s3, d2
97 @ CHECK-ERRORS: error: instruction requires: double precision VFP
98 @ CHECK-ERRORS-NEXT: vcvtr.s32.f64 s1, d0
99 @ CHECK-ERRORS: error: instruction requires: double precision VFP
100 @ CHECK-ERRORS-NEXT: vcvtr.u32.f64 s1, d2
101 @ CHECK-ERRORS: error: instruction requires: double precision VFP
102 @ CHECK-ERRORS-NEXT: vcvt.s16.f64 d3, d4, #1
103 @ CHECK-ERRORS: error: instruction requires: double precision VFP
104 @ CHECK-ERRORS-NEXT: vcvt.u16.f64 d5, d6, #2
105 @ CHECK-ERRORS: error: instruction requires: double precision VFP
106 @ CHECK-ERRORS-NEXT: vcvt.s32.f64 d7, d8, #3
107 @ CHECK-ERRORS: error: instruction requires: double precision VFP
108 @ CHECK-ERRORS-NEXT: vcvt.u32.f64 d9, d10, #4
109 @ CHECK-ERRORS: error: instruction requires: double precision VFP
110 @ CHECK-ERRORS-NEXT: vcvt.f64.s16 d11, d12, #3
111 @ CHECK-ERRORS: error: instruction requires: double precision VFP
112 @ CHECK-ERRORS-NEXT: vcvt.f64.u16 d13, d14, #2
113 @ CHECK-ERRORS: error: instruction requires: double precision VFP
114 @ CHECK-ERRORS-NEXT: vcvt.f64.s32 d15, d14, #1
115 @ CHECK-ERRORS: error: instruction requires: double precision VFP
116 @ CHECK-ERRORS-NEXT: vcvt.f64.u32 d13, d12, #1
117
118 @ v8 operations, also double precision so make sure they're rejected.
119 vselgt.f64 d0, d1, d2
120 vselge.f64 d3, d4, d5
121 vseleq.f64 d6, d7, d8
122 vselvs.f64 d9, d10, d11
123 @ CHECK-ERRORS: error: instruction requires: double precision VFP
124 @ CHECK-ERRORS-NEXT: vselgt.f64 d0, d1, d2
125 @ CHECK-ERRORS: error: instruction requires: double precision VFP
126 @ CHECK-ERRORS-NEXT: vselge.f64 d3, d4, d5
127 @ CHECK-ERRORS: error: instruction requires: double precision VFP
128 @ CHECK-ERRORS-NEXT: vseleq.f64 d6, d7, d8
129 @ CHECK-ERRORS: error: instruction requires: double precision VFP
130 @ CHECK-ERRORS-NEXT: vselvs.f64 d9, d10, d11
131
132 vmaxnm.f64 d12, d13, d14
133 @ CHECK-ERRORS: error: instruction requires: double precision VFP
134 @ CHECK-ERRORS-NEXT: vmaxnm.f64 d12, d13, d14
135
136 vcvtb.f64.f16 d7, s8
137 vcvtb.f16.f64 s9, d10
138 vcvtt.f64.f16 d11, s12
139 vcvtt.f16.f64 s13, d14
140 @ CHECK-ERRORS: error: instruction requires: double precision VFP
141 @ CHECK-ERRORS-NEXT: vcvtb.f64.f16 d7, s8
142 @ CHECK-ERRORS: error: instruction requires: double precision VFP
143 @ CHECK-ERRORS-NEXT: vcvtb.f16.f64 s9, d10
144 @ CHECK-ERRORS: error: instruction requires: double precision VFP
145 @ CHECK-ERRORS-NEXT: vcvtt.f64.f16 d11, s12
146 @ CHECK-ERRORS: error: instruction requires: double precision VFP
147 @ CHECK-ERRORS-NEXT: vcvtt.f16.f64 s13, d14
148
149 vrintz.f64 d15, d14
150 vrintr.f64.f64 d13, d12
151 vrintx.f64 d11, d10
152 vrinta.f64.f64 d9, d8
153 vrintn.f64 d7, d6
154 vrintp.f64.f64 d5, d4
155 vrintm.f64 d3, d2
156 @ CHECK-ERRORS: error: instruction requires: double precision VFP
157 @ CHECK-ERRORS-NEXT: vrintz.f64 d15, d14
158 @ CHECK-ERRORS: error: instruction requires: double precision VFP
159 @ CHECK-ERRORS-NEXT: vrintr.f64.f64 d13, d12
160 @ CHECK-ERRORS: error: instruction requires: double precision VFP
161 @ CHECK-ERRORS-NEXT: vrintx.f64 d11, d10
162 @ CHECK-ERRORS: error: instruction requires: double precision VFP
163 @ CHECK-ERRORS-NEXT: vrinta.f64.f64 d9, d8
164 @ CHECK-ERRORS: error: instruction requires: double precision VFP
165 @ CHECK-ERRORS-NEXT: vrintn.f64 d7, d6
166 @ CHECK-ERRORS: error: instruction requires: double precision VFP
167 @ CHECK-ERRORS-NEXT: vrintp.f64.f64 d5, d4
168 @ CHECK-ERRORS: error: instruction requires: double precision VFP
169 @ CHECK-ERRORS-NEXT: vrintm.f64 d3, d2
170
171 @ Double precisionish operations that actually *are* allowed.
172 vldr d0, [sp]
173 vstr d3, [sp]
174 vldm r0, {d0, d1}
175 vstm r4, {d3, d4}
176 vpush {d6, d7}
177 vpop {d8, d9}
178 vmov r1, r0, d1
179 vmov d2, r3, r4
180 vmov.f64 r5, r6, d7
181 vmov.f64 d8, r9, r10
182 @ CHECK: vldr d0, [sp]
183 @ CHECK: vstr d3, [sp]
184 @ CHECK: vldmia r0, {d0, d1}
185 @ CHECK: vstmia r4, {d3, d4}
186 @ CHECK: vpush {d6, d7}
187 @ CHECK: vpop {d8, d9}
188 @ CHECK: vmov r1, r0, d1
189 @ CHECK: vmov d2, r3, r4
190 @ CHECK: vmov r5, r6, d7
191 @ CHECK: vmov d8, r9, r10
55
66 @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
77 @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
8 @ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP
9 @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17
810 vfma.f64 d16, d18, d17
911
1012 @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
2628
2729 @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
2830 @ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b]
31 @ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP
32 @ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17
2933 vfnma.f64 d16, d18, d17
3034
3135 @ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee]
3539
3640 @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee]
3741 @ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b]
42 @ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP
43 @ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17
3844 vfms.f64 d16, d18, d17
3945
4046 @ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee]
5662
5763 @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
5864 @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b]
65 @ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP
66 @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17
5967 vfnms.f64 d16, d18, d17
6068
6169 @ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee]