llvm.org GIT mirror llvm / 445ba85
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 7 years ago
4 changed file(s) with 38 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
32443244 let Inst{15-14} = 0b10;
32453245 let Inst{12} = 1;
32463246
3247 bits<20> target;
3247 bits<24> target;
32483248 let Inst{26} = target{19};
32493249 let Inst{11} = target{18};
32503250 let Inst{13} = target{17};
3251 let Inst{21-16} = target{16-11};
3251 let Inst{25-16} = target{20-11};
32523252 let Inst{10-0} = target{10-0};
32533253 let DecoderMethod = "DecodeT2BInstruction";
32543254 }
20942094 static DecodeStatus
20952095 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
20962096 uint64_t Address, const void *Decoder) {
2097 DecodeStatus S = MCDisassembler::Success;
2098 unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) |
2099 (fieldFromInstruction(Insn, 11, 1) << 18) |
2100 (fieldFromInstruction(Insn, 13, 1) << 17) |
2101 (fieldFromInstruction(Insn, 16, 6) << 11) |
2102 (fieldFromInstruction(Insn, 26, 1) << 19);
2103 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2097 DecodeStatus Status = MCDisassembler::Success;
2098
2099 // Note the J1 and J2 values are from the encoded instruction. So here
2100 // change them to I1 and I2 values via as documented:
2101 // I1 = NOT(J1 EOR S);
2102 // I2 = NOT(J2 EOR S);
2103 // and build the imm32 with one trailing zero as documented:
2104 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2105 unsigned S = fieldFromInstruction(Insn, 26, 1);
2106 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2107 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2108 unsigned I1 = !(J1 ^ S);
2109 unsigned I2 = !(J2 ^ S);
2110 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2111 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2112 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2113 int imm32 = SignExtend32<24>(tmp << 1);
2114 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
21042115 true, 4, Inst, Decoder))
2105 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2106 return S;
2116 Inst.addOperand(MCOperand::CreateImm(imm32));
2117
2118 return Status;
21072119 }
21082120
21092121 static DecodeStatus
0 @ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s
1 .syntax unified
2 .globl _func
3 .thumb_func _foo
4 .space 0x37c6
5 _foo:
6 @------------------------------------------------------------------------------
7 @ B (thumb2 b.w encoding T4) rdar://12585795
8 @------------------------------------------------------------------------------
9 b.w 0x3680c
10
11 @ CHECK: b.w #223244 @ encoding: [0x6d,0xf0,0x0c,0xb0]
168168
169169 0x13 0xf5 0xce 0xa9
170170
171 # CHECK: b.w #208962
172
173 0x33 0xf0 0x21 0xb8 # rdar://12585795
171174
172175 #------------------------------------------------------------------------------
173176 # BFC