llvm.org GIT mirror llvm / 4403b93
Let's start another backend :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 11 years ago
25 changed file(s) with 1884 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
226226 pic16-*) llvm_cv_target_arch="PIC16" ;;
227227 xcore-*) llvm_cv_target_arch="XCore" ;;
228228 msp430-*) llvm_cv_target_arch="MSP430" ;;
229 s390x-*) llvm_cv_target_arch="SystemZ" ;;
229230 *) llvm_cv_target_arch="Unknown" ;;
230231 esac])
231232
351352 PIC16) AC_SUBST(TARGET_HAS_JIT,0) ;;
352353 XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
353354 MSP430) AC_SUBST(TARGET_HAS_JIT,0) ;;
355 SystemZ) AC_SUBST(TARGET_HAS_JIT,0) ;;
354356 *) AC_SUBST(TARGET_HAS_JIT,0) ;;
355357 esac
356358 fi
400402 [Build specific host targets: all,host-only,{target-name} (default=all)]),,
401403 enableval=all)
402404 case "$enableval" in
403 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend" ;;
405 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU PIC16 XCore MSP430 SystemZ CBackend MSIL CppBackend" ;;
404406 host-only)
405407 case "$llvm_cv_target_arch" in
406408 x86) TARGETS_TO_BUILD="X86" ;;
415417 PIC16) TARGETS_TO_BUILD="PIC16" ;;
416418 XCore) TARGETS_TO_BUILD="XCore" ;;
417419 MSP430) TARGETS_TO_BUILD="MSP430" ;;
420 SystemZ) TARGETS_TO_BUILD="SystemZ" ;;
418421 *) AC_MSG_ERROR([Can not set target to build]) ;;
419422 esac
420423 ;;
432435 pic16) TARGETS_TO_BUILD="PIC16 $TARGETS_TO_BUILD" ;;
433436 xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
434437 msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
438 systemz) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
435439 cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
436440 msil) TARGETS_TO_BUILD="MSIL $TARGETS_TO_BUILD" ;;
437441 cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
24042404 pic16-*) llvm_cv_target_arch="PIC16" ;;
24052405 xcore-*) llvm_cv_target_arch="XCore" ;;
24062406 msp430-*) llvm_cv_target_arch="MSP430" ;;
2407 s390x-*) llvm_cv_target_arch="SystemZ" ;;
24072408 *) llvm_cv_target_arch="Unknown" ;;
24082409 esac
24092410 fi
48524853 ;;
48534854 MSP430) TARGET_HAS_JIT=0
48544855 ;;
4856 SystemZ) TARGET_HAS_JIT=0
4857 ;;
48554858 *) TARGET_HAS_JIT=0
48564859 ;;
48574860 esac
49334936 fi
49344937
49354938 case "$enableval" in
4936 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend" ;;
4939 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU PIC16 XCore MSP430 SystemZ CBackend MSIL CppBackend" ;;
49374940 host-only)
49384941 case "$llvm_cv_target_arch" in
49394942 x86) TARGETS_TO_BUILD="X86" ;;
49484951 PIC16) TARGETS_TO_BUILD="PIC16" ;;
49494952 XCore) TARGETS_TO_BUILD="XCore" ;;
49504953 MSP430) TARGETS_TO_BUILD="MSP430" ;;
4954 SystemZ) TARGETS_TO_BUILD="SystemZ" ;;
49514955 *) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
49524956 echo "$as_me: error: Can not set target to build" >&2;}
49534957 { (exit 1); exit 1; }; } ;;
49674971 pic16) TARGETS_TO_BUILD="PIC16 $TARGETS_TO_BUILD" ;;
49684972 xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
49694973 msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
4974 systemz) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
49704975 cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
49714976 msil) TARGETS_TO_BUILD="MSIL $TARGETS_TO_BUILD" ;;
49724977 cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
0 ##===- lib/Target/SystemZ/Makefile ------------- -----------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8 LEVEL = ../../../..
9 LIBRARYNAME = LLVMSystemZAsmPrinter
10
11 # Hack: we need to include 'main' SystemZ target directory to grab private headers
12 CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
13
14 include $(LEVEL)/Makefile.common
0 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly writer ---------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the SystemZ assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "asm-printer"
15 #include "SystemZ.h"
16 #include "SystemZInstrInfo.h"
17 #include "SystemZTargetMachine.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Module.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/DwarfWriter.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/Target/TargetAsmInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Mangler.h"
32 #include "llvm/Support/raw_ostream.h"
33
34 using namespace llvm;
35
36 STATISTIC(EmittedInsts, "Number of machine instrs printed");
37
38 namespace {
39 class VISIBILITY_HIDDEN SystemZAsmPrinter : public AsmPrinter {
40 public:
41 SystemZAsmPrinter(raw_ostream &O, SystemZTargetMachine &TM,
42 const TargetAsmInfo *TAI,
43 CodeGenOpt::Level OL, bool V)
44 : AsmPrinter(O, TM, TAI, OL, V) {}
45
46 virtual const char *getPassName() const {
47 return "SystemZ Assembly Printer";
48 }
49
50 void printOperand(const MachineInstr *MI, int OpNum,
51 const char* Modifier = 0);
52 bool printInstruction(const MachineInstr *MI); // autogenerated.
53 void printMachineInstruction(const MachineInstr * MI);
54
55 void emitFunctionHeader(const MachineFunction &MF);
56 bool runOnMachineFunction(MachineFunction &F);
57 bool doInitialization(Module &M);
58 bool doFinalization(Module &M);
59
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AsmPrinter::getAnalysisUsage(AU);
62 AU.setPreservesAll();
63 }
64 };
65 } // end of anonymous namespace
66
67 #include "SystemZGenAsmWriter.inc"
68
69 /// createSystemZCodePrinterPass - Returns a pass that prints the SystemZ
70 /// assembly code for a MachineFunction to the given output stream,
71 /// using the given target machine description. This should work
72 /// regardless of whether the function is in SSA form.
73 ///
74 FunctionPass *llvm::createSystemZCodePrinterPass(raw_ostream &o,
75 SystemZTargetMachine &tm,
76 CodeGenOpt::Level OptLevel,
77 bool verbose) {
78 return new SystemZAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
79 }
80
81 bool SystemZAsmPrinter::doInitialization(Module &M) {
82 Mang = new Mangler(M, "", TAI->getPrivateGlobalPrefix());
83 return false; // success
84 }
85
86
87 bool SystemZAsmPrinter::doFinalization(Module &M) {
88 return AsmPrinter::doFinalization(M);
89 }
90
91 void SystemZAsmPrinter::emitFunctionHeader(const MachineFunction &MF) {
92 const Function *F = MF.getFunction();
93
94 SwitchToSection(TAI->SectionForGlobal(F));
95
96 unsigned FnAlign = 4;
97 if (F->hasFnAttr(Attribute::OptimizeForSize))
98 FnAlign = 1;
99
100 EmitAlignment(FnAlign, F);
101
102 switch (F->getLinkage()) {
103 default: assert(0 && "Unknown linkage type!");
104 case Function::InternalLinkage: // Symbols default to internal.
105 case Function::PrivateLinkage:
106 break;
107 case Function::ExternalLinkage:
108 O << "\t.globl\t" << CurrentFnName << '\n';
109 break;
110 case Function::LinkOnceAnyLinkage:
111 case Function::LinkOnceODRLinkage:
112 case Function::WeakAnyLinkage:
113 case Function::WeakODRLinkage:
114 O << "\t.weak\t" << CurrentFnName << '\n';
115 break;
116 }
117
118 printVisibility(CurrentFnName, F->getVisibility());
119
120 O << "\t.type\t" << CurrentFnName << ",@function\n"
121 << CurrentFnName << ":\n";
122 }
123
124 bool SystemZAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
125 SetupMachineFunction(MF);
126 O << "\n\n";
127
128 // Print the 'header' of function
129 emitFunctionHeader(MF);
130
131 // Print out code for the function.
132 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
133 I != E; ++I) {
134 // Print a label for the basic block.
135 if (!VerboseAsm && (I->pred_empty() || I->isOnlyReachableByFallthrough())) {
136 // This is an entry block or a block that's only reachable via a
137 // fallthrough edge. In non-VerboseAsm mode, don't print the label.
138 } else {
139 printBasicBlockLabel(I, true, true, VerboseAsm);
140 O << '\n';
141 }
142
143 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
144 II != E; ++II)
145 // Print the assembly for the instruction.
146 printMachineInstruction(II);
147 }
148
149 if (TAI->hasDotTypeDotSizeDirective())
150 O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << '\n';
151
152 O.flush();
153
154 // We didn't modify anything
155 return false;
156 }
157
158 void SystemZAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
159 ++EmittedInsts;
160
161 // Call the autogenerated instruction printer routines.
162 if (printInstruction(MI))
163 return;
164
165 assert(0 && "Should not happen");
166 }
167
168 void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
169 const char* Modifier) {
170 assert(0 && "Not implemented yet!");
171 }
0 ##===- lib/Target/SystemZ/Makefile ---------------------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file is distributed under the University of Illinois Open Source
5 # License. See LICENSE.TXT for details.
6 #
7 ##===----------------------------------------------------------------------===##
8 LEVEL = ../../..
9 LIBRARYNAME = LLVMSystemZCodeGen
10 TARGET = SystemZ
11
12 # Make sure that tblgen is run, first thing.
13 BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
14 SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
15 SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
16 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
17
18 DIRS = AsmPrinter
19
20 include $(LEVEL)/Makefile.common
21
0 //=-- SystemZ.h - Top-level interface for SystemZ representation -*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in
10 // the LLVM SystemZ backend.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_TARGET_SystemZ_H
15 #define LLVM_TARGET_SystemZ_H
16
17 #include "llvm/Target/TargetMachine.h"
18
19 namespace llvm {
20 class SystemZTargetMachine;
21 class FunctionPass;
22 class raw_ostream;
23
24 FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM,
25 CodeGenOpt::Level OptLevel);
26 FunctionPass *createSystemZCodePrinterPass(raw_ostream &o,
27 SystemZTargetMachine &tm,
28 CodeGenOpt::Level OptLevel,
29 bool verbose);
30 } // end namespace llvm;
31
32 // Defines symbolic names for SystemZ registers.
33 // This defines a mapping from register name to register number.
34 #include "SystemZGenRegisterNames.inc"
35
36 // Defines symbolic names for the SystemZ instructions.
37 #include "SystemZGenInstrNames.inc"
38
39 #endif
0 //===- SystemZ.td - Describe the SystemZ Target Machine ------*- tblgen -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 // This is the top level entry point for the SystemZ target.
9 //===----------------------------------------------------------------------===//
10
11 //===----------------------------------------------------------------------===//
12 // Target-independent interfaces
13 //===----------------------------------------------------------------------===//
14
15 include "llvm/Target/Target.td"
16
17 //===----------------------------------------------------------------------===//
18 // Subtarget Features.
19 //===----------------------------------------------------------------------===//
20 def FeatureX
21 : SubtargetFeature<"dummy", "DummyFeature", "true",
22 "Some feature">;
23
24 //===----------------------------------------------------------------------===//
25 // SystemZ supported processors.
26 //===----------------------------------------------------------------------===//
27 class Proc Features>
28 : Processor;
29
30 def : Proc<"generic", []>;
31
32 //===----------------------------------------------------------------------===//
33 // Register File Description
34 //===----------------------------------------------------------------------===//
35
36 include "SystemZRegisterInfo.td"
37
38 //===----------------------------------------------------------------------===//
39 // Calling Convention Description
40 //===----------------------------------------------------------------------===//
41
42 include "SystemZCallingConv.td"
43
44 //===----------------------------------------------------------------------===//
45 // Instruction Descriptions
46 //===----------------------------------------------------------------------===//
47
48 include "SystemZInstrInfo.td"
49
50 def SystemZInstrInfo : InstrInfo {}
51
52 //===----------------------------------------------------------------------===//
53 // Target Declaration
54 //===----------------------------------------------------------------------===//
55
56 def SystemZ : Target {
57 let InstructionSet = SystemZInstrInfo;
58 }
59
0 //=- SystemZCallingConv.td - Calling Conventions for SystemZ -*- tablegen -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 // This describes the calling conventions for SystemZ architecture.
9 //===----------------------------------------------------------------------===//
10
11 //===----------------------------------------------------------------------===//
12 // SystemZ Return Value Calling Convention
13 //===----------------------------------------------------------------------===//
14 def RetCC_SystemZ : CallingConv<[
15 // i64 is returned in register R2
16 CCIfType<[i64], CCAssignToReg<[R2]>>
17 ]>;
18
19 //===----------------------------------------------------------------------===//
20 // SystemZ Argument Calling Conventions
21 //===----------------------------------------------------------------------===//
22 def CC_SystemZ : CallingConv<[
23 // Promote i8/i16/i32 arguments to i64.
24 CCIfType<[i8, i16, i32], CCPromoteToType>,
25
26 // The first 5 integer arguments of non-varargs functions are passed in
27 // integer registers.
28 // FIXME: Check stuff for varagrs
29 CCIfNotVarArg
30 CCAssignToReg<[R2, R3, R4, R5, R6]>>>,
31
32 // Integer values get stored in stack slots that are 8 bytes in
33 // size and 8-byte aligned.
34 CCIfType<[i64], CCAssignToStack<8, 8>>
35 ]>;
0 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the SystemZ target.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZ.h"
14 #include "SystemZISelLowering.h"
15 #include "SystemZTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 using namespace llvm;
31
32 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
33 /// instructions for SelectionDAG operations.
34 ///
35 namespace {
36 class SystemZDAGToDAGISel : public SelectionDAGISel {
37 SystemZTargetLowering &Lowering;
38 const SystemZSubtarget &Subtarget;
39
40 public:
41 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
42 : SelectionDAGISel(TM, OptLevel),
43 Lowering(*TM.getTargetLowering()),
44 Subtarget(*TM.getSubtargetImpl()) { }
45
46 virtual void InstructionSelect();
47
48 virtual const char *getPassName() const {
49 return "SystemZ DAG->DAG Pattern Instruction Selection";
50 }
51
52 // Include the pieces autogenerated from the target description.
53 #include "SystemZGenDAGISel.inc"
54
55 private:
56 SDNode *Select(SDValue Op);
57
58 #ifndef NDEBUG
59 unsigned Indent;
60 #endif
61 };
62 } // end anonymous namespace
63
64 /// createSystemZISelDag - This pass converts a legalized DAG into a
65 /// SystemZ-specific DAG, ready for instruction scheduling.
66 ///
67 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
68 CodeGenOpt::Level OptLevel) {
69 return new SystemZDAGToDAGISel(TM, OptLevel);
70 }
71
72
73 /// InstructionSelect - This callback is invoked by
74 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
75 void SystemZDAGToDAGISel::InstructionSelect() {
76 DEBUG(BB->dump());
77
78 // Codegen the basic block.
79 #ifndef NDEBUG
80 DOUT << "===== Instruction selection begins:\n";
81 Indent = 0;
82 #endif
83 SelectRoot(*CurDAG);
84 #ifndef NDEBUG
85 DOUT << "===== Instruction selection ends:\n";
86 #endif
87
88 CurDAG->RemoveDeadNodes();
89 }
90
91 SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
92 SDNode *Node = Op.getNode();
93 DebugLoc dl = Op.getDebugLoc();
94
95 // Dump information about the Node being selected
96 #ifndef NDEBUG
97 DOUT << std::string(Indent, ' ') << "Selecting: ";
98 DEBUG(Node->dump(CurDAG));
99 DOUT << "\n";
100 Indent += 2;
101 #endif
102
103 // If we have a custom node, we already have selected!
104 if (Node->isMachineOpcode()) {
105 #ifndef NDEBUG
106 DOUT << std::string(Indent-2, ' ') << "== ";
107 DEBUG(Node->dump(CurDAG));
108 DOUT << "\n";
109 Indent -= 2;
110 #endif
111 return NULL;
112 }
113
114 // Select the default instruction
115 SDNode *ResNode = SelectCode(Op);
116
117 #ifndef NDEBUG
118 DOUT << std::string(Indent-2, ' ') << "=> ";
119 if (ResNode == NULL || ResNode == Op.getNode())
120 DEBUG(Op.getNode()->dump(CurDAG));
121 else
122 DEBUG(ResNode->dump(CurDAG));
123 DOUT << "\n";
124 Indent -= 2;
125 #endif
126
127 return ResNode;
128 }
0 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SystemZTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "systemz-lower"
14
15 #include "SystemZISelLowering.h"
16 #include "SystemZ.h"
17 #include "SystemZTargetMachine.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/VectorExtras.h"
35 using namespace llvm;
36
37 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
38 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
39
40 // Set up the register classes.
41 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
42
43 // Compute derived properties from the register classes
44 computeRegisterProperties();
45
46 // Provide all sorts of operation actions
47
48 setStackPointerRegisterToSaveRestore(SystemZ::R15);
49 setSchedulingPreference(SchedulingForLatency);
50 }
51
52 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
53 switch (Op.getOpcode()) {
54 default:
55 assert(0 && "unimplemented operand");
56 return SDValue();
57 }
58 }
59
60 //===----------------------------------------------------------------------===//
61 // Calling Convention Implementation
62 //===----------------------------------------------------------------------===//
63
64 #include "SystemZGenCallingConv.inc"
65
66 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
67 switch (Opcode) {
68 default: return NULL;
69 }
70 }
71
0 //==-- SystemZISelLowering.h - SystemZ DAG Lowering Interface ----*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
15 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
16
17 #include "SystemZ.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
20
21 namespace llvm {
22 namespace SystemZISD {
23 enum {
24 FIRST_NUMBER = ISD::BUILTIN_OP_END
25 };
26 }
27
28 class SystemZSubtarget;
29 class SystemZTargetMachine;
30
31 class SystemZTargetLowering : public TargetLowering {
32 public:
33 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
34
35 /// LowerOperation - Provide custom lowering hooks for some operations.
36 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
37
38 /// getTargetNodeName - This method returns the name of a target specific
39 /// DAG node.
40 virtual const char *getTargetNodeName(unsigned Opcode) const;
41
42 private:
43 const SystemZSubtarget &Subtarget;
44 const SystemZTargetMachine &TM;
45 };
46 } // namespace llvm
47
48 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
0 //===- SystemZInstrFormats.td - SystemZ Instruction Formats ----*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 class InstSystemZ pattern> : Instruction {
10 let Namespace = "SystemZ";
11
12 dag OutOperandList = outs;
13 dag InOperandList = ins;
14 let AsmString = asmstr;
15 let Pattern = pattern;
16 }
17
18 //===----------------------------------------------------------------------===//
19 // E format
20 //===----------------------------------------------------------------------===//
21
22 class F_E opcode,
23 dag outs, dag ins, string asmstr, list pattern>
24 : InstSystemZ {
25
26 field bits<16> Inst;
27
28 let Inst{15-0} = opcode;
29 }
30
31 //===----------------------------------------------------------------------===//
32 // I format
33 //===----------------------------------------------------------------------===//
34
35 class F_I opcode,
36 dag outs, dag ins, string asmstr, list pattern>
37 : InstSystemZ {
38
39 field bits<48> Inst;
40
41 let Inst{47-32} = opcode;
42 //let Inst{31-0} = simm32;
43 }
44
45 //===----------------------------------------------------------------------===//
46 // RR format
47 //===----------------------------------------------------------------------===//
48
49 class F_RR opcode,
50 dag outs, dag ins, string asmstr, list pattern>
51 : InstSystemZ {
52
53 field bits<16> Inst;
54
55 let Inst{15-8} = opcode;
56 }
57
58 //===----------------------------------------------------------------------===//
59 // RRE format
60 //===----------------------------------------------------------------------===//
61
62 class F_RRE opcode,
63 dag outs, dag ins, string asmstr, list pattern>
64 : InstSystemZ {
65
66 field bits<32> Inst;
67
68 let Inst{31-16} = opcode;
69 let Inst{15-8} = 0;
70 //let Inst{7-4} = r1;
71 //let Inst{3-0} = r2;
72 }
73
74 //===----------------------------------------------------------------------===//
75 // RRF format (1)
76 //===----------------------------------------------------------------------===//
77
78 class F_RRF_1 opcode,
79 dag outs, dag ins, string asmstr, list pattern>
80 : InstSystemZ {
81
82 field bits<32> Inst;
83
84 let Inst{31-16} = opcode;
85 //let Inst{15-12} = r1;
86 let Inst{11-8} = 0;
87 //let Inst{7-4} = r3;
88 //let Inst{3-0} = r2;
89 }
90
91 //===----------------------------------------------------------------------===//
92 // RRF format (2)
93 //===----------------------------------------------------------------------===//
94
95 class F_RRF_2 opcode,
96 dag outs, dag ins, string asmstr, list pattern>
97 : InstSystemZ {
98
99 field bits<32> Inst;
100
101 let Inst{31-16} = opcode;
102 //let Inst{15-12} = m3;
103 let Inst{11-8} = 0;
104 //let Inst{7-4} = r1;
105 //let Inst{3-0} = r2;
106 }
107
108 //===----------------------------------------------------------------------===//
109 // RRF format (3)
110 //===----------------------------------------------------------------------===//
111
112 class F_RRF_3 opcode,
113 dag outs, dag ins, string asmstr, list pattern>
114 : InstSystemZ {
115
116 field bits<32> Inst;
117
118 let Inst{31-16} = opcode;
119 //let Inst{15-12} = r3;
120 //let Inst{11-8} = m4;
121 //let Inst{7-4} = r1;
122 //let Inst{3-0} = r2;
123 }
124
125 //===----------------------------------------------------------------------===//
126 // RX format
127 //===----------------------------------------------------------------------===//
128
129 class F_RX opcode,
130 dag outs, dag ins, string asmstr, list pattern>
131 : InstSystemZ {
132
133 field bits<32> Inst;
134
135 let Inst{31-24} = opcode;
136 //let Inst{23-20} = r1;
137 //let Inst{19-16} = x2;
138 //let Inst{15-12} = b2;
139 //let Inst{11-0} = udisp12;
140 }
141
142 //===----------------------------------------------------------------------===//
143 // RXE format
144 //===----------------------------------------------------------------------===//
145
146 class F_RXE opcode,
147 dag outs, dag ins, string asmstr, list pattern>
148 : InstSystemZ {
149
150 field bits<48> Inst;
151
152 let Inst{47-40} = opcode;
153 //let Inst{39-36} = r1;
154 //let Inst{35-32} = x2;
155 //let Inst{31-28} = b2;
156 //let Inst{27-16} = udisp12;
157 let Inst{15-8} = 0;
158 //let Inst{7-0} = op2;
159 }
160
161 //===----------------------------------------------------------------------===//
162 // RXF format
163 //===----------------------------------------------------------------------===//
164
165 class F_RXF opcode,
166 dag outs, dag ins, string asmstr, list pattern>
167 : InstSystemZ {
168
169 field bits<48> Inst;
170
171 let Inst{47-40} = opcode;
172 //let Inst{39-36} = r3;
173 //let Inst{35-32} = x2;
174 //let Inst{31-28} = b2;
175 //let Inst{27-16} = udisp12;
176 //let Inst{15-11} = r1;
177 let Inst{11-8} = 0;
178 //let Inst{7-0} = op2;
179 }
180
181 //===----------------------------------------------------------------------===//
182 // RXY format
183 //===----------------------------------------------------------------------===//
184
185 class F_RXY opcode,
186 dag outs, dag ins, string asmstr, list pattern>
187 : InstSystemZ {
188
189 field bits<48> Inst;
190
191 let Inst{47-40} = opcode;
192 //let Inst{39-36} = r1;
193 //let Inst{35-32} = x2;
194 //let Inst{31-28} = b2;
195 //let Inst{27-8} = sdisp20;
196 //let Inst{7-0} = op2;
197 }
198
199 //===----------------------------------------------------------------------===//
200 // RS format (1)
201 //===----------------------------------------------------------------------===//
202
203 class F_RS_1 opcode,
204 dag outs, dag ins, string asmstr, list pattern>
205 : InstSystemZ {
206
207 field bits<32> Inst;
208
209 let Inst{31-24} = opcode;
210 //let Inst{23-20} = r1;
211 //let Inst{19-16} = r3;
212 //let Inst{15-12} = b2;
213 //let Inst{11-0} = udisp12;
214 }
215
216 //===----------------------------------------------------------------------===//
217 // RS format (2)
218 //===----------------------------------------------------------------------===//
219
220 class F_RS_2 opcode,
221 dag outs, dag ins, string asmstr, list pattern>
222 : InstSystemZ {
223
224 field bits<32> Inst;
225
226 let Inst{31-24} = opcode;
227 //let Inst{23-20} = r1;
228 //let Inst{19-16} = m3;
229 //let Inst{15-12} = b2;
230 //let Inst{11-0} = udisp12;
231 }
232
233 //===----------------------------------------------------------------------===//
234 // RS format (3)
235 //===----------------------------------------------------------------------===//
236
237 class F_RS_3 opcode,
238 dag outs, dag ins, string asmstr, list pattern>
239 : InstSystemZ {
240
241 field bits<32> Inst;
242
243 let Inst{31-24} = opcode;
244 //let Inst{23-20} = r1;
245 let Inst{19-16} = 0;
246 //let Inst{15-12} = b2;
247 //let Inst{11-0} = udisp12;
248 }
249
250 //===----------------------------------------------------------------------===//
251 // RSY format (1)
252 //===----------------------------------------------------------------------===//
253
254 class F_RSY_1 opcode,
255 dag outs, dag ins, string asmstr, list pattern>
256 : InstSystemZ {
257
258 field bits<48> Inst;
259
260 let Inst{47-40} = opcode;
261 //let Inst{39-36} = r1;
262 //let Inst{35-32} = r3;
263 //let Inst{31-28} = b2;
264 //let Inst{27-8} = sdisp20;
265 //let Inst{7-0} = op2;
266 }
267
268 //===----------------------------------------------------------------------===//
269 // RSY format (2)
270 //===----------------------------------------------------------------------===//
271
272 class F_RSY_2 opcode,
273 dag outs, dag ins, string asmstr, list pattern>
274 : InstSystemZ {
275
276 field bits<48> Inst;
277
278 let Inst{47-40} = opcode;
279 //let Inst{39-36} = r1;
280 //let Inst{35-32} = m3;
281 //let Inst{31-28} = b2;
282 //let Inst{27-8} = sdisp20;
283 //let Inst{7-0} = op2;
284 }
285
286 //===----------------------------------------------------------------------===//
287 // RSL format
288 //===----------------------------------------------------------------------===//
289
290 class F_RSL opcode,
291 dag outs, dag ins, string asmstr, list pattern>
292 : InstSystemZ {
293
294 field bits<48> Inst;
295
296 let Inst{47-40} = opcode;
297 //let Inst{39-36} = ll;
298 let Inst{35-32} = 0;
299 //let Inst{31-28} = b1;
300 //let Inst{27-16} = udisp12;
301 let Inst{15-8} = 0;
302 //let Inst{7-0} = op2;
303 }
304
305 //===----------------------------------------------------------------------===//
306 // RSI format
307 //===----------------------------------------------------------------------===//
308
309 class F_RSI opcode,
310 dag outs, dag ins, string asmstr, list pattern>
311 : InstSystemZ {
312
313 field bits<32> Inst;
314
315 let Inst{31-24} = opcode;
316 //let Inst{23-20} = r1;
317 //let Inst{19-16} = r3;
318 //let Inst{15-0} = simm16;
319 }
320
321 //===----------------------------------------------------------------------===//
322 // RI format
323 //===----------------------------------------------------------------------===//
324
325 class F_RI opcode,
326 dag outs, dag ins, string asmstr, list pattern>
327 : InstSystemZ {
328
329 field bits<32> Inst;
330
331 let Inst{31-24} = opcode;
332 //let Inst{23-20} = r1;
333 //let Inst{19-16} = op2;
334 //let Inst{15-0} = simm16;
335 }
336
337 //===----------------------------------------------------------------------===//
338 // RIE format
339 //===----------------------------------------------------------------------===//
340
341 class F_RIE opcode,
342 dag outs, dag ins, string asmstr, list pattern>
343 : InstSystemZ {
344
345 field bits<48> Inst;
346
347 let Inst{47-40} = opcode;
348 //let Inst{39-36} = r1;
349 //let Inst{35-32} = r2;
350 //let Inst{31-16} = simm16;
351 let Inst{15-8} = 0;
352 //let Inst{7-0} = op2;
353 }
354
355 //===----------------------------------------------------------------------===//
356 // RIL format (1)
357 //===----------------------------------------------------------------------===//
358
359 class F_RIL_1 opcode,
360 dag outs, dag ins, string asmstr, list pattern>
361 : InstSystemZ {
362
363 field bits<48> Inst;
364
365 let Inst{47-40} = opcode;
366 //let Inst{39-36} = r1;
367 //let Inst{35-32} = op2;
368 //let Inst{31-0} = simm32;
369 }
370
371 //===----------------------------------------------------------------------===//
372 // RIL format (2)
373 //===----------------------------------------------------------------------===//
374
375 class F_RIL_2 opcode,
376 dag outs, dag ins, string asmstr, list pattern>
377 : InstSystemZ {
378
379 field bits<48> Inst;
380
381 let Inst{47-40} = opcode;
382 //let Inst{39-36} = m1;
383 //let Inst{35-32} = op2;
384 //let Inst{31-0} = simm32;
385 }
386
387 //===----------------------------------------------------------------------===//
388 // SI format
389 //===----------------------------------------------------------------------===//
390
391 class F_SI opcode,
392 dag outs, dag ins, string asmstr, list pattern>
393 : InstSystemZ {
394
395 field bits<32> Inst;
396
397 let Inst{31-24} = opcode;
398 //let Inst{23-16} = simm8;
399 //let Inst{15-12} = b1;
400 //let Inst{11-0} = udisp12;
401 }
402
403 //===----------------------------------------------------------------------===//
404 // SIY format
405 //===----------------------------------------------------------------------===//
406
407 class F_SIY opcode,
408 dag outs, dag ins, string asmstr, list pattern>
409 : InstSystemZ {
410
411 field bits<48> Inst;
412
413 let Inst{47-40} = opcode;
414 //let Inst{39-32} = simm8;
415 //let Inst{31-28} = b1;
416 //let Inst{27-8} = sdisp20;
417 //let Inst{7-0} = op2;
418 }
419
420 //===----------------------------------------------------------------------===//
421 // S format
422 //===----------------------------------------------------------------------===//
423
424 class F_S opcode,
425 dag outs, dag ins, string asmstr, list pattern>
426 : InstSystemZ {
427
428 field bits<32> Inst;
429
430 let Inst{31-16} = opcode;
431 //let Inst{15-12} = b2;
432 //let Inst{11-0} = udisp12;
433 }
434
435 //===----------------------------------------------------------------------===//
436 // SS format (1)
437 //===----------------------------------------------------------------------===//
438
439 class F_SS_1 opcode,
440 dag outs, dag ins, string asmstr, list pattern>
441 : InstSystemZ {
442
443 field bits<48> Inst;
444
445 let Inst{47-40} = opcode;
446 //let Inst{39-32} = ll;
447 //let Inst{31-28} = b1;
448 //let Inst{27-16} = udisp12;
449 //let Inst{15-12} = b2;
450 //let Inst{11-0} = udisp12_2;
451 }
452
453 //===----------------------------------------------------------------------===//
454 // SS format (2)
455 //===----------------------------------------------------------------------===//
456
457 class F_SS_2 opcode,
458 dag outs, dag ins, string asmstr, list pattern>
459 : InstSystemZ {
460
461 field bits<48> Inst;
462
463 let Inst{47-40} = opcode;
464 //let Inst{39-36} = l1;
465 //let Inst{35-32} = l2;
466 //let Inst{31-28} = b1;
467 //let Inst{27-16} = udisp12;
468 //let Inst{15-12} = b2;
469 //let Inst{11-0} = udisp12_2;
470 }
471
472 //===----------------------------------------------------------------------===//
473 // SS format (3)
474 //===----------------------------------------------------------------------===//
475
476 class F_SS_3 opcode,
477 dag outs, dag ins, string asmstr, list pattern>
478 : InstSystemZ {
479
480 field bits<48> Inst;
481
482 let Inst{47-40} = opcode;
483 //let Inst{39-36} = r1;
484 //let Inst{35-32} = r3;
485 //let Inst{31-28} = b1;
486 //let Inst{27-16} = udisp12;
487 //let Inst{15-12} = b2;
488 //let Inst{11-0} = udisp12_2;
489 }
490
491 //===----------------------------------------------------------------------===//
492 // SS format (4)
493 //===----------------------------------------------------------------------===//
494
495 class F_SS_4 opcode,
496 dag outs, dag ins, string asmstr, list pattern>
497 : InstSystemZ {
498
499 field bits<48> Inst;
500
501 let Inst{47-40} = opcode;
502 //let Inst{39-36} = r1;
503 //let Inst{35-32} = r3;
504 //let Inst{31-28} = b2;
505 //let Inst{27-16} = udisp12_2;
506 //let Inst{15-12} = b4;
507 //let Inst{11-0} = udisp12_4;
508 }
509
510 //===----------------------------------------------------------------------===//
511 // SSE format
512 //===----------------------------------------------------------------------===//
513
514 class F_SSE opcode,
515 dag outs, dag ins, string asmstr, list pattern>
516 : InstSystemZ {
517
518 field bits<48> Inst;
519
520 let Inst{47-32} = opcode;
521 //let Inst{31-28} = b1;
522 //let Inst{27-16} = udisp12;
523 //let Inst{15-12} = b2;
524 //let Inst{11-0} = udisp12_2;
525 }
526
527 //===----------------------------------------------------------------------===//
528 // Pseudo instructions
529 //===----------------------------------------------------------------------===//
530
531 class Pseudo pattern>
532 : InstSystemZ {
533 }
0 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZ.h"
14 #include "SystemZInstrInfo.h"
15 #include "SystemZMachineFunctionInfo.h"
16 #include "SystemZTargetMachine.h"
17 #include "SystemZGenInstrInfo.inc"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23
24 using namespace llvm;
25
26 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
27 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
28 RI(tm, *this), TM(tm) {}
29
30 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
31 MachineBasicBlock::iterator MI,
32 unsigned SrcReg, bool isKill, int FrameIdx,
33 const TargetRegisterClass *RC) const {
34 assert(0 && "Cannot store this register to stack slot!");
35 }
36
37 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 unsigned DestReg, int FrameIdx,
40 const TargetRegisterClass *RC) const{
41 assert(0 && "Cannot store this register to stack slot!");
42 }
43
44 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator I,
46 unsigned DestReg, unsigned SrcReg,
47 const TargetRegisterClass *DestRC,
48 const TargetRegisterClass *SrcRC) const {
49 return false;
50 }
51
52 bool
53 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
54 unsigned &SrcReg, unsigned &DstReg,
55 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
56 return false;
57 }
58
59 bool
60 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 const std::vector &CSI) const {
63 return false;
64 }
65
66 bool
67 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator MI,
69 const std::vector &CSI) const {
70 return false;
71 }
72
73 unsigned
74 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
75 MachineBasicBlock *FBB,
76 const SmallVectorImpl &Cond) const {
77 assert(0 && "Implement branches!");
78
79 return 0;
80 }
0 //===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
14 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
15
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "SystemZRegisterInfo.h"
18
19 namespace llvm {
20
21 class SystemZTargetMachine;
22
23 class SystemZInstrInfo : public TargetInstrInfoImpl {
24 const SystemZRegisterInfo RI;
25 SystemZTargetMachine &TM;
26 public:
27 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
28
29 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
30 /// such, whenever a client has an instance of instruction info, it should
31 /// always be able to get register info as well (through this method).
32 ///
33 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
34
35 bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
36 unsigned DestReg, unsigned SrcReg,
37 const TargetRegisterClass *DestRC,
38 const TargetRegisterClass *SrcRC) const;
39
40 bool isMoveInstr(const MachineInstr& MI,
41 unsigned &SrcReg, unsigned &DstReg,
42 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
43
44 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MI,
46 unsigned SrcReg, bool isKill,
47 int FrameIndex,
48 const TargetRegisterClass *RC) const;
49 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI,
51 unsigned DestReg, int FrameIdx,
52 const TargetRegisterClass *RC) const;
53
54 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI,
56 const std::vector &CSI) const;
57 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 const std::vector &CSI) const;
60
61 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
62 MachineBasicBlock *FBB,
63 const SmallVectorImpl &Cond) const;
64
65 };
66
67 }
68
69 #endif
0 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the SystemZ instructions in TableGen format.
10 //
11 //===----------------------------------------------------------------------===//
12
13 include "SystemZInstrFormats.td"
14
15 let neverHasSideEffects = 1 in
16 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
0 //==- SystemZMachineFuctionInfo.h - SystemZ machine function info -*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares SystemZ-specific per-machine-function information.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SYSTEMZMACHINEFUNCTIONINFO_H
14 #define SYSTEMZMACHINEFUNCTIONINFO_H
15
16 #include "llvm/CodeGen/MachineFunction.h"
17
18 namespace llvm {
19
20 /// SystemZMachineFunctionInfo - This class is derived from MachineFunction and
21 /// contains private SystemZ target-specific information for each MachineFunction.
22 class SystemZMachineFunctionInfo : public MachineFunctionInfo {
23 /// CalleeSavedFrameSize - Size of the callee-saved register portion of the
24 /// stack frame in bytes.
25 unsigned CalleeSavedFrameSize;
26
27 public:
28 SystemZMachineFunctionInfo() : CalleeSavedFrameSize(0) {}
29
30 SystemZMachineFunctionInfo(MachineFunction &MF) : CalleeSavedFrameSize(0) {}
31
32 unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; }
33 void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; }
34 };
35
36 } // End llvm namespace
37
38 #endif
0 //===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZ.h"
14 #include "SystemZRegisterInfo.h"
15 #include "SystemZSubtarget.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/ADT/BitVector.h"
22 using namespace llvm;
23
24 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
25 const TargetInstrInfo &tii)
26 : SystemZGenRegisterInfo(SystemZ::NOP, SystemZ::NOP),
27 TM(tm), TII(tii) {
28 }
29
30 const unsigned*
31 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
32 static const unsigned CalleeSavedRegs[] = {
33 SystemZ::R6, SystemZ::R7, SystemZ::R8, SystemZ::R9,
34 SystemZ::R10, SystemZ::R11, SystemZ::R12, SystemZ::R13,
35 SystemZ::F1, SystemZ::F3, SystemZ::F5, SystemZ::F7,
36 0
37 };
38
39 return CalleeSavedRegs;
40 }
41
42 const TargetRegisterClass* const*
43 SystemZRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
44 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
45 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
46 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
47 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
48 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
49 &SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
50 &SystemZ::FP64RegClass, &SystemZ::FP64RegClass, 0
51 };
52 return CalleeSavedRegClasses;
53 }
54
55 BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
56 BitVector Reserved(getNumRegs());
57 if (hasFP(MF))
58 Reserved.set(SystemZ::R11);
59 Reserved.set(SystemZ::R14);
60 Reserved.set(SystemZ::R15);
61 return Reserved;
62 }
63
64 // needsFP - Return true if the specified function should have a dedicated frame
65 // pointer register. This is true if the function has variable sized allocas or
66 // if frame pointer elimination is disabled.
67 //
68 bool SystemZRegisterInfo::hasFP(const MachineFunction &MF) const {
69 const MachineFrameInfo *MFI = MF.getFrameInfo();
70 return NoFramePointerElim || MFI->hasVarSizedObjects();
71 }
72
73 void SystemZRegisterInfo::
74 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I) const {
76 assert(0 && "Not implemented yet!");
77 }
78
79 void SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
80 int SPAdj, RegScavenger *RS) const {
81 assert(0 && "Not implemented yet!");
82 }
83
84 void SystemZRegisterInfo::emitPrologue(MachineFunction &MF) const {
85 // Nothing here yet
86 }
87
88 void SystemZRegisterInfo::emitEpilogue(MachineFunction &MF,
89 MachineBasicBlock &MBB) const {
90 // Nothing here yet
91 }
92
93 unsigned SystemZRegisterInfo::getRARegister() const {
94 assert(0 && "What is the return address register");
95 return 0;
96 }
97
98 unsigned SystemZRegisterInfo::getFrameRegister(MachineFunction &MF) const {
99 assert(0 && "What is the frame register");
100 return 0;
101 }
102
103 unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
104 assert(0 && "What is the exception register");
105 return 0;
106 }
107
108 unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
109 assert(0 && "What is the exception handler register");
110 return 0;
111 }
112
113 int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
114 assert(0 && "What is the dwarf register number");
115 return -1;
116 }
117
118 #include "SystemZGenRegisterInfo.inc"
0 //===- SystemZRegisterInfo.h - SystemZ Register Information Impl ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SystemZREGISTERINFO_H
14 #define SystemZREGISTERINFO_H
15
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "SystemZGenRegisterInfo.h.inc"
18
19 namespace llvm {
20
21 class SystemZSubtarget;
22 class TargetInstrInfo;
23 class Type;
24
25 struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
26 SystemZTargetMachine &TM;
27 const TargetInstrInfo &TII;
28
29 SystemZRegisterInfo(SystemZTargetMachine &tm, const TargetInstrInfo &tii);
30
31 /// Code Generation virtual methods...
32 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
33
34 const TargetRegisterClass* const* getCalleeSavedRegClasses(
35 const MachineFunction *MF = 0) const;
36
37 BitVector getReservedRegs(const MachineFunction &MF) const;
38
39 bool hasFP(const MachineFunction &MF) const;
40
41 void eliminateCallFramePseudoInstr(MachineFunction &MF,
42 MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator I) const;
44
45 void eliminateFrameIndex(MachineBasicBlock::iterator II,
46 int SPAdj, RegScavenger *RS = NULL) const;
47
48 void emitPrologue(MachineFunction &MF) const;
49 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
50
51 // Debug information queries.
52 unsigned getRARegister() const;
53 unsigned getFrameRegister(MachineFunction &MF) const;
54
55 // Exception handling queries.
56 unsigned getEHExceptionRegister() const;
57 unsigned getEHHandlerRegister() const;
58
59 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
60 };
61
62 } // end namespace llvm
63
64 #endif
0 //===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 class SystemZReg : Register {
13 let Namespace = "SystemZ";
14 }
15
16 // We identify all our registers with a 4-bit ID, for consistency's sake.
17
18 // GPR - One of the 16 64-bit general-purpose registers
19 class GPR num, string n> : SystemZReg {
20 field bits<4> Num = num;
21 }
22
23 // FPR - One of the 16 64-bit floating-point registers
24 class FPR num, string n> : SystemZReg {
25 field bits<4> Num = num;
26 }
27
28 // General-purpose registers
29 def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>;
30 def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>;
31 def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>;
32 def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>;
33 def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>;
34 def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>;
35 def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>;
36 def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>;
37 def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>;
38 def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>;
39 def R10 : GPR<10, "r10">, DwarfRegNum<[10]>;
40 def R11 : GPR<11, "r11">, DwarfRegNum<[11]>;
41 def R12 : GPR<12, "r12">, DwarfRegNum<[12]>;
42 def R13 : GPR<13, "r13">, DwarfRegNum<[13]>;
43 def R14 : GPR<14, "r14">, DwarfRegNum<[14]>;
44 def R15 : GPR<15, "r15">, DwarfRegNum<[15]>;
45
46 // Floating-point registers
47 def F0 : FPR< 0, "f0">, DwarfRegNum<[16]>;
48 def F1 : FPR< 1, "f1">, DwarfRegNum<[17]>;
49 def F2 : FPR< 2, "f2">, DwarfRegNum<[18]>;
50 def F3 : FPR< 3, "f3">, DwarfRegNum<[19]>;
51 def F4 : FPR< 4, "f4">, DwarfRegNum<[20]>;
52 def F5 : FPR< 5, "f5">, DwarfRegNum<[21]>;
53 def F6 : FPR< 6, "f6">, DwarfRegNum<[22]>;
54 def F7 : FPR< 7, "f7">, DwarfRegNum<[23]>;
55 def F8 : FPR< 8, "f8">, DwarfRegNum<[24]>;
56 def F9 : FPR< 9, "f9">, DwarfRegNum<[25]>;
57 def F10 : FPR<10, "f10">, DwarfRegNum<[26]>;
58 def F11 : FPR<11, "f11">, DwarfRegNum<[27]>;
59 def F12 : FPR<12, "f12">, DwarfRegNum<[28]>;
60 def F13 : FPR<13, "f13">, DwarfRegNum<[29]>;
61 def F14 : FPR<14, "f14">, DwarfRegNum<[30]>;
62 def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
63
64 /// Register classes
65 def GR64 : RegisterClass<"SystemZ", [i64], 16,
66 // Volatile registers
67 [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R12, R13,
68 // Frame pointer, sometimes allocable
69 R11,
70 // Volatile, but not allocable
71 R14, R15]>
72 {
73 let MethodProtos = [{
74 iterator allocation_order_end(const MachineFunction &MF) const;
75 }];
76 let MethodBodies = [{
77 GR64Class::iterator
78 GR64Class::allocation_order_end(const MachineFunction &MF) const {
79 const TargetMachine &TM = MF.getTarget();
80 const TargetRegisterInfo *RI = TM.getRegisterInfo();
81 // Depending on whether the function uses frame pointer or not, last 2 or 3
82 // registers on the list above are reserved
83 if (RI->hasFP(MF))
84 return end()-3;
85 else
86 return end()-2;
87 }
88 }];
89 }
90
91 def FP64 : RegisterClass<"SystemZ", [f64], 64,
92 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>;
0 //===- SystemZSubtarget.cpp - SystemZ Subtarget Information -------*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SystemZ specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZSubtarget.h"
14 #include "SystemZ.h"
15 #include "SystemZGenSubtarget.inc"
16 #include "llvm/Target/TargetMachine.h"
17
18 using namespace llvm;
19
20 SystemZSubtarget::SystemZSubtarget(const TargetMachine &TM, const Module &M,
21 const std::string &FS) {
22 std::string CPU = "generic";
23
24 // Parse features string.
25 ParseSubtargetFeatures(FS, CPU);
26 }
0 //==-- SystemZSubtarget.h - Define Subtarget for the SystemZ ---*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the SystemZ specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_TARGET_SystemZ_SUBTARGET_H
14 #define LLVM_TARGET_SystemZ_SUBTARGET_H
15
16 #include "llvm/Target/TargetSubtarget.h"
17
18 #include
19
20 namespace llvm {
21 class Module;
22 class TargetMachine;
23
24 class SystemZSubtarget : public TargetSubtarget {
25 bool DummyFeature;
26 public:
27 /// This constructor initializes the data members to match that
28 /// of the specified module.
29 ///
30 SystemZSubtarget(const TargetMachine &TM, const Module &M,
31 const std::string &FS);
32
33 /// ParseSubtargetFeatures - Parses features string setting specified
34 /// subtarget options. Definition of function is auto generated by tblgen.
35 void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
36 };
37 } // End llvm namespace
38
39 #endif // LLVM_TARGET_SystemZ_SUBTARGET_H
0 //===-- SystemZTargetAsmInfo.cpp - SystemZ asm properties -----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declarations of the SystemZTargetAsmInfo properties.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZTargetAsmInfo.h"
14 #include "SystemZTargetMachine.h"
15
16 using namespace llvm;
17
18 SystemZTargetAsmInfo::SystemZTargetAsmInfo(const SystemZTargetMachine &TM)
19 : ELFTargetAsmInfo(TM) {
20 AlignmentIsInBytes = false;
21 }
0 //====-- SystemZTargetAsmInfo.h - SystemZ asm properties -------*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the SystemZTargetAsmInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef SystemZTARGETASMINFO_H
14 #define SystemZTARGETASMINFO_H
15
16 #include "llvm/Target/TargetAsmInfo.h"
17 #include "llvm/Target/ELFTargetAsmInfo.h"
18
19 namespace llvm {
20
21 // Forward declaration.
22 class SystemZTargetMachine;
23
24 struct SystemZTargetAsmInfo : public ELFTargetAsmInfo {
25 explicit SystemZTargetAsmInfo(const SystemZTargetMachine &TM);
26 };
27
28 } // namespace llvm
29
30 #endif
0 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SystemZTargetAsmInfo.h"
13 #include "SystemZTargetMachine.h"
14 #include "SystemZ.h"
15 #include "llvm/Module.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Target/TargetMachineRegistry.h"
18 using namespace llvm;
19
20 /// SystemZTargetMachineModule - Note that this is used on hosts that
21 /// cannot link in a library unless there are references into the
22 /// library. In particular, it seems that it is not possible to get
23 /// things to work on Win32 without this. Though it is unused, do not
24 /// remove it.
25 extern "C" int SystemZTargetMachineModule;
26 int SystemZTargetMachineModule = 0;
27
28 // Register the target.
29 static RegisterTarget
30 X("systemz", "SystemZ [experimental]");
31
32 const TargetAsmInfo *SystemZTargetMachine::createTargetAsmInfo() const {
33 // FIXME: Handle Solaris subtarget someday :)
34 return new SystemZTargetAsmInfo(*this);
35 }
36
37 /// SystemZTargetMachine ctor - Create an ILP64 architecture model
38 ///
39 SystemZTargetMachine::SystemZTargetMachine(const Module &M, const std::string &FS)
40 : Subtarget(*this, M, FS),
41 DataLayout("E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"),
42 InstrInfo(*this), TLInfo(*this),
43 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
44 }
45
46 bool SystemZTargetMachine::addInstSelector(PassManagerBase &PM,
47 CodeGenOpt::Level OptLevel) {
48 // Install an instruction selector.
49 PM.add(createSystemZISelDag(*this, OptLevel));
50 return false;
51 }
52
53 bool SystemZTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
54 CodeGenOpt::Level OptLevel,
55 bool Verbose,
56 raw_ostream &Out) {
57 // Output assembly language.
58 PM.add(createSystemZCodePrinterPass(Out, *this, OptLevel, Verbose));
59 return false;
60 }
61
62 unsigned SystemZTargetMachine::getModuleMatchQuality(const Module &M) {
63 std::string TT = M.getTargetTriple();
64
65 // We strongly match s390x
66 if (TT.size() >= 5 && TT[0] == 's' && TT[1] == '3' && TT[2] == '9' &&
67 TT[3] == '0' && TT[4] == 'x')
68 return 20;
69
70 return 0;
71 }
0 //==- SystemZTargetMachine.h - Define TargetMachine for SystemZ ---*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the SystemZ specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12
13
14 #ifndef LLVM_TARGET_SYSTEMZ_TARGETMACHINE_H
15 #define LLVM_TARGET_SYSTEMZ_TARGETMACHINE_H
16
17 #include "SystemZInstrInfo.h"
18 #include "SystemZISelLowering.h"
19 #include "SystemZRegisterInfo.h"
20 #include "SystemZSubtarget.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24
25 namespace llvm {
26
27 /// SystemZTargetMachine
28 ///
29 class SystemZTargetMachine : public LLVMTargetMachine {
30 SystemZSubtarget Subtarget;
31 const TargetData DataLayout; // Calculates type size & alignment
32 SystemZInstrInfo InstrInfo;
33 SystemZTargetLowering TLInfo;
34
35 // SystemZ does not have any call stack frame, therefore not having
36 // any SystemZ specific FrameInfo class.
37 TargetFrameInfo FrameInfo;
38
39 protected:
40 virtual const TargetAsmInfo *createTargetAsmInfo() const;
41
42 public:
43 SystemZTargetMachine(const Module &M, const std::string &FS);
44
45 virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
46 virtual const SystemZInstrInfo *getInstrInfo() const { return &InstrInfo; }
47 virtual const TargetData *getTargetData() const { return &DataLayout;}
48 virtual const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
49
50 virtual const TargetRegisterInfo *getRegisterInfo() const {
51 return &InstrInfo.getRegisterInfo();
52 }
53
54 virtual SystemZTargetLowering *getTargetLowering() const {
55 return const_cast(&TLInfo);
56 }
57
58 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
59 virtual bool addAssemblyEmitter(PassManagerBase &PM,
60 CodeGenOpt::Level OptLevel, bool Verbose,
61 raw_ostream &Out);
62 static unsigned getModuleMatchQuality(const Module &M);
63 }; // SystemZTargetMachine.
64
65 } // end namespace llvm
66
67 #endif // LLVM_TARGET_SystemZ_TARGETMACHINE_H