llvm.org GIT mirror llvm / 43f589a
ARM: diagnose unpredictable IT instructions IT instructions are allowed to have the 'AL' predicate, but it must never result in an 'NV' predicated instruction. Essentially this means that all branches must be 't' rather than 'e' if the predicate is 'AL'. This patch adds a diagnostic for this during assembly (error because parsing hits an assertion if allowed to continue) and an annotation during disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335593 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 2 years ago
4 changed file(s) with 76 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
63476347
63486348 const unsigned Opcode = Inst.getOpcode();
63496349 switch (Opcode) {
6350 case ARM::t2IT: {
6351 // Encoding is unpredictable if it ever results in a notional 'NV'
6352 // predicate. Since we don't parse 'NV' directly this means an 'AL'
6353 // predicate with an "else" mask bit.
6354 unsigned Cond = Inst.getOperand(0).getImm();
6355 unsigned Mask = Inst.getOperand(1).getImm();
6356
6357 // Mask hasn't been modified to the IT instruction encoding yet so
6358 // conditions only allowing a 't' are a block of 1s starting at bit 3
6359 // followed by all 0s. Easiest way is to just list the 4 possibilities.
6360 if (Cond == ARMCC::AL && Mask != 8 && Mask != 12 && Mask != 14 &&
6361 Mask != 15)
6362 return Error(Loc, "unpredictable IT predicate sequence");
6363 break;
6364 }
63506365 case ARM::LDRD:
63516366 case ARM::LDRD_PRE:
63526367 case ARM::LDRD_POST: {
728728 // code and mask operands so that we can apply them correctly
729729 // to the subsequent instructions.
730730 if (MI.getOpcode() == ARM::t2IT) {
731
732731 unsigned Firstcond = MI.getOperand(0).getImm();
733732 unsigned Mask = MI.getOperand(1).getImm();
734733 ITBlock.setITState(Firstcond, Mask);
734
735 // An IT instruction that would give a 'NV' predicate is unpredictable.
736 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
737 CS << "unpredictable IT predicate sequence";
735738 }
736739
737740 return Result;
0 @ RUN: not llvm-mc -triple thumbv7m-apple-macho %s 2> %t.errs
1 @ RUN: FileCheck %s < %t.errs --check-prefix=CHECK-ERRS
2
3 @ CHECK-ERRS: error: unpredictable IT predicate sequence
4 @ CHECK-ERRS: ite al
5 @ CHECK-ERRS: error: unpredictable IT predicate sequence
6 @ CHECK-ERRS: itee al
7 @ CHECK-ERRS: error: unpredictable IT predicate sequence
8 @ CHECK-ERRS: itet al
9 @ CHECK-ERRS: error: unpredictable IT predicate sequence
10 @ CHECK-ERRS: itte al
11 @ CHECK-ERRS: error: unpredictable IT predicate sequence
12 @ CHECK-ERRS: ittte al
13 ite al
14 itee al
15 itet al
16 itte al
17 ittte al
18
19 @ CHECK-ERRS-NOT: error
20 it al
21 nop
22
23 itt al
24 nop
25 nop
26
27 ittt al
28 nop
29 nop
30 nop
31
32 itttt al
33 nop
34 nop
35 nop
36 nop
37
38 ite eq
39 nopeq
40 nopne
41
42 iteet hi
43 nophi
44 nopls
45 nopls
46 nophi
0 # RUN: llvm-objdump -macho -d %p/Inputs/it-nv.o | FileCheck %s
1
2 # CHECK: ite al @ unpredictable IT predicate sequence
3 # CHECK: itet al @ unpredictable IT predicate sequence
4 # CHECK: itte al @ unpredictable IT predicate sequence
5 # CHECK: ite eq{{$}}
6 # CHECK: it al{{$}}
7 # CHECK: itt al{{$}}
8 # CHECK: ittt al{{$}}
9 # CHECK: itttt al{{$}}