llvm.org GIT mirror llvm / 43dbe05
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 11 years ago
30 changed file(s) with 1599 addition(s) and 1630 deletion(s). Raw diff Collapse all Expand all
483483 unsigned DestReg,
484484 const MachineInstr *Orig) const = 0;
485485
486 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
487 /// slot into the specified machine instruction for the specified operand(s).
488 /// If this is possible, a new instruction is returned with the specified
489 /// operand folded, otherwise NULL is returned. The client is responsible for
490 /// removing the old instruction and adding the new one in the instruction
491 /// stream.
492 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
493 SmallVectorImpl &Ops,
494 int FrameIndex) const {
495 return 0;
496 }
497
498 /// foldMemoryOperand - Same as the previous version except it allows folding
499 /// of any load and store from / to any address, not just from a specific
500 /// stack slot.
501 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
502 SmallVectorImpl &Ops,
503 MachineInstr* LoadMI) const {
504 return 0;
505 }
506
507 /// canFoldMemoryOperand - Returns true if the specified load / store is
508 /// folding is possible.
509 virtual
510 bool canFoldMemoryOperand(MachineInstr *MI,
511 SmallVectorImpl &Ops) const{
512 return false;
513 }
514
515 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
516 /// a store or a load and a store into two or more instruction. If this is
517 /// possible, returns true as well as the new instructions by reference.
518 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
519 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
520 SmallVectorImpl &NewMIs) const{
521 return false;
522 }
523
524 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
525 SmallVectorImpl &NewNodes) const {
526 return false;
527 }
528
529 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
530 /// instruction after load / store are unfolded from an instruction of the
531 /// specified opcode. It returns zero if the specified unfolding is not
532 /// possible.
533 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
534 bool UnfoldLoad, bool UnfoldStore) const {
535 return 0;
536 }
537
538486 /// targetHandlesStackFrameRounding - Returns true if the target is
539487 /// responsible for rounding up the stack frame (probably at emitPrologue
540488 /// time).
2626 class TargetRegisterClass;
2727 class LiveVariables;
2828 class CalleeSavedInfo;
29 class SDNode;
30 class SelectionDAG;
2931
3032 template class SmallVectorImpl;
3133
539541 return false;
540542 }
541543
544 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
545 /// slot into the specified machine instruction for the specified operand(s).
546 /// If this is possible, a new instruction is returned with the specified
547 /// operand folded, otherwise NULL is returned. The client is responsible for
548 /// removing the old instruction and adding the new one in the instruction
549 /// stream.
550 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
551 SmallVectorImpl &Ops,
552 int FrameIndex) const {
553 return 0;
554 }
555
556 /// foldMemoryOperand - Same as the previous version except it allows folding
557 /// of any load and store from / to any address, not just from a specific
558 /// stack slot.
559 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
560 SmallVectorImpl &Ops,
561 MachineInstr* LoadMI) const {
562 return 0;
563 }
564
565 /// canFoldMemoryOperand - Returns true if the specified load / store is
566 /// folding is possible.
567 virtual
568 bool canFoldMemoryOperand(MachineInstr *MI,
569 SmallVectorImpl &Ops) const{
570 return false;
571 }
572
573 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
574 /// a store or a load and a store into two or more instruction. If this is
575 /// possible, returns true as well as the new instructions by reference.
576 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
577 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
578 SmallVectorImpl &NewMIs) const{
579 return false;
580 }
581
582 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
583 SmallVectorImpl &NewNodes) const {
584 return false;
585 }
586
587 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
588 /// instruction after load / store are unfolded from an instruction of the
589 /// specified opcode. It returns zero if the specified unfolding is not
590 /// possible.
591 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
592 bool UnfoldLoad, bool UnfoldStore) const {
593 return 0;
594 }
595
542596 /// BlockHasNoFallThrough - Return true if the specified block does not
543597 /// fall-through into its successor block. This is primarily used when a
544598 /// branch is unanalyzable. It is useful for things like unconditional
642642 return true;
643643 }
644644
645 MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineInstr *MI,
646 SmallVectorImpl &Ops,
647 int FI) const {
648 if (Ops.size() != 1) return NULL;
649
650 unsigned OpNum = Ops[0];
651 unsigned Opc = MI->getOpcode();
652 MachineInstr *NewMI = NULL;
653 switch (Opc) {
654 default: break;
655 case ARM::MOVr: {
656 if (MI->getOperand(4).getReg() == ARM::CPSR)
657 // If it is updating CPSR, then it cannot be foled.
658 break;
659 unsigned Pred = MI->getOperand(2).getImm();
660 unsigned PredReg = MI->getOperand(3).getReg();
661 if (OpNum == 0) { // move -> store
662 unsigned SrcReg = MI->getOperand(1).getReg();
663 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
664 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
665 } else { // move -> load
666 unsigned DstReg = MI->getOperand(0).getReg();
667 NewMI = BuildMI(get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
668 .addImm(0).addImm(Pred).addReg(PredReg);
669 }
670 break;
671 }
672 case ARM::tMOVr: {
673 if (OpNum == 0) { // move -> store
674 unsigned SrcReg = MI->getOperand(1).getReg();
675 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
676 // tSpill cannot take a high register operand.
677 break;
678 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
679 .addImm(0);
680 } else { // move -> load
681 unsigned DstReg = MI->getOperand(0).getReg();
682 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
683 // tRestore cannot target a high register operand.
684 break;
685 NewMI = BuildMI(get(ARM::tRestore), DstReg).addFrameIndex(FI)
686 .addImm(0);
687 }
688 break;
689 }
690 case ARM::FCPYS: {
691 unsigned Pred = MI->getOperand(2).getImm();
692 unsigned PredReg = MI->getOperand(3).getReg();
693 if (OpNum == 0) { // move -> store
694 unsigned SrcReg = MI->getOperand(1).getReg();
695 NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
696 .addImm(0).addImm(Pred).addReg(PredReg);
697 } else { // move -> load
698 unsigned DstReg = MI->getOperand(0).getReg();
699 NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI)
700 .addImm(0).addImm(Pred).addReg(PredReg);
701 }
702 break;
703 }
704 case ARM::FCPYD: {
705 unsigned Pred = MI->getOperand(2).getImm();
706 unsigned PredReg = MI->getOperand(3).getReg();
707 if (OpNum == 0) { // move -> store
708 unsigned SrcReg = MI->getOperand(1).getReg();
709 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
710 .addImm(0).addImm(Pred).addReg(PredReg);
711 } else { // move -> load
712 unsigned DstReg = MI->getOperand(0).getReg();
713 NewMI = BuildMI(get(ARM::FLDD), DstReg).addFrameIndex(FI)
714 .addImm(0).addImm(Pred).addReg(PredReg);
715 }
716 break;
717 }
718 }
719
720 if (NewMI)
721 NewMI->copyKillDeadInfo(MI);
722 return NewMI;
723 }
724
725 bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
726 SmallVectorImpl &Ops) const {
727 if (Ops.size() != 1) return false;
728
729 unsigned OpNum = Ops[0];
730 unsigned Opc = MI->getOpcode();
731 switch (Opc) {
732 default: break;
733 case ARM::MOVr:
734 // If it is updating CPSR, then it cannot be foled.
735 return MI->getOperand(4).getReg() != ARM::CPSR;
736 case ARM::tMOVr: {
737 if (OpNum == 0) { // move -> store
738 unsigned SrcReg = MI->getOperand(1).getReg();
739 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
740 // tSpill cannot take a high register operand.
741 return false;
742 } else { // move -> load
743 unsigned DstReg = MI->getOperand(0).getReg();
744 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
745 // tRestore cannot target a high register operand.
746 return false;
747 }
748 return true;
749 }
750 case ARM::FCPYS:
751 case ARM::FCPYD:
752 return true;
753 }
754
755 return false;
756 }
757
645758 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
646759 if (MBB.empty()) return false;
647760
189189 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
190190 MachineBasicBlock::iterator MI,
191191 const std::vector &CSI) const;
192
193 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
194 SmallVectorImpl &Ops,
195 int FrameIndex) const;
196
197 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
198 SmallVectorImpl &Ops,
199 MachineInstr* LoadMI) const {
200 return 0;
201 }
202
203 virtual bool canFoldMemoryOperand(MachineInstr *MI,
204 SmallVectorImpl &Ops) const;
205
192206 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
193207 virtual bool ReverseBranchCondition(std::vector &Cond) const;
194208
135135
136136 /// isLowRegister - Returns true if the register is low register r0-r7.
137137 ///
138 static bool isLowRegister(unsigned Reg) {
138 bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
139139 using namespace ARM;
140140 switch (Reg) {
141141 case R0: case R1: case R2: case R3:
144144 default:
145145 return false;
146146 }
147 }
148
149 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
150 SmallVectorImpl &Ops,
151 int FI) const {
152 if (Ops.size() != 1) return NULL;
153
154 unsigned OpNum = Ops[0];
155 unsigned Opc = MI->getOpcode();
156 MachineInstr *NewMI = NULL;
157 switch (Opc) {
158 default: break;
159 case ARM::MOVr: {
160 if (MI->getOperand(4).getReg() == ARM::CPSR)
161 // If it is updating CPSR, then it cannot be foled.
162 break;
163 unsigned Pred = MI->getOperand(2).getImm();
164 unsigned PredReg = MI->getOperand(3).getReg();
165 if (OpNum == 0) { // move -> store
166 unsigned SrcReg = MI->getOperand(1).getReg();
167 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
168 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
169 } else { // move -> load
170 unsigned DstReg = MI->getOperand(0).getReg();
171 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
172 .addImm(0).addImm(Pred).addReg(PredReg);
173 }
174 break;
175 }
176 case ARM::tMOVr: {
177 if (OpNum == 0) { // move -> store
178 unsigned SrcReg = MI->getOperand(1).getReg();
179 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
180 // tSpill cannot take a high register operand.
181 break;
182 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
183 .addImm(0);
184 } else { // move -> load
185 unsigned DstReg = MI->getOperand(0).getReg();
186 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
187 // tRestore cannot target a high register operand.
188 break;
189 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
190 .addImm(0);
191 }
192 break;
193 }
194 case ARM::FCPYS: {
195 unsigned Pred = MI->getOperand(2).getImm();
196 unsigned PredReg = MI->getOperand(3).getReg();
197 if (OpNum == 0) { // move -> store
198 unsigned SrcReg = MI->getOperand(1).getReg();
199 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
200 .addImm(0).addImm(Pred).addReg(PredReg);
201 } else { // move -> load
202 unsigned DstReg = MI->getOperand(0).getReg();
203 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
204 .addImm(0).addImm(Pred).addReg(PredReg);
205 }
206 break;
207 }
208 case ARM::FCPYD: {
209 unsigned Pred = MI->getOperand(2).getImm();
210 unsigned PredReg = MI->getOperand(3).getReg();
211 if (OpNum == 0) { // move -> store
212 unsigned SrcReg = MI->getOperand(1).getReg();
213 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
214 .addImm(0).addImm(Pred).addReg(PredReg);
215 } else { // move -> load
216 unsigned DstReg = MI->getOperand(0).getReg();
217 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
218 .addImm(0).addImm(Pred).addReg(PredReg);
219 }
220 break;
221 }
222 }
223
224 if (NewMI)
225 NewMI->copyKillDeadInfo(MI);
226 return NewMI;
227 }
228
229 bool ARMRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
230 SmallVectorImpl &Ops) const {
231 if (Ops.size() != 1) return false;
232
233 unsigned OpNum = Ops[0];
234 unsigned Opc = MI->getOpcode();
235 switch (Opc) {
236 default: break;
237 case ARM::MOVr:
238 // If it is updating CPSR, then it cannot be foled.
239 return MI->getOperand(4).getReg() != ARM::CPSR;
240 case ARM::tMOVr: {
241 if (OpNum == 0) { // move -> store
242 unsigned SrcReg = MI->getOperand(1).getReg();
243 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
244 // tSpill cannot take a high register operand.
245 return false;
246 } else { // move -> load
247 unsigned DstReg = MI->getOperand(0).getReg();
248 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
249 // tRestore cannot target a high register operand.
250 return false;
251 }
252 return true;
253 }
254 case ARM::FCPYS:
255 case ARM::FCPYD:
256 return true;
257 }
258
259 return false;
260147 }
261148
262149 const unsigned*
425312 /// constpool entry.
426313 static
427314 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator &MBBI,
429 unsigned DestReg, unsigned BaseReg,
430 int NumBytes, bool CanChangeCC,
431 const TargetInstrInfo &TII) {
432 bool isHigh = !isLowRegister(DestReg) ||
433 (BaseReg != 0 && !isLowRegister(BaseReg));
315 MachineBasicBlock::iterator &MBBI,
316 unsigned DestReg, unsigned BaseReg,
317 int NumBytes, bool CanChangeCC,
318 const TargetInstrInfo &TII,
319 const ARMRegisterInfo& MRI) {
320 bool isHigh = !MRI.isLowRegister(DestReg) ||
321 (BaseReg != 0 && !MRI.isLowRegister(BaseReg));
434322 bool isSub = false;
435323 // Subtract doesn't have high register version. Load the negative value
436324 // if either base or dest register is a high register. Also, if do not
475363 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
476364 MachineBasicBlock::iterator &MBBI,
477365 unsigned DestReg, unsigned BaseReg,
478 int NumBytes, const TargetInstrInfo &TII) {
366 int NumBytes, const TargetInstrInfo &TII,
367 const ARMRegisterInfo& MRI) {
479368 bool isSub = NumBytes < 0;
480369 unsigned Bytes = (unsigned)NumBytes;
481370 if (isSub) Bytes = -NumBytes;
521410 if (NumMIs > Threshold) {
522411 // This will expand into too many instructions. Load the immediate from a
523412 // constpool entry.
524 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
413 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI);
525414 return;
526415 }
527416
528417 if (DstNotEqBase) {
529 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
418 if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
530419 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
531420 unsigned Chunk = (1 << 3) - 1;
532421 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
576465 static
577466 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
578467 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
579 bool isThumb, const TargetInstrInfo &TII) {
468 bool isThumb, const TargetInstrInfo &TII,
469 const ARMRegisterInfo& MRI) {
580470 if (isThumb)
581 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
471 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI);
582472 else
583473 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
584474 Pred, PredReg, TII);
609499 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
610500 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
611501 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
612 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
502 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this);
613503 } else {
614504 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
615505 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
616506 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
617 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
507 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this);
618508 }
619509 }
620510 }
626516 static void emitThumbConstant(MachineBasicBlock &MBB,
627517 MachineBasicBlock::iterator &MBBI,
628518 unsigned DestReg, int Imm,
629 const TargetInstrInfo &TII) {
519 const TargetInstrInfo &TII,
520 const ARMRegisterInfo& MRI) {
630521 bool isSub = Imm < 0;
631522 if (isSub) Imm = -Imm;
632523
635526 Imm -= ThisVal;
636527 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
637528 if (Imm > 0)
638 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
529 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI);
639530 if (isSub)
640531 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
641532 .addReg(DestReg, false, false, true);
769660 // MI would expand into a large number of instructions. Don't try to
770661 // simplify the immediate.
771662 if (NumMIs > 2) {
772 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
663 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this);
773664 MBB.erase(II);
774665 return;
775666 }
782673 MI.getOperand(i+1).ChangeToImmediate(Mask);
783674 Offset = (Offset - Mask * Scale);
784675 MachineBasicBlock::iterator NII = next(II);
785 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
676 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this);
786677 } else {
787678 // Translate r0 = add sp, -imm to
788679 // r0 = -imm (this is then translated into a series of instructons)
789680 // r0 = add r0, sp
790 emitThumbConstant(MBB, II, DestReg, Offset, TII);
681 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this);
791682 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
792683 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
793684 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
890781 bool UseRR = false;
891782 if (Opcode == ARM::tRestore) {
892783 if (FrameReg == ARM::SP)
893 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
784 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
785 Offset, false, TII, *this);
894786 else {
895787 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
896788 UseRR = true;
897789 }
898790 } else
899 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
791 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
900792 MI.setInstrDescriptor(TII.get(ARM::tLDR));
901793 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
902794 if (UseRR)
926818 .addReg(ARM::R3, false, false, true);
927819 if (Opcode == ARM::tSpill) {
928820 if (FrameReg == ARM::SP)
929 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
821 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
822 Offset, false, TII, *this);
930823 else {
931824 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
932825 UseRR = true;
933826 }
934827 } else
935 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
828 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
936829 MI.setInstrDescriptor(TII.get(ARM::tSTR));
937830 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
938831 if (UseRR) // Use [reg, reg] addrmode.
12651158 int FramePtrSpillFI = 0;
12661159
12671160 if (VARegSaveSize)
1268 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1161 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
12691162
12701163 if (!AFI->hasStackFrame()) {
12711164 if (NumBytes != 0)
1272 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1165 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
12731166 return;
12741167 }
12751168
13091202
13101203 if (!isThumb) {
13111204 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1312 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII);
1205 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this);
13131206 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
13141207 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
13151208 ++MBBI;
13251218
13261219 if (!isThumb) {
13271220 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1328 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII);
1221 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this);
13291222
13301223 // Build the new SUBri to adjust SP for FP callee-save spill area.
13311224 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1332 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII);
1225 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this);
13331226 }
13341227
13351228 // Determine starting offsets of spill areas.
13461239 // Insert it after all the callee-save spills.
13471240 if (!isThumb)
13481241 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1349 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1242 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
13501243 }
13511244
13521245 if(STI.isTargetELF() && hasFP(MF)) {
13891282 int NumBytes = (int)MFI->getStackSize();
13901283 if (!AFI->hasStackFrame()) {
13911284 if (NumBytes != 0)
1392 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1285 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
13931286 } else {
13941287 // Unwind MBBI to point to first LDR / FLDD.
13951288 const unsigned *CSRegs = getCalleeSavedRegs();
14111304 // Reset SP based on frame pointer only if the stack frame extends beyond
14121305 // frame pointer stack slot or target is ELF and the function has FP.
14131306 if (NumBytes)
1414 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1307 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
1308 TII, *this);
14151309 else
14161310 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
14171311 } else {
14191313 &MBB.front() != MBBI &&
14201314 prior(MBBI)->getOpcode() == ARM::tPOP) {
14211315 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1422 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1316 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
14231317 } else
1424 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1318 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
14251319 }
14261320 } else {
14271321 // Darwin ABI requires FP to point to the stack slot that contains the
14421336 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
14431337 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
14441338 } else if (NumBytes) {
1445 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
1339 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
14461340 }
14471341
14481342 // Move SP to start of integer callee save spill area 2.
14491343 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
14501344 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1451 false, TII);
1345 false, TII, *this);
14521346
14531347 // Move SP to start of integer callee save spill area 1.
14541348 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
14551349 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1456 false, TII);
1350 false, TII, *this);
14571351
14581352 // Move SP to SP upon entry to the function.
14591353 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
14601354 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1461 false, TII);
1355 false, TII, *this);
14621356 }
14631357 }
14641358
14681362 // FIXME: Verify this is still ok when R3 is no longer being reserved.
14691363 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
14701364
1471 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1365 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
14721366
14731367 if (isThumb) {
14741368 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
3939 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4040 unsigned DestReg, const MachineInstr *Orig) const;
4141
42 MachineInstr* foldMemoryOperand(MachineInstr* MI,
43 SmallVectorImpl &Ops,
44 int FrameIndex) const;
45
46 MachineInstr* foldMemoryOperand(MachineInstr* MI,
47 SmallVectorImpl &Ops,
48 MachineInstr* LoadMI) const {
49 return 0;
50 }
51
52 bool canFoldMemoryOperand(MachineInstr *MI,
53 SmallVectorImpl &Ops) const;
54
5542 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5643
5744 const TargetRegisterClass* const*
8976 unsigned getEHHandlerRegister() const;
9077
9178 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
79
80 bool isLowRegister(unsigned Reg) const;
9281 };
9382
9483 } // end namespace llvm
249249 NewMIs.push_back(MIB);
250250 }
251251
252 MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineInstr *MI,
253 SmallVectorImpl &Ops,
254 int FrameIndex) const {
255 if (Ops.size() != 1) return NULL;
256
257 // Make sure this is a reg-reg copy.
258 unsigned Opc = MI->getOpcode();
259
260 MachineInstr *NewMI = NULL;
261 switch(Opc) {
262 default:
263 break;
264 case Alpha::BISr:
265 case Alpha::CPYSS:
266 case Alpha::CPYST:
267 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
268 if (Ops[0] == 0) { // move -> store
269 unsigned InReg = MI->getOperand(1).getReg();
270 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
271 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
272 NewMI = BuildMI(get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
273 .addReg(Alpha::F31);
274 } else { // load -> move
275 unsigned OutReg = MI->getOperand(0).getReg();
276 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
277 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
278 NewMI = BuildMI(get(Opc), OutReg).addFrameIndex(FrameIndex)
279 .addReg(Alpha::F31);
280 }
281 }
282 break;
283 }
284 if (NewMI)
285 NewMI->copyKillDeadInfo(MI);
286 return 0;
287 }
288
252289 static unsigned AlphaRevCondCode(unsigned Opcode) {
253290 switch (Opcode) {
254291 case Alpha::BEQ: return Alpha::BNE;
6565 SmallVectorImpl &Addr,
6666 const TargetRegisterClass *RC,
6767 SmallVectorImpl &NewMIs) const;
68
69 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
70 SmallVectorImpl &Ops,
71 int FrameIndex) const;
72
73 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
74 SmallVectorImpl &Ops,
75 MachineInstr* LoadMI) const {
76 return 0;
77 }
78
6879 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
6980 MachineBasicBlock *&FBB,
7081 std::vector &Cond) const;
5757 {
5858 }
5959
60 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
61 SmallVectorImpl &Ops,
62 int FrameIndex) const {
63 if (Ops.size() != 1) return NULL;
64
65 // Make sure this is a reg-reg copy.
66 unsigned Opc = MI->getOpcode();
67
68 MachineInstr *NewMI = NULL;
69 switch(Opc) {
70 default:
71 break;
72 case Alpha::BISr:
73 case Alpha::CPYSS:
74 case Alpha::CPYST:
75 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
76 if (Ops[0] == 0) { // move -> store
77 unsigned InReg = MI->getOperand(1).getReg();
78 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
79 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
80 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
81 .addReg(Alpha::F31);
82 } else { // load -> move
83 unsigned OutReg = MI->getOperand(0).getReg();
84 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
85 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
86 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
87 .addReg(Alpha::F31);
88 }
89 }
90 break;
91 }
92 if (NewMI)
93 NewMI->copyKillDeadInfo(MI);
94 return 0;
95 }
96
9760 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
9861 MachineBasicBlock::iterator I,
9962 unsigned DestReg,
2727 AlphaRegisterInfo(const TargetInstrInfo &tii);
2828
2929 /// Code Generation virtual methods...
30 MachineInstr* foldMemoryOperand(MachineInstr* MI,
31 SmallVectorImpl &Ops,
32 int FrameIndex) const;
33
34 MachineInstr* foldMemoryOperand(MachineInstr* MI,
35 SmallVectorImpl &Ops,
36 MachineInstr* LoadMI) const {
37 return 0;
38 }
39
4030 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4131 unsigned DestReg, const MachineInstr *Orig) const;
4232
387387 }
388388 }
389389
390 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
391 /// copy instructions, turning them into load/store instructions.
392 MachineInstr *
393 SPUInstrInfo::foldMemoryOperand(MachineInstr *MI,
394 SmallVectorImpl &Ops,
395 int FrameIndex) const
396 {
397 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
398 if (Ops.size() != 1) return NULL;
399
400 unsigned OpNum = Ops[0];
401 unsigned Opc = MI->getOpcode();
402 MachineInstr *NewMI = 0;
403
404 if ((Opc == SPU::ORr32
405 || Opc == SPU::ORv4i32)
406 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
407 if (OpNum == 0) { // move -> store
408 unsigned InReg = MI->getOperand(1).getReg();
409 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
410 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
411 FrameIndex);
412 }
413 } else { // move -> load
414 unsigned OutReg = MI->getOperand(0).getReg();
415 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
416 NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
417 }
418 }
419
420 if (NewMI)
421 NewMI->copyKillDeadInfo(MI);
422
423 return NewMI;
424 #else
425 return 0;
426 #endif
427 }
428
7373 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
7474 SmallVectorImpl &Addr,
7575 const TargetRegisterClass *RC,
76 SmallVectorImpl &NewMIs) const;
76 SmallVectorImpl &NewMIs) const;
77
78 //! Fold spills into load/store instructions
79 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
80 SmallVectorImpl &Ops,
81 int FrameIndex) const;
82
83 //! Fold any load/store to an operand
84 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
85 SmallVectorImpl &Ops,
86 MachineInstr* LoadMI) const {
87 return 0;
88 }
7789 };
7890 }
7991
294294 return Reserved;
295295 }
296296
297 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
298 /// copy instructions, turning them into load/store instructions.
299 MachineInstr *
300 SPURegisterInfo::foldMemoryOperand(MachineInstr *MI,
301 SmallVectorImpl &Ops,
302 int FrameIndex) const
303 {
304 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
305 if (Ops.size() != 1) return NULL;
306
307 unsigned OpNum = Ops[0];
308 unsigned Opc = MI->getOpcode();
309 MachineInstr *NewMI = 0;
310
311 if ((Opc == SPU::ORr32
312 || Opc == SPU::ORv4i32)
313 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
314 if (OpNum == 0) { // move -> store
315 unsigned InReg = MI->getOperand(1).getReg();
316 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
317 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
318 FrameIndex);
319 }
320 } else { // move -> load
321 unsigned OutReg = MI->getOperand(0).getReg();
322 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
323 NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
324 }
325 }
326
327 if (NewMI)
328 NewMI->copyKillDeadInfo(MI);
329
330 return NewMI;
331 #else
332 return 0;
333 #endif
334 }
335
336 /// General-purpose load/store fold to operand code
337 MachineInstr *
338 SPURegisterInfo::foldMemoryOperand(MachineInstr *MI,
339 SmallVectorImpl &Ops,
340 MachineInstr *LoadMI) const
341 {
342 return 0;
343 }
344
345297 //===----------------------------------------------------------------------===//
346298 // Stack Frame Processing methods
347299 //===----------------------------------------------------------------------===//
4141
4242 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4343 unsigned DestReg, const MachineInstr *Orig) const;
44
45 //! Fold spills into load/store instructions
46 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
47 SmallVectorImpl &Ops,
48 int FrameIndex) const;
49
50 //! Fold any load/store to an operand
51 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
52 SmallVectorImpl &Ops,
53 MachineInstr* LoadMI) const;
5444
5545 //! Return the array of callee-saved registers
5646 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
370370 return;
371371 }
372372
373 MachineInstr *MipsInstrInfo::
374 foldMemoryOperand(MachineInstr* MI,
375 SmallVectorImpl &Ops, int FI) const
376 {
377 if (Ops.size() != 1) return NULL;
378
379 MachineInstr *NewMI = NULL;
380
381 switch (MI->getOpcode())
382 {
383 case Mips::ADDu:
384 if ((MI->getOperand(0).isRegister()) &&
385 (MI->getOperand(1).isRegister()) &&
386 (MI->getOperand(1).getReg() == Mips::ZERO) &&
387 (MI->getOperand(2).isRegister()))
388 {
389 if (Ops[0] == 0) // COPY -> STORE
390 NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
391 .addImm(0).addReg(MI->getOperand(2).getReg());
392 else // COPY -> LOAD
393 NewMI = BuildMI(get(Mips::LW), MI->getOperand(0)
394 .getReg()).addImm(0).addFrameIndex(FI);
395 }
396 break;
397 }
398
399 if (NewMI)
400 NewMI->copyKillDeadInfo(MI);
401 return NewMI;
402 }
403
373404 unsigned MipsInstrInfo::
374405 RemoveBranch(MachineBasicBlock &MBB) const
375406 {
104104 SmallVectorImpl &Addr,
105105 const TargetRegisterClass *RC,
106106 SmallVectorImpl &NewMIs) const;
107
108 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
109 SmallVectorImpl &Ops,
110 int FrameIndex) const;
111
112 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
113 SmallVectorImpl &Ops,
114 MachineInstr* LoadMI) const {
115 return 0;
116 }
117
107118 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
108119 virtual bool ReverseBranchCondition(std::vector &Cond) const;
109120
9292 MBB.insert(I, MI);
9393 }
9494
95 MachineInstr *MipsRegisterInfo::
96 foldMemoryOperand(MachineInstr* MI,
97 SmallVectorImpl &Ops, int FI) const
98 {
99 if (Ops.size() != 1) return NULL;
100
101 MachineInstr *NewMI = NULL;
102
103 switch (MI->getOpcode())
104 {
105 case Mips::ADDu:
106 if ((MI->getOperand(0).isRegister()) &&
107 (MI->getOperand(1).isRegister()) &&
108 (MI->getOperand(1).getReg() == Mips::ZERO) &&
109 (MI->getOperand(2).isRegister()))
110 {
111 if (Ops[0] == 0) // COPY -> STORE
112 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
113 .addImm(0).addReg(MI->getOperand(2).getReg());
114 else // COPY -> LOAD
115 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
116 .getReg()).addImm(0).addFrameIndex(FI);
117 }
118 break;
119 }
120
121 if (NewMI)
122 NewMI->copyKillDeadInfo(MI);
123 return NewMI;
124 }
125
12695 //===----------------------------------------------------------------------===//
12796 //
12897 // Callee Saved Registers methods
3434 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
3535 unsigned DestReg, const MachineInstr *Orig) const;
3636
37 MachineInstr* foldMemoryOperand(MachineInstr* MI,
38 SmallVectorImpl &Ops,
39 int FrameIndex) const;
40
41 MachineInstr* foldMemoryOperand(MachineInstr* MI,
42 SmallVectorImpl &Ops,
43 MachineInstr* LoadMI) const {
44 return 0;
45 }
46
4737 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
4838
4939 const TargetRegisterClass* const*
533533 return;
534534 }
535535
536 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
537 /// copy instructions, turning them into load/store instructions.
538 MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineInstr *MI,
539 SmallVectorImpl &Ops,
540 int FrameIndex) const {
541 if (Ops.size() != 1) return NULL;
542
543 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
544 // it takes more than one instruction to store it.
545 unsigned Opc = MI->getOpcode();
546 unsigned OpNum = Ops[0];
547
548 MachineInstr *NewMI = NULL;
549 if ((Opc == PPC::OR &&
550 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
551 if (OpNum == 0) { // move -> store
552 unsigned InReg = MI->getOperand(1).getReg();
553 NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
554 FrameIndex);
555 } else { // move -> load
556 unsigned OutReg = MI->getOperand(0).getReg();
557 NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
558 FrameIndex);
559 }
560 } else if ((Opc == PPC::OR8 &&
561 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
562 if (OpNum == 0) { // move -> store
563 unsigned InReg = MI->getOperand(1).getReg();
564 NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
565 FrameIndex);
566 } else { // move -> load
567 unsigned OutReg = MI->getOperand(0).getReg();
568 NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
569 }
570 } else if (Opc == PPC::FMRD) {
571 if (OpNum == 0) { // move -> store
572 unsigned InReg = MI->getOperand(1).getReg();
573 NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
574 FrameIndex);
575 } else { // move -> load
576 unsigned OutReg = MI->getOperand(0).getReg();
577 NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
578 }
579 } else if (Opc == PPC::FMRS) {
580 if (OpNum == 0) { // move -> store
581 unsigned InReg = MI->getOperand(1).getReg();
582 NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
583 FrameIndex);
584 } else { // move -> load
585 unsigned OutReg = MI->getOperand(0).getReg();
586 NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
587 }
588 }
589
590 if (NewMI)
591 NewMI->copyKillDeadInfo(MI);
592 return NewMI;
593 }
594
595 bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
596 SmallVectorImpl &Ops) const {
597 if (Ops.size() != 1) return false;
598
599 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
600 // it takes more than one instruction to store it.
601 unsigned Opc = MI->getOpcode();
602
603 if ((Opc == PPC::OR &&
604 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
605 return true;
606 else if ((Opc == PPC::OR8 &&
607 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
608 return true;
609 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
610 return true;
611
612 return false;
613 }
614
536615
537616 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
538617 if (MBB.empty()) return false;
128128 const TargetRegisterClass *RC,
129129 SmallVectorImpl &NewMIs) const;
130130
131 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
132 /// copy instructions, turning them into load/store instructions.
133 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
134 SmallVectorImpl &Ops,
135 int FrameIndex) const;
136
137 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
138 SmallVectorImpl &Ops,
139 MachineInstr* LoadMI) const {
140 return 0;
141 }
142
143 virtual bool canFoldMemoryOperand(MachineInstr *MI,
144 SmallVectorImpl &Ops) const;
145
131146 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
132147 virtual bool ReverseBranchCondition(std::vector &Cond) const;
133148 };
295295 if (needsFP(MF))
296296 Reserved.set(PPC::R31);
297297 return Reserved;
298 }
299
300 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
301 /// copy instructions, turning them into load/store instructions.
302 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
303 SmallVectorImpl &Ops,
304 int FrameIndex) const {
305 if (Ops.size() != 1) return NULL;
306
307 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
308 // it takes more than one instruction to store it.
309 unsigned Opc = MI->getOpcode();
310 unsigned OpNum = Ops[0];
311
312 MachineInstr *NewMI = NULL;
313 if ((Opc == PPC::OR &&
314 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
315 if (OpNum == 0) { // move -> store
316 unsigned InReg = MI->getOperand(1).getReg();
317 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
318 FrameIndex);
319 } else { // move -> load
320 unsigned OutReg = MI->getOperand(0).getReg();
321 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
322 FrameIndex);
323 }
324 } else if ((Opc == PPC::OR8 &&
325 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
326 if (OpNum == 0) { // move -> store
327 unsigned InReg = MI->getOperand(1).getReg();
328 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
329 FrameIndex);
330 } else { // move -> load
331 unsigned OutReg = MI->getOperand(0).getReg();
332 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
333 }
334 } else if (Opc == PPC::FMRD) {
335 if (OpNum == 0) { // move -> store
336 unsigned InReg = MI->getOperand(1).getReg();
337 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
338 FrameIndex);
339 } else { // move -> load
340 unsigned OutReg = MI->getOperand(0).getReg();
341 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
342 }
343 } else if (Opc == PPC::FMRS) {
344 if (OpNum == 0) { // move -> store
345 unsigned InReg = MI->getOperand(1).getReg();
346 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
347 FrameIndex);
348 } else { // move -> load
349 unsigned OutReg = MI->getOperand(0).getReg();
350 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
351 }
352 }
353
354 if (NewMI)
355 NewMI->copyKillDeadInfo(MI);
356 return NewMI;
357 }
358
359 bool PPCRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
360 SmallVectorImpl &Ops) const {
361 if (Ops.size() != 1) return false;
362
363 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
364 // it takes more than one instruction to store it.
365 unsigned Opc = MI->getOpcode();
366
367 if ((Opc == PPC::OR &&
368 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
369 return true;
370 else if ((Opc == PPC::OR8 &&
371 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
372 return true;
373 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
374 return true;
375
376 return false;
377298 }
378299
379300 //===----------------------------------------------------------------------===//
3636 /// Code Generation virtual methods...
3737 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
3838 unsigned DestReg, const MachineInstr *Orig) const;
39
40 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
41 /// copy instructions, turning them into load/store instructions.
42 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
43 SmallVectorImpl &Ops,
44 int FrameIndex) const;
45
46 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
47 SmallVectorImpl &Ops,
48 MachineInstr* LoadMI) const {
49 return 0;
50 }
51
52 virtual bool canFoldMemoryOperand(MachineInstr *MI,
53 SmallVectorImpl &Ops) const;
5439
5540 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
5641
220220 NewMIs.push_back(MIB);
221221 return;
222222 }
223
224 MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineInstr* MI,
225 SmallVectorImpl &Ops,
226 int FI) const {
227 if (Ops.size() != 1) return NULL;
228
229 unsigned OpNum = Ops[0];
230 bool isFloat = false;
231 MachineInstr *NewMI = NULL;
232 switch (MI->getOpcode()) {
233 case SP::ORrr:
234 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
235 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
236 if (OpNum == 0) // COPY -> STORE
237 NewMI = BuildMI(get(SP::STri)).addFrameIndex(FI).addImm(0)
238 .addReg(MI->getOperand(2).getReg());
239 else // COPY -> LOAD
240 NewMI = BuildMI(get(SP::LDri), MI->getOperand(0).getReg())
241 .addFrameIndex(FI).addImm(0);
242 }
243 break;
244 case SP::FMOVS:
245 isFloat = true;
246 // FALLTHROUGH
247 case SP::FMOVD:
248 if (OpNum == 0) // COPY -> STORE
249 NewMI = BuildMI(get(isFloat ? SP::STFri : SP::STDFri))
250 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
251 else // COPY -> LOAD
252 NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri),
253 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
254 break;
255 }
256
257 if (NewMI)
258 NewMI->copyKillDeadInfo(MI);
259 return NewMI;
260 }
9292 SmallVectorImpl &Addr,
9393 const TargetRegisterClass *RC,
9494 SmallVectorImpl &NewMIs) const;
95
96 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
97 SmallVectorImpl &Ops,
98 int FrameIndex) const;
99
100 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
101 SmallVectorImpl &Ops,
102 MachineInstr* LoadMI) const {
103 return 0;
104 }
95105 };
96106
97107 }
3636 MachineInstr *MI = Orig->clone();
3737 MI->getOperand(0).setReg(DestReg);
3838 MBB.insert(I, MI);
39 }
40
41 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
42 SmallVectorImpl &Ops,
43 int FI) const {
44 if (Ops.size() != 1) return NULL;
45
46 unsigned OpNum = Ops[0];
47 bool isFloat = false;
48 MachineInstr *NewMI = NULL;
49 switch (MI->getOpcode()) {
50 case SP::ORrr:
51 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
52 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
53 if (OpNum == 0) // COPY -> STORE
54 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
55 .addReg(MI->getOperand(2).getReg());
56 else // COPY -> LOAD
57 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
58 .addFrameIndex(FI).addImm(0);
59 }
60 break;
61 case SP::FMOVS:
62 isFloat = true;
63 // FALLTHROUGH
64 case SP::FMOVD:
65 if (OpNum == 0) // COPY -> STORE
66 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
67 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
68 else // COPY -> LOAD
69 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
70 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
71 break;
72 }
73
74 if (NewMI)
75 NewMI->copyKillDeadInfo(MI);
76 return NewMI;
7739 }
7840
7941 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
3131 /// Code Generation virtual methods...
3232 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
3333 unsigned DestReg, const MachineInstr *Orig) const;
34
35 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
36 SmallVectorImpl &Ops,
37 int FrameIndex) const;
38
39 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
40 SmallVectorImpl &Ops,
41 MachineInstr* LoadMI) const {
42 return 0;
43 }
4434
4535 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
4636
2222 #include "llvm/CodeGen/MachineInstrBuilder.h"
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
2424 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/Support/CommandLine.h"
2526 #include "llvm/Target/TargetOptions.h"
27
2628 using namespace llvm;
29
30 namespace {
31 cl::opt
32 NoFusing("disable-spill-fusing",
33 cl::desc("Disable fusing of spill code into instructions"));
34 cl::opt
35 PrintFailedFusing("print-failed-fuse-candidates",
36 cl::desc("Print instructions that the allocator wants to"
37 " fuse, but the X86 backend currently can't"),
38 cl::Hidden);
39 }
2740
2841 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
2942 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
3043 TM(tm), RI(tm, *this) {
44 SmallVector AmbEntries;
45 static const unsigned OpTbl2Addr[][2] = {
46 { X86::ADC32ri, X86::ADC32mi },
47 { X86::ADC32ri8, X86::ADC32mi8 },
48 { X86::ADC32rr, X86::ADC32mr },
49 { X86::ADC64ri32, X86::ADC64mi32 },
50 { X86::ADC64ri8, X86::ADC64mi8 },
51 { X86::ADC64rr, X86::ADC64mr },
52 { X86::ADD16ri, X86::ADD16mi },
53 { X86::ADD16ri8, X86::ADD16mi8 },
54 { X86::ADD16rr, X86::ADD16mr },
55 { X86::ADD32ri, X86::ADD32mi },
56 { X86::ADD32ri8, X86::ADD32mi8 },
57 { X86::ADD32rr, X86::ADD32mr },
58 { X86::ADD64ri32, X86::ADD64mi32 },
59 { X86::ADD64ri8, X86::ADD64mi8 },
60 { X86::ADD64rr, X86::ADD64mr },
61 { X86::ADD8ri, X86::ADD8mi },
62 { X86::ADD8rr, X86::ADD8mr },
63 { X86::AND16ri, X86::AND16mi },
64 { X86::AND16ri8, X86::AND16mi8 },
65 { X86::AND16rr, X86::AND16mr },
66 { X86::AND32ri, X86::AND32mi },
67 { X86::AND32ri8, X86::AND32mi8 },
68 { X86::AND32rr, X86::AND32mr },
69 { X86::AND64ri32, X86::AND64mi32 },
70 { X86::AND64ri8, X86::AND64mi8 },
71 { X86::AND64rr, X86::AND64mr },
72 { X86::AND8ri, X86::AND8mi },
73 { X86::AND8rr, X86::AND8mr },
74 { X86::DEC16r, X86::DEC16m },
75 { X86::DEC32r, X86::DEC32m },
76 { X86::DEC64_16r, X86::DEC64_16m },
77 { X86::DEC64_32r, X86::DEC64_32m },
78 { X86::DEC64r, X86::DEC64m },
79 { X86::DEC8r, X86::DEC8m },
80 { X86::INC16r, X86::INC16m },
81 { X86::INC32r, X86::INC32m },
82 { X86::INC64_16r, X86::INC64_16m },
83 { X86::INC64_32r, X86::INC64_32m },
84 { X86::INC64r, X86::INC64m },
85 { X86::INC8r, X86::INC8m },
86 { X86::NEG16r, X86::NEG16m },
87 { X86::NEG32r, X86::NEG32m },
88 { X86::NEG64r, X86::NEG64m },
89 { X86::NEG8r, X86::NEG8m },
90 { X86::NOT16r, X86::NOT16m },
91 { X86::NOT32r, X86::NOT32m },
92 { X86::NOT64r, X86::NOT64m },
93 { X86::NOT8r, X86::NOT8m },
94 { X86::OR16ri, X86::OR16mi },
95 { X86::OR16ri8, X86::OR16mi8 },
96 { X86::OR16rr, X86::OR16mr },
97 { X86::OR32ri, X86::OR32mi },
98 { X86::OR32ri8, X86::OR32mi8 },
99 { X86::OR32rr, X86::OR32mr },
100 { X86::OR64ri32, X86::OR64mi32 },
101 { X86::OR64ri8, X86::OR64mi8 },
102 { X86::OR64rr, X86::OR64mr },
103 { X86::OR8ri, X86::OR8mi },
104 { X86::OR8rr, X86::OR8mr },
105 { X86::ROL16r1, X86::ROL16m1 },
106 { X86::ROL16rCL, X86::ROL16mCL },
107 { X86::ROL16ri, X86::ROL16mi },
108 { X86::ROL32r1, X86::ROL32m1 },
109 { X86::ROL32rCL, X86::ROL32mCL },
110 { X86::ROL32ri, X86::ROL32mi },
111 { X86::ROL64r1, X86::ROL64m1 },
112 { X86::ROL64rCL, X86::ROL64mCL },
113 { X86::ROL64ri, X86::ROL64mi },
114 { X86::ROL8r1, X86::ROL8m1 },
115 { X86::ROL8rCL, X86::ROL8mCL },
116 { X86::ROL8ri, X86::ROL8mi },
117 { X86::ROR16r1, X86::ROR16m1 },
118 { X86::ROR16rCL, X86::ROR16mCL },
119 { X86::ROR16ri, X86::ROR16mi },
120 { X86::ROR32r1, X86::ROR32m1 },
121 { X86::ROR32rCL, X86::ROR32mCL },
122 { X86::ROR32ri, X86::ROR32mi },
123 { X86::ROR64r1, X86::ROR64m1 },
124 { X86::ROR64rCL, X86::ROR64mCL },
125 { X86::ROR64ri, X86::ROR64mi },
126 { X86::ROR8r1, X86::ROR8m1 },
127 { X86::ROR8rCL, X86::ROR8mCL },
128 { X86::ROR8ri, X86::ROR8mi },
129 { X86::SAR16r1, X86::SAR16m1 },
130 { X86::SAR16rCL, X86::SAR16mCL },
131 { X86::SAR16ri, X86::SAR16mi },
132 { X86::SAR32r1, X86::SAR32m1 },
133 { X86::SAR32rCL, X86::SAR32mCL },
134 { X86::SAR32ri, X86::SAR32mi },
135 { X86::SAR64r1, X86::SAR64m1 },
136 { X86::SAR64rCL, X86::SAR64mCL },
137 { X86::SAR64ri, X86::SAR64mi },
138 { X86::SAR8r1, X86::SAR8m1 },
139 { X86::SAR8rCL, X86::SAR8mCL },
140 { X86::SAR8ri, X86::SAR8mi },
141 { X86::SBB32ri, X86::SBB32mi },
142 { X86::SBB32ri8, X86::SBB32mi8 },
143 { X86::SBB32rr, X86::SBB32mr },
144 { X86::SBB64ri32, X86::SBB64mi32 },
145 { X86::SBB64ri8, X86::SBB64mi8 },
146 { X86::SBB64rr, X86::SBB64mr },
147 { X86::SHL16r1, X86::SHL16m1 },
148 { X86::SHL16rCL, X86::SHL16mCL },
149 { X86::SHL16ri, X86::SHL16mi },
150 { X86::SHL32r1, X86::SHL32m1 },
151 { X86::SHL32rCL, X86::SHL32mCL },
152 { X86::SHL32ri, X86::SHL32mi },
153 { X86::SHL64r1, X86::SHL64m1 },
154 { X86::SHL64rCL, X86::SHL64mCL },
155 { X86::SHL64ri, X86::SHL64mi },
156 { X86::SHL8r1, X86::SHL8m1 },
157 { X86::SHL8rCL, X86::SHL8mCL },
158 { X86::SHL8ri, X86::SHL8mi },
159 { X86::SHLD16rrCL, X86::SHLD16mrCL },
160 { X86::SHLD16rri8, X86::SHLD16mri8 },
161 { X86::SHLD32rrCL, X86::SHLD32mrCL },
162 { X86::SHLD32rri8, X86::SHLD32mri8 },
163 { X86::SHLD64rrCL, X86::SHLD64mrCL },
164 { X86::SHLD64rri8, X86::SHLD64mri8 },
165 { X86::SHR16r1, X86::SHR16m1 },
166 { X86::SHR16rCL, X86::SHR16mCL },
167 { X86::SHR16ri, X86::SHR16mi },
168 { X86::SHR32r1, X86::SHR32m1 },
169 { X86::SHR32rCL, X86::SHR32mCL },
170 { X86::SHR32ri, X86::SHR32mi },
171 { X86::SHR64r1, X86::SHR64m1 },
172 { X86::SHR64rCL, X86::SHR64mCL },
173 { X86::SHR64ri, X86::SHR64mi },
174 { X86::SHR8r1, X86::SHR8m1 },
175 { X86::SHR8rCL, X86::SHR8mCL },
176 { X86::SHR8ri, X86::SHR8mi },
177 { X86::SHRD16rrCL, X86::SHRD16mrCL },
178 { X86::SHRD16rri8, X86::SHRD16mri8 },
179 { X86::SHRD32rrCL, X86::SHRD32mrCL },
180 { X86::SHRD32rri8, X86::SHRD32mri8 },
181 { X86::SHRD64rrCL, X86::SHRD64mrCL },
182 { X86::SHRD64rri8, X86::SHRD64mri8 },
183 { X86::SUB16ri, X86::SUB16mi },
184 { X86::SUB16ri8, X86::SUB16mi8 },
185 { X86::SUB16rr, X86::SUB16mr },
186 { X86::SUB32ri, X86::SUB32mi },
187 { X86::SUB32ri8, X86::SUB32mi8 },
188 { X86::SUB32rr, X86::SUB32mr },
189 { X86::SUB64ri32, X86::SUB64mi32 },
190 { X86::SUB64ri8, X86::SUB64mi8 },
191 { X86::SUB64rr, X86::SUB64mr },
192 { X86::SUB8ri, X86::SUB8mi },
193 { X86::SUB8rr, X86::SUB8mr },
194 { X86::XOR16ri, X86::XOR16mi },
195 { X86::XOR16ri8, X86::XOR16mi8 },
196 { X86::XOR16rr, X86::XOR16mr },
197 { X86::XOR32ri, X86::XOR32mi },
198 { X86::XOR32ri8, X86::XOR32mi8 },
199 { X86::XOR32rr, X86::XOR32mr },
200 { X86::XOR64ri32, X86::XOR64mi32 },
201 { X86::XOR64ri8, X86::XOR64mi8 },
202 { X86::XOR64rr, X86::XOR64mr },
203 { X86::XOR8ri, X86::XOR8mi },
204 { X86::XOR8rr, X86::XOR8mr }
205 };
206
207 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
208 unsigned RegOp = OpTbl2Addr[i][0];
209 unsigned MemOp = OpTbl2Addr[i][1];
210 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
211 assert(false && "Duplicated entries?");
212 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
213 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
214 std::make_pair(RegOp, AuxInfo))))
215 AmbEntries.push_back(MemOp);
216 }
217
218 // If the third value is 1, then it's folding either a load or a store.
219 static const unsigned OpTbl0[][3] = {
220 { X86::CALL32r, X86::CALL32m, 1 },
221 { X86::CALL64r, X86::CALL64m, 1 },
222 { X86::CMP16ri, X86::CMP16mi, 1 },
223 { X86::CMP16ri8, X86::CMP16mi8, 1 },
224 { X86::CMP32ri, X86::CMP32mi, 1 },
225 { X86::CMP32ri8, X86::CMP32mi8, 1 },
226 { X86::CMP64ri32, X86::CMP64mi32, 1 },
227 { X86::CMP64ri8, X86::CMP64mi8, 1 },
228 { X86::CMP8ri, X86::CMP8mi, 1 },
229 { X86::DIV16r, X86::DIV16m, 1 },
230 { X86::DIV32r, X86::DIV32m, 1 },
231 { X86::DIV64r, X86::DIV64m, 1 },
232 { X86::DIV8r, X86::DIV8m, 1 },
233 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
234 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
235 { X86::IDIV16r, X86::IDIV16m, 1 },
236 { X86::IDIV32r, X86::IDIV32m, 1 },
237 { X86::IDIV64r, X86::IDIV64m, 1 },
238 { X86::IDIV8r, X86::IDIV8m, 1 },
239 { X86::IMUL16r, X86::IMUL16m, 1 },
240 { X86::IMUL32r, X86::IMUL32m, 1 },
241 { X86::IMUL64r, X86::IMUL64m, 1 },
242 { X86::IMUL8r, X86::IMUL8m, 1 },
243 { X86::JMP32r, X86::JMP32m, 1 },
244 { X86::JMP64r, X86::JMP64m, 1 },
245 { X86::MOV16ri, X86::MOV16mi, 0 },
246 { X86::MOV16rr, X86::MOV16mr, 0 },
247 { X86::MOV16to16_, X86::MOV16_mr, 0 },
248 { X86::MOV32ri, X86::MOV32mi, 0 },
249 { X86::MOV32rr, X86::MOV32mr, 0 },
250 { X86::MOV32to32_, X86::MOV32_mr, 0 },
251 { X86::MOV64ri32, X86::MOV64mi32, 0 },
252 { X86::MOV64rr, X86::MOV64mr, 0 },
253 { X86::MOV8ri, X86::MOV8mi, 0 },
254 { X86::MOV8rr, X86::MOV8mr, 0 },
255 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
256 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
257 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
258 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
259 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
260 { X86::MOVSDrr, X86::MOVSDmr, 0 },
261 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
262 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
263 { X86::MOVSSrr, X86::MOVSSmr, 0 },
264 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
265 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
266 { X86::MUL16r, X86::MUL16m, 1 },
267 { X86::MUL32r, X86::MUL32m, 1 },
268 { X86::MUL64r, X86::MUL64m, 1 },
269 { X86::MUL8r, X86::MUL8m, 1 },
270 { X86::SETAEr, X86::SETAEm, 0 },
271 { X86::SETAr, X86::SETAm, 0 },
272 { X86::SETBEr, X86::SETBEm, 0 },
273 { X86::SETBr, X86::SETBm, 0 },
274 { X86::SETEr, X86::SETEm, 0 },
275 { X86::SETGEr, X86::SETGEm, 0 },
276 { X86::SETGr, X86::SETGm, 0 },
277 { X86::SETLEr, X86::SETLEm, 0 },
278 { X86::SETLr, X86::SETLm, 0 },
279 { X86::SETNEr, X86::SETNEm, 0 },
280 { X86::SETNPr, X86::SETNPm, 0 },
281 { X86::SETNSr, X86::SETNSm, 0 },
282 { X86::SETPr, X86::SETPm, 0 },
283 { X86::SETSr, X86::SETSm, 0 },
284 { X86::TAILJMPr, X86::TAILJMPm, 1 },
285 { X86::TEST16ri, X86::TEST16mi, 1 },
286 { X86::TEST32ri, X86::TEST32mi, 1 },
287 { X86::TEST64ri32, X86::TEST64mi32, 1 },
288 { X86::TEST8ri, X86::TEST8mi, 1 },
289 { X86::XCHG16rr, X86::XCHG16mr, 0 },
290 { X86::XCHG32rr, X86::XCHG32mr, 0 },
291 { X86::XCHG64rr, X86::XCHG64mr, 0 },
292 { X86::XCHG8rr, X86::XCHG8mr, 0 }
293 };
294
295 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
296 unsigned RegOp = OpTbl0[i][0];
297 unsigned MemOp = OpTbl0[i][1];
298 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
299 assert(false && "Duplicated entries?");
300 unsigned FoldedLoad = OpTbl0[i][2];
301 // Index 0, folded load or store.
302 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
303 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
304 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
305 std::make_pair(RegOp, AuxInfo))))
306 AmbEntries.push_back(MemOp);
307 }
308
309 static const unsigned OpTbl1[][2] = {
310 { X86::CMP16rr, X86::CMP16rm },
311 { X86::CMP32rr, X86::CMP32rm },
312 { X86::CMP64rr, X86::CMP64rm },
313 { X86::CMP8rr, X86::CMP8rm },
314 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
315 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
316 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
317 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
318 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
319 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
320 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
321 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
322 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
323 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
324 { X86::FsMOVAPDrr, X86::MOVSDrm },
325 { X86::FsMOVAPSrr, X86::MOVSSrm },
326 { X86::IMUL16rri, X86::IMUL16rmi },
327 { X86::IMUL16rri8, X86::IMUL16rmi8 },
328 { X86::IMUL32rri, X86::IMUL32rmi },
329 { X86::IMUL32rri8, X86::IMUL32rmi8 },
330 { X86::IMUL64rri32, X86::IMUL64rmi32 },
331 { X86::IMUL64rri8, X86::IMUL64rmi8 },
332 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
333 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
334 { X86::Int_COMISDrr, X86::Int_COMISDrm },
335 { X86::Int_COMISSrr, X86::Int_COMISSrm },
336 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
337 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
338 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
339 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
340 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
341 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
342 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
343 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
344 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
345 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
346 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
347 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
348 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
349 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
350 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
351 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
352 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
353 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
354 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
355 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
356 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
357 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
358 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
359 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
360 { X86::MOV16rr, X86::MOV16rm },
361 { X86::MOV16to16_, X86::MOV16_rm },
362 { X86::MOV32rr, X86::MOV32rm },
363 { X86::MOV32to32_, X86::MOV32_rm },
364 { X86::MOV64rr, X86::MOV64rm },
365 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
366 { X86::MOV64toSDrr, X86::MOV64toSDrm },
367 { X86::MOV8rr, X86::MOV8rm },
368 { X86::MOVAPDrr, X86::MOVAPDrm },
369 { X86::MOVAPSrr, X86::MOVAPSrm },
370 { X86::MOVDDUPrr, X86::MOVDDUPrm },
371 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
372 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
373 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
374 { X86::MOVSDrr, X86::MOVSDrm },
375 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
376 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
377 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
378 { X86::MOVSSrr, X86::MOVSSrm },
379 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
380 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
381 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
382 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
383 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
384 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
385 { X86::MOVUPDrr, X86::MOVUPDrm },
386 { X86::MOVUPSrr, X86::MOVUPSrm },
387 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
388 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
389 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
390 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
391 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
392 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
393 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
394 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
395 { X86::PSHUFDri, X86::PSHUFDmi },
396 { X86::PSHUFHWri, X86::PSHUFHWmi },
397 { X86::PSHUFLWri, X86::PSHUFLWmi },
398 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
399 { X86::RCPPSr, X86::RCPPSm },
400 { X86::RCPPSr_Int, X86::RCPPSm_Int },
401 { X86::RSQRTPSr, X86::RSQRTPSm },
402 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
403 { X86::RSQRTSSr, X86::RSQRTSSm },
404 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
405 { X86::SQRTPDr, X86::SQRTPDm },
406 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
407 { X86::SQRTPSr, X86::SQRTPSm },
408 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
409 { X86::SQRTSDr, X86::SQRTSDm },
410 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
411 { X86::SQRTSSr, X86::SQRTSSm },
412 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
413 { X86::TEST16rr, X86::TEST16rm },
414 { X86::TEST32rr, X86::TEST32rm },
415 { X86::TEST64rr, X86::TEST64rm },
416 { X86::TEST8rr, X86::TEST8rm },
417 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
418 { X86::UCOMISDrr, X86::UCOMISDrm },
419 { X86::UCOMISSrr, X86::UCOMISSrm },
420 { X86::XCHG16rr, X86::XCHG16rm },
421 { X86::XCHG32rr, X86::XCHG32rm },
422 { X86::XCHG64rr, X86::XCHG64rm },
423 { X86::XCHG8rr, X86::XCHG8rm }
424 };
425
426 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
427 unsigned RegOp = OpTbl1[i][0];
428 unsigned MemOp = OpTbl1[i][1];
429 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
430 assert(false && "Duplicated entries?");
431 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
432 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
433 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
434 std::make_pair(RegOp, AuxInfo))))
435 AmbEntries.push_back(MemOp);
436 }
437
438 static const unsigned OpTbl2[][2] = {
439 { X86::ADC32rr, X86::ADC32rm },
440 { X86::ADC64rr, X86::ADC64rm },
441 { X86::ADD16rr, X86::ADD16rm },
442 { X86::ADD32rr, X86::ADD32rm },
443 { X86::ADD64rr, X86::ADD64rm },
444 { X86::ADD8rr, X86::ADD8rm },
445 { X86::ADDPDrr, X86::ADDPDrm },
446 { X86::ADDPSrr, X86::ADDPSrm },
447 { X86::ADDSDrr, X86::ADDSDrm },
448 { X86::ADDSSrr, X86::ADDSSrm },
449 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
450 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
451 { X86::AND16rr, X86::AND16rm },
452 { X86::AND32rr, X86::AND32rm },
453 { X86::AND64rr, X86::AND64rm },
454 { X86::AND8rr, X86::AND8rm },
455 { X86::ANDNPDrr, X86::ANDNPDrm },
456 { X86::ANDNPSrr, X86::ANDNPSrm },
457 { X86::ANDPDrr, X86::ANDPDrm },
458 { X86::ANDPSrr, X86::ANDPSrm },
459 { X86::CMOVA16rr, X86::CMOVA16rm },
460 { X86::CMOVA32rr, X86::CMOVA32rm },
461 { X86::CMOVA64rr, X86::CMOVA64rm },
462 { X86::CMOVAE16rr, X86::CMOVAE16rm },
463 { X86::CMOVAE32rr, X86::CMOVAE32rm },
464 { X86::CMOVAE64rr, X86::CMOVAE64rm },
465 { X86::CMOVB16rr, X86::CMOVB16rm },
466 { X86::CMOVB32rr, X86::CMOVB32rm },
467 { X86::CMOVB64rr, X86::CMOVB64rm },
468 { X86::CMOVBE16rr, X86::CMOVBE16rm },
469 { X86::CMOVBE32rr, X86::CMOVBE32rm },
470 { X86::CMOVBE64rr, X86::CMOVBE64rm },
471 { X86::CMOVE16rr, X86::CMOVE16rm },
472 { X86::CMOVE32rr, X86::CMOVE32rm },
473 { X86::CMOVE64rr, X86::CMOVE64rm },
474 { X86::CMOVG16rr, X86::CMOVG16rm },
475 { X86::CMOVG32rr, X86::CMOVG32rm },
476 { X86::CMOVG64rr, X86::CMOVG64rm },
477 { X86::CMOVGE16rr, X86::CMOVGE16rm },
478 { X86::CMOVGE32rr, X86::CMOVGE32rm },
479 { X86::CMOVGE64rr, X86::CMOVGE64rm },
480 { X86::CMOVL16rr, X86::CMOVL16rm },
481 { X86::CMOVL32rr, X86::CMOVL32rm },
482 { X86::CMOVL64rr, X86::CMOVL64rm },
483 { X86::CMOVLE16rr, X86::CMOVLE16rm },
484 { X86::CMOVLE32rr, X86::CMOVLE32rm },
485 { X86::CMOVLE64rr, X86::CMOVLE64rm },
486 { X86::CMOVNE16rr, X86::CMOVNE16rm },
487 { X86::CMOVNE32rr, X86::CMOVNE32rm },
488 { X86::CMOVNE64rr, X86::CMOVNE64rm },
489 { X86::CMOVNP16rr, X86::CMOVNP16rm },
490 { X86::CMOVNP32rr, X86::CMOVNP32rm },
491 { X86::CMOVNP64rr, X86::CMOVNP64rm },
492 { X86::CMOVNS16rr, X86::CMOVNS16rm },
493 { X86::CMOVNS32rr, X86::CMOVNS32rm },
494 { X86::CMOVNS64rr, X86::CMOVNS64rm },
495 { X86::CMOVP16rr, X86::CMOVP16rm },
496 { X86::CMOVP32rr, X86::CMOVP32rm },
497 { X86::CMOVP64rr, X86::CMOVP64rm },
498 { X86::CMOVS16rr, X86::CMOVS16rm },
499 { X86::CMOVS32rr, X86::CMOVS32rm },
500 { X86::CMOVS64rr, X86::CMOVS64rm },
501 { X86::CMPPDrri, X86::CMPPDrmi },
502 { X86::CMPPSrri, X86::CMPPSrmi },
503 { X86::CMPSDrr, X86::CMPSDrm },
504 { X86::CMPSSrr, X86::CMPSSrm },
505 { X86::DIVPDrr, X86::DIVPDrm },
506 { X86::DIVPSrr, X86::DIVPSrm },
507 { X86::DIVSDrr, X86::DIVSDrm },
508 { X86::DIVSSrr, X86::DIVSSrm },
509 { X86::HADDPDrr, X86::HADDPDrm },
510 { X86::HADDPSrr, X86::HADDPSrm },
511 { X86::HSUBPDrr, X86::HSUBPDrm },
512 { X86::HSUBPSrr, X86::HSUBPSrm },
513 { X86::IMUL16rr, X86::IMUL16rm },
514 { X86::IMUL32rr, X86::IMUL32rm },
515 { X86::IMUL64rr, X86::IMUL64rm },
516 { X86::MAXPDrr, X86::MAXPDrm },
517 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
518 { X86::MAXPSrr, X86::MAXPSrm },
519 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
520 { X86::MAXSDrr, X86::MAXSDrm },
521 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
522 { X86::MAXSSrr, X86::MAXSSrm },
523 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
524 { X86::MINPDrr, X86::MINPDrm },
525 { X86::MINPDrr_Int, X86::MINPDrm_Int },
526 { X86::MINPSrr, X86::MINPSrm },
527 { X86::MINPSrr_Int, X86::MINPSrm_Int },
528 { X86::MINSDrr, X86::MINSDrm },
529 { X86::MINSDrr_Int, X86::MINSDrm_Int },
530 { X86::MINSSrr, X86::MINSSrm },
531 { X86::MINSSrr_Int, X86::MINSSrm_Int },
532 { X86::MULPDrr, X86::MULPDrm },
533 { X86::MULPSrr, X86::MULPSrm },
534 { X86::MULSDrr, X86::MULSDrm },
535 { X86::MULSSrr, X86::MULSSrm },
536 { X86::OR16rr, X86::OR16rm },
537 { X86::OR32rr, X86::OR32rm },
538 { X86::OR64rr, X86::OR64rm },
539 { X86::OR8rr, X86::OR8rm },
540 { X86::ORPDrr, X86::ORPDrm },
541 { X86::ORPSrr, X86::ORPSrm },
542 { X86::PACKSSDWrr, X86::PACKSSDWrm },
543 { X86::PACKSSWBrr, X86::PACKSSWBrm },
544 { X86::PACKUSWBrr, X86::PACKUSWBrm },
545 { X86::PADDBrr, X86::PADDBrm },
546 { X86::PADDDrr, X86::PADDDrm },
547 { X86::PADDQrr, X86::PADDQrm },
548 { X86::PADDSBrr, X86::PADDSBrm },
549 { X86::PADDSWrr, X86::PADDSWrm },
550 { X86::PADDWrr, X86::PADDWrm },
551 { X86::PANDNrr, X86::PANDNrm },
552 { X86::PANDrr, X86::PANDrm },
553 { X86::PAVGBrr, X86::PAVGBrm },
554 { X86::PAVGWrr, X86::PAVGWrm },
555 { X86::PCMPEQBrr, X86::PCMPEQBrm },
556 { X86::PCMPEQDrr, X86::PCMPEQDrm },
557 { X86::PCMPEQWrr, X86::PCMPEQWrm },
558 { X86::PCMPGTBrr, X86::PCMPGTBrm },
559 { X86::PCMPGTDrr, X86::PCMPGTDrm },
560 { X86::PCMPGTWrr, X86::PCMPGTWrm },
561 { X86::PINSRWrri, X86::PINSRWrmi },
562 { X86::PMADDWDrr, X86::PMADDWDrm },
563 { X86::PMAXSWrr, X86::PMAXSWrm },
564 { X86::PMAXUBrr, X86::PMAXUBrm },
565 { X86::PMINSWrr, X86::PMINSWrm },
566 { X86::PMINUBrr, X86::PMINUBrm },
567 { X86::PMULHUWrr, X86::PMULHUWrm },
568 { X86::PMULHWrr, X86::PMULHWrm },
569 { X86::PMULLWrr, X86::PMULLWrm },
570 { X86::PMULUDQrr, X86::PMULUDQrm },
571 { X86::PORrr, X86::PORrm },
572 { X86::PSADBWrr, X86::PSADBWrm },
573 { X86::PSLLDrr, X86::PSLLDrm },
574 { X86::PSLLQrr, X86::PSLLQrm },
575 { X86::PSLLWrr, X86::PSLLWrm },
576 { X86::PSRADrr, X86::PSRADrm },
577 { X86::PSRAWrr, X86::PSRAWrm },
578 { X86::PSRLDrr, X86::PSRLDrm },
579 { X86::PSRLQrr, X86::PSRLQrm },
580 { X86::PSRLWrr, X86::PSRLWrm },
581 { X86::PSUBBrr, X86::PSUBBrm },
582 { X86::PSUBDrr, X86::PSUBDrm },
583 { X86::PSUBSBrr, X86::PSUBSBrm },
584 { X86::PSUBSWrr, X86::PSUBSWrm },
585 { X86::PSUBWrr, X86::PSUBWrm },
586 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
587 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
588 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
589 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
590 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
591 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
592 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
593 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
594 { X86::PXORrr, X86::PXORrm },
595 { X86::SBB32rr, X86::SBB32rm },
596 { X86::SBB64rr, X86::SBB64rm },
597 { X86::SHUFPDrri, X86::SHUFPDrmi },
598 { X86::SHUFPSrri, X86::SHUFPSrmi },
599 { X86::SUB16rr, X86::SUB16rm },
600 { X86::SUB32rr, X86::SUB32rm },
601 { X86::SUB64rr, X86::SUB64rm },
602 { X86::SUB8rr, X86::SUB8rm },
603 { X86::SUBPDrr, X86::SUBPDrm },
604 { X86::SUBPSrr, X86::SUBPSrm },
605 { X86::SUBSDrr, X86::SUBSDrm },
606 { X86::SUBSSrr, X86::SUBSSrm },
607 // FIXME: TEST*rr -> swapped operand of TEST*mr.
608 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
609 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
610 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
611 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
612 { X86::XOR16rr, X86::XOR16rm },
613 { X86::XOR32rr, X86::XOR32rm },
614 { X86::XOR64rr, X86::XOR64rm },
615 { X86::XOR8rr, X86::XOR8rm },
616 { X86::XORPDrr, X86::XORPDrm },
617 { X86::XORPSrr, X86::XORPSrm }
618 };
619
620 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
621 unsigned RegOp = OpTbl2[i][0];
622 unsigned MemOp = OpTbl2[i][1];
623 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
624 assert(false && "Duplicated entries?");
625 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
626 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
627 std::make_pair(RegOp, AuxInfo))))
628 AmbEntries.push_back(MemOp);
629 }
630
631 // Remove ambiguous entries.
632 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
31633 }
32634
33635 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
10251627 return true;
10261628 }
10271629
1630 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1631 SmallVector &MOs,
1632 MachineInstr *MI, const TargetInstrInfo &TII) {
1633 // Create the base instruction with the memory operand as the first part.
1634 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1635 MachineInstrBuilder MIB(NewMI);
1636 unsigned NumAddrOps = MOs.size();
1637 for (unsigned i = 0; i != NumAddrOps; ++i)
1638 MIB = X86InstrAddOperand(MIB, MOs[i]);
1639 if (NumAddrOps < 4) // FrameIndex only
1640 MIB.addImm(1).addReg(0).addImm(0);
1641
1642 // Loop over the rest of the ri operands, converting them over.
1643 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
1644 for (unsigned i = 0; i != NumOps; ++i) {
1645 MachineOperand &MO = MI->getOperand(i+2);
1646 MIB = X86InstrAddOperand(MIB, MO);
1647 }
1648 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1649 MachineOperand &MO = MI->getOperand(i);
1650 MIB = X86InstrAddOperand(MIB, MO);
1651 }
1652 return MIB;
1653 }
1654
1655 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1656 SmallVector &MOs,
1657 MachineInstr *MI, const TargetInstrInfo &TII) {
1658 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1659 MachineInstrBuilder MIB(NewMI);
1660
1661 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1662 MachineOperand &MO = MI->getOperand(i);
1663 if (i == OpNo) {
1664 assert(MO.isRegister() && "Expected to fold into reg operand!");
1665 unsigned NumAddrOps = MOs.size();
1666 for (unsigned i = 0; i != NumAddrOps; ++i)
1667 MIB = X86InstrAddOperand(MIB, MOs[i]);
1668 if (NumAddrOps < 4) // FrameIndex only
1669 MIB.addImm(1).addReg(0).addImm(0);
1670 } else {
1671 MIB = X86InstrAddOperand(MIB, MO);
1672 }
1673 }
1674 return MIB;
1675 }
1676
1677 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1678 SmallVector &MOs,
1679 MachineInstr *MI) {
1680 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1681
1682 unsigned NumAddrOps = MOs.size();
1683 for (unsigned i = 0; i != NumAddrOps; ++i)
1684 MIB = X86InstrAddOperand(MIB, MOs[i]);
1685 if (NumAddrOps < 4) // FrameIndex only
1686 MIB.addImm(1).addReg(0).addImm(0);
1687 return MIB.addImm(0);
1688 }
1689
1690 MachineInstr*
1691 X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1692 SmallVector &MOs) const {
1693 const DenseMap *OpcodeTablePtr = NULL;
1694 bool isTwoAddrFold = false;
1695 unsigned NumOps = getNumOperands(MI->getOpcode());
1696 bool isTwoAddr = NumOps > 1 &&
1697 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
1698
1699 MachineInstr *NewMI = NULL;
1700 // Folding a memory location into the two-address part of a two-address
1701 // instruction is different than folding it other places. It requires
1702 // replacing the *two* registers with the memory location.
1703 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1704 MI->getOperand(0).isRegister() &&
1705 MI->getOperand(1).isRegister() &&
1706 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1707 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1708 isTwoAddrFold = true;
1709 } else if (i == 0) { // If operand 0
1710 if (MI->getOpcode() == X86::MOV16r0)
1711 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
1712 else if (MI->getOpcode() == X86::MOV32r0)
1713 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
1714 else if (MI->getOpcode() == X86::MOV64r0)
1715 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
1716 else if (MI->getOpcode() == X86::MOV8r0)
1717 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1718 if (NewMI) {
1719 NewMI->copyKillDeadInfo(MI);
1720 return NewMI;
1721 }
1722
1723 OpcodeTablePtr = &RegOp2MemOpTable0;
1724 } else if (i == 1) {
1725 OpcodeTablePtr = &RegOp2MemOpTable1;
1726 } else if (i == 2) {
1727 OpcodeTablePtr = &RegOp2MemOpTable2;
1728 }
1729
1730 // If table selected...
1731 if (OpcodeTablePtr) {
1732 // Find the Opcode to fuse
1733 DenseMap::iterator I =
1734 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1735 if (I != OpcodeTablePtr->end()) {
1736 if (isTwoAddrFold)
1737 NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this);
1738 else
1739 NewMI = FuseInst(I->second, i, MOs, MI, *this);
1740 NewMI->copyKillDeadInfo(MI);
1741 return NewMI;
1742 }
1743 }
1744
1745 // No fusion
1746 if (PrintFailedFusing)
1747 cerr << "We failed to fuse ("
1748 << ((i == 1) ? "r" : "s") << "): " << *MI;
1749 return NULL;
1750 }
1751
1752
1753 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI,
1754 SmallVectorImpl &Ops,
1755 int FrameIndex) const {
1756 // Check switch flag
1757 if (NoFusing) return NULL;
1758
1759 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1760 unsigned NewOpc = 0;
1761 switch (MI->getOpcode()) {
1762 default: return NULL;
1763 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1764 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1765 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1766 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1767 }
1768 // Change to CMPXXri r, 0 first.
1769 MI->setInstrDescriptor(get(NewOpc));
1770 MI->getOperand(1).ChangeToImmediate(0);
1771 } else if (Ops.size() != 1)
1772 return NULL;
1773
1774 SmallVector MOs;
1775 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
1776 return foldMemoryOperand(MI, Ops[0], MOs);
1777 }
1778
1779 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI,
1780 SmallVectorImpl &Ops,
1781 MachineInstr *LoadMI) const {
1782 // Check switch flag
1783 if (NoFusing) return NULL;
1784
1785 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1786 unsigned NewOpc = 0;
1787 switch (MI->getOpcode()) {
1788 default: return NULL;
1789 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1790 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1791 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1792 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1793 }
1794 // Change to CMPXXri r, 0 first.
1795 MI->setInstrDescriptor(get(NewOpc));
1796 MI->getOperand(1).ChangeToImmediate(0);
1797 } else if (Ops.size() != 1)
1798 return NULL;
1799
1800 SmallVector MOs;
1801 unsigned NumOps = getNumOperands(LoadMI->getOpcode());
1802 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1803 MOs.push_back(LoadMI->getOperand(i));
1804 return foldMemoryOperand(MI, Ops[0], MOs);
1805 }
1806
1807
1808 bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
1809 SmallVectorImpl &Ops) const {
1810 // Check switch flag
1811 if (NoFusing) return 0;
1812
1813 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1814 switch (MI->getOpcode()) {
1815 default: return false;
1816 case X86::TEST8rr:
1817 case X86::TEST16rr:
1818 case X86::TEST32rr:
1819 case X86::TEST64rr:
1820 return true;
1821 }
1822 }
1823
1824 if (Ops.size() != 1)
1825 return false;
1826
1827 unsigned OpNum = Ops[0];
1828 unsigned Opc = MI->getOpcode();
1829 unsigned NumOps = getNumOperands(Opc);
1830 bool isTwoAddr = NumOps > 1 &&
1831 getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
1832
1833 // Folding a memory location into the two-address part of a two-address
1834 // instruction is different than folding it other places. It requires
1835 // replacing the *two* registers with the memory location.
1836 const DenseMap *OpcodeTablePtr = NULL;
1837 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1838 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1839 } else if (OpNum == 0) { // If operand 0
1840 switch (Opc) {
1841 case X86::MOV16r0:
1842 case X86::MOV32r0:
1843 case X86::MOV64r0:
1844 case X86::MOV8r0:
1845 return true;
1846 default: break;
1847 }
1848 OpcodeTablePtr = &RegOp2MemOpTable0;
1849 } else if (OpNum == 1) {
1850 OpcodeTablePtr = &RegOp2MemOpTable1;
1851 } else if (OpNum == 2) {
1852 OpcodeTablePtr = &RegOp2MemOpTable2;
1853 }
1854
1855 if (OpcodeTablePtr) {
1856 // Find the Opcode to fuse
1857 DenseMap::iterator I =
1858 OpcodeTablePtr->find((unsigned*)Opc);
1859 if (I != OpcodeTablePtr->end())
1860 return true;
1861 }
1862 return false;
1863 }
1864
1865 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1866 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1867 SmallVectorImpl &NewMIs) const {
1868 DenseMap >::iterator I =
1869 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
1870 if (I == MemOp2RegOpTable.end())
1871 return false;
1872 unsigned Opc = I->second.first;
1873 unsigned Index = I->second.second & 0xf;
1874 bool FoldedLoad = I->second.second & (1 << 4);
1875 bool FoldedStore = I->second.second & (1 << 5);
1876 if (UnfoldLoad && !FoldedLoad)
1877 return false;
1878 UnfoldLoad &= FoldedLoad;
1879 if (UnfoldStore && !FoldedStore)
1880 return false;
1881 UnfoldStore &= FoldedStore;
1882
1883 const TargetInstrDescriptor &TID = get(Opc);
1884 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1885 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1886 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
1887 SmallVector AddrOps;
1888 SmallVector BeforeOps;
1889 SmallVector AfterOps;
1890 SmallVector ImpOps;
1891 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1892 MachineOperand &Op = MI->getOperand(i);
1893 if (i >= Index && i < Index+4)
1894 AddrOps.push_back(Op);
1895 else if (Op.isRegister() && Op.isImplicit())
1896 ImpOps.push_back(Op);
1897 else if (i < Index)
1898 BeforeOps.push_back(Op);
1899 else if (i > Index)
1900 AfterOps.push_back(Op);
1901 }
1902
1903 // Emit the load instruction.
1904 if (UnfoldLoad) {
1905 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
1906 if (UnfoldStore) {
1907 // Address operands cannot be marked isKill.
1908 for (unsigned i = 1; i != 5; ++i) {
1909 MachineOperand &MO = NewMIs[0]->getOperand(i);
1910 if (MO.isRegister())
1911 MO.setIsKill(false);
1912 }
1913 }
1914 }
1915
1916 // Emit the data processing instruction.
1917 MachineInstr *DataMI = new MachineInstr(TID, true);
1918 MachineInstrBuilder MIB(DataMI);
1919
1920 if (FoldedStore)
1921 MIB.addReg(Reg, true);
1922 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
1923 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
1924 if (FoldedLoad)
1925 MIB.addReg(Reg);
1926 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
1927 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
1928 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
1929 MachineOperand &MO = ImpOps[i];
1930 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
1931 }
1932 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
1933 unsigned NewOpc = 0;
1934 switch (DataMI->getOpcode()) {
1935 default: break;
1936 case X86::CMP64ri32:
1937 case X86::CMP32ri:
1938 case X86::CMP16ri:
1939 case X86::CMP8ri: {
1940 MachineOperand &MO0 = DataMI->getOperand(0);
1941 MachineOperand &MO1 = DataMI->getOperand(1);
1942 if (MO1.getImm() == 0) {
1943 switch (DataMI->getOpcode()) {
1944 default: break;
1945 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
1946 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
1947 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
1948 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
1949 }
1950 DataMI->setInstrDescriptor(get(NewOpc));
1951 MO1.ChangeToRegister(MO0.getReg(), false);
1952 }
1953 }
1954 }
1955 NewMIs.push_back(DataMI);
1956
1957 // Emit the store instruction.
1958 if (UnfoldStore) {
1959 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1960 const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1961 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
1962 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
1963 }
1964
1965 return true;
1966 }
1967
1968 bool
1969 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1970 SmallVectorImpl &NewNodes) const {
1971 if (!N->isTargetOpcode())
1972 return false;
1973
1974 DenseMap >::iterator I =
1975 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
1976 if (I == MemOp2RegOpTable.end())
1977 return false;
1978 unsigned Opc = I->second.first;
1979 unsigned Index = I->second.second & 0xf;
1980 bool FoldedLoad = I->second.second & (1 << 4);
1981 bool FoldedStore = I->second.second & (1 << 5);
1982 const TargetInstrDescriptor &TID = get(Opc);
1983 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1984 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1985 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
1986 std::vector AddrOps;
1987 std::vector BeforeOps;
1988 std::vector AfterOps;
1989 unsigned NumOps = N->getNumOperands();
1990 for (unsigned i = 0; i != NumOps-1; ++i) {
1991 SDOperand Op = N->getOperand(i);
1992 if (i >= Index && i < Index+4)
1993 AddrOps.push_back(Op);
1994 else if (i < Index)
1995 BeforeOps.push_back(Op);
1996 else if (i > Index)
1997 AfterOps.push_back(Op);
1998 }
1999 SDOperand Chain = N->getOperand(NumOps-1);
2000 AddrOps.push_back(Chain);
2001
2002 // Emit the load instruction.
2003 SDNode *Load = 0;
2004 if (FoldedLoad) {
2005 MVT::ValueType VT = *RC->vt_begin();
2006 Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT,
2007 MVT::Other, &AddrOps[0], AddrOps.size());
2008 NewNodes.push_back(Load);
2009 }
2010
2011 // Emit the data processing instruction.
2012 std::vector VTs;
2013 const TargetRegisterClass *DstRC = 0;
2014 if (TID.numDefs > 0) {
2015 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2016 DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
2017 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2018 VTs.push_back(*DstRC->vt_begin());
2019 }
2020 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2021 MVT::ValueType VT = N->getValueType(i);
2022 if (VT != MVT::Other && i >= TID.numDefs)
2023 VTs.push_back(VT);
2024 }
2025 if (Load)
2026 BeforeOps.push_back(SDOperand(Load, 0));
2027 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2028 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2029 NewNodes.push_back(NewNode);
2030
2031 // Emit the store instruction.
2032 if (FoldedStore) {
2033 AddrOps.pop_back();
2034 AddrOps.push_back(SDOperand(NewNode, 0));
2035 AddrOps.push_back(Chain);
2036 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, RI.getStackAlignment()),
2037 MVT::Other, &AddrOps[0], AddrOps.size());
2038 NewNodes.push_back(Store);
2039 }
2040
2041 return true;
2042 }
2043
2044 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2045 bool UnfoldLoad, bool UnfoldStore) const {
2046 DenseMap >::iterator I =
2047 MemOp2RegOpTable.find((unsigned*)Opc);
2048 if (I == MemOp2RegOpTable.end())
2049 return 0;
2050 bool FoldedLoad = I->second.second & (1 << 4);
2051 bool FoldedStore = I->second.second & (1 << 5);
2052 if (UnfoldLoad && !FoldedLoad)
2053 return 0;
2054 if (UnfoldStore && !FoldedStore)
2055 return 0;
2056 return I->second.first;
2057 }
2058
10282059 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
10292060 if (MBB.empty()) return false;
10302061
224224 class X86InstrInfo : public TargetInstrInfoImpl {
225225 X86TargetMachine &TM;
226226 const X86RegisterInfo RI;
227
228 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
229 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
230 ///
231 DenseMap RegOp2MemOpTable2Addr;
232 DenseMap RegOp2MemOpTable0;
233 DenseMap RegOp2MemOpTable1;
234 DenseMap RegOp2MemOpTable2;
235
236 /// MemOp2RegOpTable - Load / store unfolding opcode map.
237 ///
238 DenseMap > MemOp2RegOpTable;
239
227240 public:
228241 X86InstrInfo(X86TargetMachine &tm);
229242
304317 MachineBasicBlock::iterator MI,
305318 const std::vector &CSI) const;
306319
320 /// foldMemoryOperand - If this target supports it, fold a load or store of
321 /// the specified stack slot into the specified machine instruction for the
322 /// specified operand(s). If this is possible, the target should perform the
323 /// folding and return true, otherwise it should return false. If it folds
324 /// the instruction, it is likely that the MachineInstruction the iterator
325 /// references has been changed.
326 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
327 SmallVectorImpl &Ops,
328 int FrameIndex) const;
329
330 /// foldMemoryOperand - Same as the previous version except it allows folding
331 /// of any load and store from / to any address, not just from a specific
332 /// stack slot.
333 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
334 SmallVectorImpl &Ops,
335 MachineInstr* LoadMI) const;
336
337 /// canFoldMemoryOperand - Returns true if the specified load / store is
338 /// folding is possible.
339 virtual bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl &) const;
340
341 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
342 /// a store or a load and a store into two or more instruction. If this is
343 /// possible, returns true as well as the new instructions by reference.
344 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
345 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
346 SmallVectorImpl &NewMIs) const;
347
348 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
349 SmallVectorImpl &NewNodes) const;
350
351 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
352 /// instruction after load / store are unfolded from an instruction of the
353 /// specified opcode. It returns zero if the specified unfolding is not
354 /// possible.
355 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
356 bool UnfoldLoad, bool UnfoldStore) const;
357
307358 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
308359 virtual bool ReverseBranchCondition(std::vector &Cond) const;
309360
318369 unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const {
319370 return getBaseOpcodeFor(&get(Opcode));
320371 }
372
373 private:
374 MachineInstr* foldMemoryOperand(MachineInstr* MI,
375 unsigned OpNum,
376 SmallVector &MOs) const;
321377 };
322378
323379 } // End llvm namespace
3232 #include "llvm/Target/TargetInstrInfo.h"
3333 #include "llvm/Target/TargetMachine.h"
3434 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
3635 #include "llvm/ADT/BitVector.h"
3736 #include "llvm/ADT/STLExtras.h"
3837 using namespace llvm;
39
40 namespace {
41 cl::opt
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
44 cl::opt
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
48 cl::Hidden);
49 }
5038
5139 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
5240 const TargetInstrInfo &tii)
6553 StackPtr = X86::ESP;
6654 FramePtr = X86::EBP;
6755 }
68
69 SmallVector AmbEntries;
70 static const unsigned OpTbl2Addr[][2] = {
71 { X86::ADC32ri, X86::ADC32mi },
72 { X86::ADC32ri8, X86::ADC32mi8 },
73 { X86::ADC32rr, X86::ADC32mr },
74 { X86::ADC64ri32, X86::ADC64mi32 },
75 { X86::ADC64ri8, X86::ADC64mi8 },
76 { X86::ADC64rr, X86::ADC64mr },
77 { X86::ADD16ri, X86::ADD16mi },
78 { X86::ADD16ri8, X86::ADD16mi8 },
79 { X86::ADD16rr, X86::ADD16mr },
80 { X86::ADD32ri, X86::ADD32mi },
81 { X86::ADD32ri8, X86::ADD32mi8 },
82 { X86::ADD32rr, X86::ADD32mr },
83 { X86::ADD64ri32, X86::ADD64mi32 },
84 { X86::ADD64ri8, X86::ADD64mi8 },
85 { X86::ADD64rr, X86::ADD64mr },
86 { X86::ADD8ri, X86::ADD8mi },
87 { X86::ADD8rr, X86::ADD8mr },
88 { X86::AND16ri, X86::AND16mi },
89 { X86::AND16ri8, X86::AND16mi8 },
90 { X86::AND16rr, X86::AND16mr },
91 { X86::AND32ri, X86::AND32mi },
92 { X86::AND32ri8, X86::AND32mi8 },
93 { X86::AND32rr, X86::AND32mr },
94 { X86::AND64ri32, X86::AND64mi32 },
95 { X86::AND64ri8, X86::AND64mi8 },
96 { X86::AND64rr, X86::AND64mr },
97 { X86::AND8ri, X86::AND8mi },
98 { X86::AND8rr, X86::AND8mr },
99 { X86::DEC16r, X86::DEC16m },
100 { X86::DEC32r, X86::DEC32m },
101 { X86::DEC64_16r, X86::DEC64_16m },
102 { X86::DEC64_32r, X86::DEC64_32m },
103 { X86::DEC64r, X86::DEC64m },
104 { X86::DEC8r, X86::DEC8m },
105 { X86::INC16r, X86::INC16m },
106 { X86::INC32r, X86::INC32m },
107 { X86::INC64_16r, X86::INC64_16m },
108 { X86::INC64_32r, X86::INC64_32m },
109 { X86::INC64r, X86::INC64m },
110 { X86::INC8r, X86::INC8m },
111 { X86::NEG16r, X86::NEG16m },
112 { X86::NEG32r, X86::NEG32m },
113 { X86::NEG64r, X86::NEG64m },
114 { X86::NEG8r, X86::NEG8m },
115 { X86::NOT16r, X86::NOT16m },
116 { X86::NOT32r, X86::NOT32m },
117 { X86::NOT64r, X86::NOT64m },
118 { X86::NOT8r, X86::NOT8m },
119 { X86::OR16ri, X86::OR16mi },
120 { X86::OR16ri8, X86::OR16mi8 },
121 { X86::OR16rr, X86::OR16mr },
122 { X86::OR32ri, X86::OR32mi },
123 { X86::OR32ri8, X86::OR32mi8 },
124 { X86::OR32rr, X86::OR32mr },
125 { X86::OR64ri32, X86::OR64mi32 },
126 { X86::OR64ri8, X86::OR64mi8 },
127 { X86::OR64rr, X86::OR64mr },
128 { X86::OR8ri, X86::OR8mi },
129 { X86::OR8rr, X86::OR8mr },
130 { X86::ROL16r1, X86::ROL16m1 },
131 { X86::ROL16rCL, X86::ROL16mCL },
132 { X86::ROL16ri, X86::ROL16mi },
133 { X86::ROL32r1, X86::ROL32m1 },
134 { X86::ROL32rCL, X86::ROL32mCL },
135 { X86::ROL32ri, X86::ROL32mi },
136 { X86::ROL64r1, X86::ROL64m1 },
137 { X86::ROL64rCL, X86::ROL64mCL },
138 { X86::ROL64ri, X86::ROL64mi },
139 { X86::ROL8r1, X86::ROL8m1 },
140 { X86::ROL8rCL, X86::ROL8mCL },
141 { X86::ROL8ri, X86::ROL8mi },
142 { X86::ROR16r1, X86::ROR16m1 },
143 { X86::ROR16rCL, X86::ROR16mCL },
144 { X86::ROR16ri, X86::ROR16mi },
145 { X86::ROR32r1, X86::ROR32m1 },
146 { X86::ROR32rCL, X86::ROR32mCL },
147 { X86::ROR32ri, X86::ROR32mi },
148 { X86::ROR64r1, X86::ROR64m1 },
149 { X86::ROR64rCL, X86::ROR64mCL },
150 { X86::ROR64ri, X86::ROR64mi },
151 { X86::ROR8r1, X86::ROR8m1 },
152 { X86::ROR8rCL, X86::ROR8mCL },
153 { X86::ROR8ri, X86::ROR8mi },
154 { X86::SAR16r1, X86::SAR16m1 },
155 { X86::SAR16rCL, X86::SAR16mCL },
156 { X86::SAR16ri, X86::SAR16mi },
157 { X86::SAR32r1, X86::SAR32m1 },
158 { X86::SAR32rCL, X86::SAR32mCL },
159 { X86::SAR32ri, X86::SAR32mi },
160 { X86::SAR64r1, X86::SAR64m1 },
161 { X86::SAR64rCL, X86::SAR64mCL },
162 { X86::SAR64ri, X86::SAR64mi },
163 { X86::SAR8r1, X86::SAR8m1 },
164 { X86::SAR8rCL, X86::SAR8mCL },
165 { X86::SAR8ri, X86::SAR8mi },
166 { X86::SBB32ri, X86::SBB32mi },
167 { X86::SBB32ri8, X86::SBB32mi8 },
168 { X86::SBB32rr, X86::SBB32mr },
169 { X86::SBB64ri32, X86::SBB64mi32 },
170 { X86::SBB64ri8, X86::SBB64mi8 },
171 { X86::SBB64rr, X86::SBB64mr },
172 { X86::SHL16r1, X86::SHL16m1 },
173 { X86::SHL16rCL, X86::SHL16mCL },
174 { X86::SHL16ri, X86::SHL16mi },
175 { X86::SHL32r1, X86::SHL32m1 },
176 { X86::SHL32rCL, X86::SHL32mCL },
177 { X86::SHL32ri, X86::SHL32mi },
178 { X86::SHL64r1, X86::SHL64m1 },
179 { X86::SHL64rCL, X86::SHL64mCL },
180 { X86::SHL64ri, X86::SHL64mi },
181 { X86::SHL8r1, X86::SHL8m1 },
182 { X86::SHL8rCL, X86::SHL8mCL },
183 { X86::SHL8ri, X86::SHL8mi },
184 { X86::SHLD16rrCL, X86::SHLD16mrCL },
185 { X86::SHLD16rri8, X86::SHLD16mri8 },
186 { X86::SHLD32rrCL, X86::SHLD32mrCL },
187 { X86::SHLD32rri8, X86::SHLD32mri8 },
188 { X86::SHLD64rrCL, X86::SHLD64mrCL },
189 { X86::SHLD64rri8, X86::SHLD64mri8 },
190 { X86::SHR16r1, X86::SHR16m1 },
191 { X86::SHR16rCL, X86::SHR16mCL },
192 { X86::SHR16ri, X86::SHR16mi },
193 { X86::SHR32r1, X86::SHR32m1 },
194 { X86::SHR32rCL, X86::SHR32mCL },
195 { X86::SHR32ri, X86::SHR32mi },
196 { X86::SHR64r1, X86::SHR64m1 },
197 { X86::SHR64rCL, X86::SHR64mCL },
198 { X86::SHR64ri, X86::SHR64mi },
199 { X86::SHR8r1, X86::SHR8m1 },
200 { X86::SHR8rCL, X86::SHR8mCL },
201 { X86::SHR8ri, X86::SHR8mi },
202 { X86::SHRD16rrCL, X86::SHRD16mrCL },
203 { X86::SHRD16rri8, X86::SHRD16mri8 },
204 { X86::SHRD32rrCL, X86::SHRD32mrCL },
205 { X86::SHRD32rri8, X86::SHRD32mri8 },
206 { X86::SHRD64rrCL, X86::SHRD64mrCL },
207 { X86::SHRD64rri8, X86::SHRD64mri8 },
208 { X86::SUB16ri, X86::SUB16mi },
209 { X86::SUB16ri8, X86::SUB16mi8 },
210 { X86::SUB16rr, X86::SUB16mr },
211 { X86::SUB32ri, X86::SUB32mi },
212 { X86::SUB32ri8, X86::SUB32mi8 },
213 { X86::SUB32rr, X86::SUB32mr },
214 { X86::SUB64ri32, X86::SUB64mi32 },
215 { X86::SUB64ri8, X86::SUB64mi8 },
216 { X86::SUB64rr, X86::SUB64mr },
217 { X86::SUB8ri, X86::SUB8mi },
218 { X86::SUB8rr, X86::SUB8mr },
219 { X86::XOR16ri, X86::XOR16mi },
220 { X86::XOR16ri8, X86::XOR16mi8 },
221 { X86::XOR16rr, X86::XOR16mr },
222 { X86::XOR32ri, X86::XOR32mi },
223 { X86::XOR32ri8, X86::XOR32mi8 },
224 { X86::XOR32rr, X86::XOR32mr },
225 { X86::XOR64ri32, X86::XOR64mi32 },
226 { X86::XOR64ri8, X86::XOR64mi8 },
227 { X86::XOR64rr, X86::XOR64mr },
228 { X86::XOR8ri, X86::XOR8mi },
229 { X86::XOR8rr, X86::XOR8mr }
230 };
231
232 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
233 unsigned RegOp = OpTbl2Addr[i][0];
234 unsigned MemOp = OpTbl2Addr[i][1];
235 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
236 assert(false && "Duplicated entries?");
237 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
238 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
239 std::make_pair(RegOp, AuxInfo))))
240 AmbEntries.push_back(MemOp);
241 }
242
243 // If the third value is 1, then it's folding either a load or a store.
244 static const unsigned OpTbl0[][3] = {
245 { X86::CALL32r, X86::CALL32m, 1 },
246 { X86::CALL64r, X86::CALL64m, 1 },
247 { X86::CMP16ri, X86::CMP16mi, 1 },
248 { X86::CMP16ri8, X86::CMP16mi8, 1 },
249 { X86::CMP32ri, X86::CMP32mi, 1 },
250 { X86::CMP32ri8, X86::CMP32mi8, 1 },
251 { X86::CMP64ri32, X86::CMP64mi32, 1 },
252 { X86::CMP64ri8, X86::CMP64mi8, 1 },
253 { X86::CMP8ri, X86::CMP8mi, 1 },
254 { X86::DIV16r, X86::DIV16m, 1 },
255 { X86::DIV32r, X86::DIV32m, 1 },
256 { X86::DIV64r, X86::DIV64m, 1 },
257 { X86::DIV8r, X86::DIV8m, 1 },
258 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
259 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
260 { X86::IDIV16r, X86::IDIV16m, 1 },
261 { X86::IDIV32r, X86::IDIV32m, 1 },
262 { X86::IDIV64r, X86::IDIV64m, 1 },
263 { X86::IDIV8r, X86::IDIV8m, 1 },
264 { X86::IMUL16r, X86::IMUL16m, 1 },
265 { X86::IMUL32r, X86::IMUL32m, 1 },
266 { X86::IMUL64r, X86::IMUL64m, 1 },
267 { X86::IMUL8r, X86::IMUL8m, 1 },
268 { X86::JMP32r, X86::JMP32m, 1 },
269 { X86::JMP64r, X86::JMP64m, 1 },
270 { X86::MOV16ri, X86::MOV16mi, 0 },
271 { X86::MOV16rr, X86::MOV16mr, 0 },
272 { X86::MOV16to16_, X86::MOV16_mr, 0 },
273 { X86::MOV32ri, X86::MOV32mi, 0 },
274 { X86::MOV32rr, X86::MOV32mr, 0 },
275 { X86::MOV32to32_, X86::MOV32_mr, 0 },
276 { X86::MOV64ri32, X86::MOV64mi32, 0 },
277 { X86::MOV64rr, X86::MOV64mr, 0 },
278 { X86::MOV8ri, X86::MOV8mi, 0 },
279 { X86::MOV8rr, X86::MOV8mr, 0 },
280 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
281 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
282 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
283 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
284 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
285 { X86::MOVSDrr, X86::MOVSDmr, 0 },
286 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
287 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
288 { X86::MOVSSrr, X86::MOVSSmr, 0 },
289 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
290 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
291 { X86::MUL16r, X86::MUL16m, 1 },
292 { X86::MUL32r, X86::MUL32m, 1 },
293 { X86::MUL64r, X86::MUL64m, 1 },
294 { X86::MUL8r, X86::MUL8m, 1 },
295 { X86::SETAEr, X86::SETAEm, 0 },
296 { X86::SETAr, X86::SETAm, 0 },
297 { X86::SETBEr, X86::SETBEm, 0 },
298 { X86::SETBr, X86::SETBm, 0 },
299 { X86::SETEr, X86::SETEm, 0 },
300 { X86::SETGEr, X86::SETGEm, 0 },
301 { X86::SETGr, X86::SETGm, 0 },
302 { X86::SETLEr, X86::SETLEm, 0 },
303 { X86::SETLr, X86::SETLm, 0 },
304 { X86::SETNEr, X86::SETNEm, 0 },
305 { X86::SETNPr, X86::SETNPm, 0 },
306 { X86::SETNSr, X86::SETNSm, 0 },
307 { X86::SETPr, X86::SETPm, 0 },
308 { X86::SETSr, X86::SETSm, 0 },
309 { X86::TAILJMPr, X86::TAILJMPm, 1 },
310 { X86::TEST16ri, X86::TEST16mi, 1 },
311 { X86::TEST32ri, X86::TEST32mi, 1 },
312 { X86::TEST64ri32, X86::TEST64mi32, 1 },
313 { X86::TEST8ri, X86::TEST8mi, 1 },
314 { X86::XCHG16rr, X86::XCHG16mr, 0 },
315 { X86::XCHG32rr, X86::XCHG32mr, 0 },
316 { X86::XCHG64rr, X86::XCHG64mr, 0 },
317 { X86::XCHG8rr, X86::XCHG8mr, 0 }
318 };
319
320 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
321 unsigned RegOp = OpTbl0[i][0];
322 unsigned MemOp = OpTbl0[i][1];
323 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
324 assert(false && "Duplicated entries?");
325 unsigned FoldedLoad = OpTbl0[i][2];
326 // Index 0, folded load or store.
327 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
328 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
329 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
330 std::make_pair(RegOp, AuxInfo))))
331 AmbEntries.push_back(MemOp);
332 }
333
334 static const unsigned OpTbl1[][2] = {
335 { X86::CMP16rr, X86::CMP16rm },
336 { X86::CMP32rr, X86::CMP32rm },
337 { X86::CMP64rr, X86::CMP64rm },
338 { X86::CMP8rr, X86::CMP8rm },
339 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
340 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
341 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
342 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
343 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
344 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
345 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
346 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
347 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
348 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
349 { X86::FsMOVAPDrr, X86::MOVSDrm },
350 { X86::FsMOVAPSrr, X86::MOVSSrm },
351 { X86::IMUL16rri, X86::IMUL16rmi },
352 { X86::IMUL16rri8, X86::IMUL16rmi8 },
353 { X86::IMUL32rri, X86::IMUL32rmi },
354 { X86::IMUL32rri8, X86::IMUL32rmi8 },
355 { X86::IMUL64rri32, X86::IMUL64rmi32 },
356 { X86::IMUL64rri8, X86::IMUL64rmi8 },
357 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
358 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
359 { X86::Int_COMISDrr, X86::Int_COMISDrm },
360 { X86::Int_COMISSrr, X86::Int_COMISSrm },
361 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
362 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
363 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
364 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
365 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
366 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
367 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
368 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
369 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
370 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
371 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
372 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
373 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
374 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
375 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
376 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
377 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
378 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
379 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
380 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
381 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
382 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
383 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
384 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
385 { X86::MOV16rr, X86::MOV16rm },
386 { X86::MOV16to16_, X86::MOV16_rm },
387 { X86::MOV32rr, X86::MOV32rm },
388 { X86::MOV32to32_, X86::MOV32_rm },
389 { X86::MOV64rr, X86::MOV64rm },
390 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
391 { X86::MOV64toSDrr, X86::MOV64toSDrm },
392 { X86::MOV8rr, X86::MOV8rm },
393 { X86::MOVAPDrr, X86::MOVAPDrm },
394 { X86::MOVAPSrr, X86::MOVAPSrm },
395 { X86::MOVDDUPrr, X86::MOVDDUPrm },
396 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
397 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
398 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
399 { X86::MOVSDrr, X86::MOVSDrm },
400 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
401 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
402 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
403 { X86::MOVSSrr, X86::MOVSSrm },
404 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
405 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
406 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
407 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
408 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
409 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
410 { X86::MOVUPDrr, X86::MOVUPDrm },
411 { X86::MOVUPSrr, X86::MOVUPSrm },
412 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
413 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
414 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
415 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
416 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
417 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
418 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
419 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
420 { X86::PSHUFDri, X86::PSHUFDmi },
421 { X86::PSHUFHWri, X86::PSHUFHWmi },
422 { X86::PSHUFLWri, X86::PSHUFLWmi },
423 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
424 { X86::RCPPSr, X86::RCPPSm },
425 { X86::RCPPSr_Int, X86::RCPPSm_Int },
426 { X86::RSQRTPSr, X86::RSQRTPSm },
427 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
428 { X86::RSQRTSSr, X86::RSQRTSSm },
429 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
430 { X86::SQRTPDr, X86::SQRTPDm },
431 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
432 { X86::SQRTPSr, X86::SQRTPSm },
433 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
434 { X86::SQRTSDr, X86::SQRTSDm },
435 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
436 { X86::SQRTSSr, X86::SQRTSSm },
437 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
438 { X86::TEST16rr, X86::TEST16rm },
439 { X86::TEST32rr, X86::TEST32rm },
440 { X86::TEST64rr, X86::TEST64rm },
441 { X86::TEST8rr, X86::TEST8rm },
442 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
443 { X86::UCOMISDrr, X86::UCOMISDrm },
444 { X86::UCOMISSrr, X86::UCOMISSrm },
445 { X86::XCHG16rr, X86::XCHG16rm },
446 { X86::XCHG32rr, X86::XCHG32rm },
447 { X86::XCHG64rr, X86::XCHG64rm },
448 { X86::XCHG8rr, X86::XCHG8rm }
449 };
450
451 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
452 unsigned RegOp = OpTbl1[i][0];
453 unsigned MemOp = OpTbl1[i][1];
454 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
455 assert(false && "Duplicated entries?");
456 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
457 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
458 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
459 std::make_pair(RegOp, AuxInfo))))
460 AmbEntries.push_back(MemOp);
461 }
462
463 static const unsigned OpTbl2[][2] = {
464 { X86::ADC32rr, X86::ADC32rm },
465 { X86::ADC64rr, X86::ADC64rm },
466 { X86::ADD16rr, X86::ADD16rm },
467 { X86::ADD32rr, X86::ADD32rm },
468 { X86::ADD64rr, X86::ADD64rm },
469 { X86::ADD8rr, X86::ADD8rm },
470 { X86::ADDPDrr, X86::ADDPDrm },
471 { X86::ADDPSrr, X86::ADDPSrm },
472 { X86::ADDSDrr, X86::ADDSDrm },
473 { X86::ADDSSrr, X86::ADDSSrm },
474 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
475 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
476 { X86::AND16rr, X86::AND16rm },
477 { X86::AND32rr, X86::AND32rm },
478 { X86::AND64rr, X86::AND64rm },
479 { X86::AND8rr, X86::AND8rm },
480 { X86::ANDNPDrr, X86::ANDNPDrm },
481 { X86::ANDNPSrr, X86::ANDNPSrm },
482 { X86::ANDPDrr, X86::ANDPDrm },
483 { X86::ANDPSrr, X86::ANDPSrm },
484 { X86::CMOVA16rr, X86::CMOVA16rm },
485 { X86::CMOVA32rr, X86::CMOVA32rm },
486 { X86::CMOVA64rr, X86::CMOVA64rm },
487 { X86::CMOVAE16rr, X86::CMOVAE16rm },
488 { X86::CMOVAE32rr, X86::CMOVAE32rm },
489 { X86::CMOVAE64rr, X86::CMOVAE64rm },
490 { X86::CMOVB16rr, X86::CMOVB16rm },
491 { X86::CMOVB32rr, X86::CMOVB32rm },
492 { X86::CMOVB64rr, X86::CMOVB64rm },
493 { X86::CMOVBE16rr, X86::CMOVBE16rm },
494 { X86::CMOVBE32rr, X86::CMOVBE32rm },
495 { X86::CMOVBE64rr, X86::CMOVBE64rm },
496 { X86::CMOVE16rr, X86::CMOVE16rm },
497 { X86::CMOVE32rr, X86::CMOVE32rm },
498 { X86::CMOVE64rr, X86::CMOVE64rm },
499 { X86::CMOVG16rr, X86::CMOVG16rm },
500 { X86::CMOVG32rr, X86::CMOVG32rm },
501 { X86::CMOVG64rr, X86::CMOVG64rm },
502 { X86::CMOVGE16rr, X86::CMOVGE16rm },
503 { X86::CMOVGE32rr, X86::CMOVGE32rm },
504 { X86::CMOVGE64rr, X86::CMOVGE64rm },
505 { X86::CMOVL16rr, X86::CMOVL16rm },
506 { X86::CMOVL32rr, X86::CMOVL32rm },
507 { X86::CMOVL64rr, X86::CMOVL64rm },
508 { X86::CMOVLE16rr, X86::CMOVLE16rm },
509 { X86::CMOVLE32rr, X86::CMOVLE32rm },
510 { X86::CMOVLE64rr, X86::CMOVLE64rm },
511 { X86::CMOVNE16rr, X86::CMOVNE16rm },
512 { X86::CMOVNE32rr, X86::CMOVNE32rm },
513 { X86::CMOVNE64rr, X86::CMOVNE64rm },
514 { X86::CMOVNP16rr, X86::CMOVNP16rm },
515 { X86::CMOVNP32rr, X86::CMOVNP32rm },
516 { X86::CMOVNP64rr, X86::CMOVNP64rm },
517 { X86::CMOVNS16rr, X86::CMOVNS16rm },
518 { X86::CMOVNS32rr, X86::CMOVNS32rm },
519 { X86::CMOVNS64rr, X86::CMOVNS64rm },
520 { X86::CMOVP16rr, X86::CMOVP16rm },
521 { X86::CMOVP32rr, X86::CMOVP32rm },
522 { X86::CMOVP64rr, X86::CMOVP64rm },
523 { X86::CMOVS16rr, X86::CMOVS16rm },
524 { X86::CMOVS32rr, X86::CMOVS32rm },
525 { X86::CMOVS64rr, X86::CMOVS64rm },
526 { X86::CMPPDrri, X86::CMPPDrmi },
527 { X86::CMPPSrri, X86::CMPPSrmi },
528 { X86::CMPSDrr, X86::CMPSDrm },
529 { X86::CMPSSrr, X86::CMPSSrm },
530 { X86::DIVPDrr, X86::DIVPDrm },
531 { X86::DIVPSrr, X86::DIVPSrm },
532 { X86::DIVSDrr, X86::DIVSDrm },
533 { X86::DIVSSrr, X86::DIVSSrm },
534 { X86::HADDPDrr, X86::HADDPDrm },
535 { X86::HADDPSrr, X86::HADDPSrm },
536 { X86::HSUBPDrr, X86::HSUBPDrm },
537 { X86::HSUBPSrr, X86::HSUBPSrm },
538 { X86::IMUL16rr, X86::IMUL16rm },
539 { X86::IMUL32rr, X86::IMUL32rm },
540 { X86::IMUL64rr, X86::IMUL64rm },
541 { X86::MAXPDrr, X86::MAXPDrm },
542 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
543 { X86::MAXPSrr, X86::MAXPSrm },
544 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
545 { X86::MAXSDrr, X86::MAXSDrm },
546 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
547 { X86::MAXSSrr, X86::MAXSSrm },
548 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
549 { X86::MINPDrr, X86::MINPDrm },
550 { X86::MINPDrr_Int, X86::MINPDrm_Int },
551 { X86::MINPSrr, X86::MINPSrm },
552 { X86::MINPSrr_Int, X86::MINPSrm_Int },
553 { X86::MINSDrr, X86::MINSDrm },
554 { X86::MINSDrr_Int, X86::MINSDrm_Int },
555 { X86::MINSSrr, X86::MINSSrm },
556 { X86::MINSSrr_Int, X86::MINSSrm_Int },
557 { X86::MULPDrr, X86::MULPDrm },
558 { X86::MULPSrr, X86::MULPSrm },
559 { X86::MULSDrr, X86::MULSDrm },
560 { X86::MULSSrr, X86::MULSSrm },
561 { X86::OR16rr, X86::OR16rm },
562 { X86::OR32rr, X86::OR32rm },
563 { X86::OR64rr, X86::OR64rm },
564 { X86::OR8rr, X86::OR8rm },
565 { X86::ORPDrr, X86::ORPDrm },
566 { X86::ORPSrr, X86::ORPSrm },
567 { X86::PACKSSDWrr, X86::PACKSSDWrm },
568 { X86::PACKSSWBrr, X86::PACKSSWBrm },
569 { X86::PACKUSWBrr, X86::PACKUSWBrm },
570 { X86::PADDBrr, X86::PADDBrm },
571 { X86::PADDDrr, X86::PADDDrm },
572 { X86::PADDQrr, X86::PADDQrm },
573 { X86::PADDSBrr, X86::PADDSBrm },
574 { X86::PADDSWrr, X86::PADDSWrm },
575 { X86::PADDWrr, X86::PADDWrm },
576 { X86::PANDNrr, X86::PANDNrm },
577 { X86::PANDrr, X86::PANDrm },
578 { X86::PAVGBrr, X86::PAVGBrm },
579 { X86::PAVGWrr, X86::PAVGWrm },
580 { X86::PCMPEQBrr, X86::PCMPEQBrm },
581 { X86::PCMPEQDrr, X86::PCMPEQDrm },
582 { X86::PCMPEQWrr, X86::PCMPEQWrm },
583 { X86::PCMPGTBrr, X86::PCMPGTBrm },
584 { X86::PCMPGTDrr, X86::PCMPGTDrm },
585 { X86::PCMPGTWrr, X86::PCMPGTWrm },
586 { X86::PINSRWrri, X86::PINSRWrmi },
587 { X86::PMADDWDrr, X86::PMADDWDrm },
588 { X86::PMAXSWrr, X86::PMAXSWrm },
589 { X86::PMAXUBrr, X86::PMAXUBrm },
590 { X86::PMINSWrr, X86::PMINSWrm },
591 { X86::PMINUBrr, X86::PMINUBrm },
592 { X86::PMULHUWrr, X86::PMULHUWrm },
593 { X86::PMULHWrr, X86::PMULHWrm },
594 { X86::PMULLWrr, X86::PMULLWrm },
595 { X86::PMULUDQrr, X86::PMULUDQrm },
596 { X86::PORrr, X86::PORrm },
597 { X86::PSADBWrr, X86::PSADBWrm },
598 { X86::PSLLDrr, X86::PSLLDrm },
599 { X86::PSLLQrr, X86::PSLLQrm },
600 { X86::PSLLWrr, X86::PSLLWrm },
601 { X86::PSRADrr, X86::PSRADrm },
602 { X86::PSRAWrr, X86::PSRAWrm },
603 { X86::PSRLDrr, X86::PSRLDrm },
604 { X86::PSRLQrr, X86::PSRLQrm },
605 { X86::PSRLWrr, X86::PSRLWrm },
606 { X86::PSUBBrr, X86::PSUBBrm },
607 { X86::PSUBDrr, X86::PSUBDrm },
608 { X86::PSUBSBrr, X86::PSUBSBrm },
609 { X86::PSUBSWrr, X86::PSUBSWrm },
610 { X86::PSUBWrr, X86::PSUBWrm },
611 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
612 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
613 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
614 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
615 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
616 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
617 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
618 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
619 { X86::PXORrr, X86::PXORrm },
620 { X86::SBB32rr, X86::SBB32rm },
621 { X86::SBB64rr, X86::SBB64rm },
622 { X86::SHUFPDrri, X86::SHUFPDrmi },
623 { X86::SHUFPSrri, X86::SHUFPSrmi },
624 { X86::SUB16rr, X86::SUB16rm },
625 { X86::SUB32rr, X86::SUB32rm },
626 { X86::SUB64rr, X86::SUB64rm },
627 { X86::SUB8rr, X86::SUB8rm },
628 { X86::SUBPDrr, X86::SUBPDrm },
629 { X86::SUBPSrr, X86::SUBPSrm },
630 { X86::SUBSDrr, X86::SUBSDrm },
631 { X86::SUBSSrr, X86::SUBSSrm },
632 // FIXME: TEST*rr -> swapped operand of TEST*mr.
633 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
634 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
635 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
636 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
637 { X86::XOR16rr, X86::XOR16rm },
638 { X86::XOR32rr, X86::XOR32rm },
639 { X86::XOR64rr, X86::XOR64rm },
640 { X86::XOR8rr, X86::XOR8rm },
641 { X86::XORPDrr, X86::XORPDrm },
642 { X86::XORPSrr, X86::XORPSrm }
643 };
644
645 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
646 unsigned RegOp = OpTbl2[i][0];
647 unsigned MemOp = OpTbl2[i][1];
648 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
649 assert(false && "Duplicated entries?");
650 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
651 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
652 std::make_pair(RegOp, AuxInfo))))
653 AmbEntries.push_back(MemOp);
654 }
655
656 // Remove ambiguous entries.
657 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
65856 }
65957
66058 // getDwarfRegNum - This function maps LLVM register identifiers to the
838236 break;
839237 }
840238 }
841 }
842
843 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
844 SmallVector &MOs,
845 MachineInstr *MI, const TargetInstrInfo &TII) {
846 // Create the base instruction with the memory operand as the first part.
847 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
848 MachineInstrBuilder MIB(NewMI);
849 unsigned NumAddrOps = MOs.size();
850 for (unsigned i = 0; i != NumAddrOps; ++i)
851 MIB = X86InstrAddOperand(MIB, MOs[i]);
852 if (NumAddrOps < 4) // FrameIndex only
853 MIB.addImm(1).addReg(0).addImm(0);
854
855 // Loop over the rest of the ri operands, converting them over.
856 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
857 for (unsigned i = 0; i != NumOps; ++i) {
858 MachineOperand &MO = MI->getOperand(i+2);
859 MIB = X86InstrAddOperand(MIB, MO);
860 }
861 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
862 MachineOperand &MO = MI->getOperand(i);
863 MIB = X86InstrAddOperand(MIB, MO);
864 }
865 return MIB;
866 }
867
868 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
869 SmallVector &MOs,
870 MachineInstr *MI, const TargetInstrInfo &TII) {
871 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
872 MachineInstrBuilder MIB(NewMI);
873
874 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
875 MachineOperand &MO = MI->getOperand(i);
876 if (i == OpNo) {
877 assert(MO.isRegister() && "Expected to fold into reg operand!");
878 unsigned NumAddrOps = MOs.size();
879 for (unsigned i = 0; i != NumAddrOps; ++i)
880 MIB = X86InstrAddOperand(MIB, MOs[i]);
881 if (NumAddrOps < 4) // FrameIndex only
882 MIB.addImm(1).addReg(0).addImm(0);
883 } else {
884 MIB = X86InstrAddOperand(MIB, MO);
885 }
886 }
887 return MIB;
888 }
889
890 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
891 SmallVector &MOs,
892 MachineInstr *MI) {
893 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
894
895 unsigned NumAddrOps = MOs.size();
896 for (unsigned i = 0; i != NumAddrOps; ++i)
897 MIB = X86InstrAddOperand(MIB, MOs[i]);
898 if (NumAddrOps < 4) // FrameIndex only
899 MIB.addImm(1).addReg(0).addImm(0);
900 return MIB.addImm(0);
901 }
902
903 MachineInstr*
904 X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
905 SmallVector &MOs) const {
906 const DenseMap *OpcodeTablePtr = NULL;
907 bool isTwoAddrFold = false;
908 unsigned NumOps = TII.getNumOperands(MI->getOpcode());
909 bool isTwoAddr = NumOps > 1 &&
910 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
911
912 MachineInstr *NewMI = NULL;
913 // Folding a memory location into the two-address part of a two-address
914 // instruction is different than folding it other places. It requires
915 // replacing the *two* registers with the memory location.
916 if (isTwoAddr && NumOps >= 2 && i < 2 &&
917 MI->getOperand(0).isRegister() &&
918 MI->getOperand(1).isRegister() &&
919 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
920 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
921 isTwoAddrFold = true;
922 } else if (i == 0) { // If operand 0
923 if (MI->getOpcode() == X86::MOV16r0)
924 NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI);
925 else if (MI->getOpcode() == X86::MOV32r0)
926 NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI);
927 else if (MI->getOpcode() == X86::MOV64r0)
928 NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI);
929 else if (MI->getOpcode() == X86::MOV8r0)
930 NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI);
931 if (NewMI) {
932 NewMI->copyKillDeadInfo(MI);
933 return NewMI;
934 }
935
936 OpcodeTablePtr = &RegOp2MemOpTable0;
937 } else if (i == 1) {
938 OpcodeTablePtr = &RegOp2MemOpTable1;
939 } else if (i == 2) {
940 OpcodeTablePtr = &RegOp2MemOpTable2;
941 }
942
943 // If table selected...
944 if (OpcodeTablePtr) {
945 // Find the Opcode to fuse
946 DenseMap::iterator I =
947 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
948 if (I != OpcodeTablePtr->end()) {
949 if (isTwoAddrFold)
950 NewMI = FuseTwoAddrInst(I->second, MOs, MI, TII);
951 else
952 NewMI = FuseInst(I->second, i, MOs, MI, TII);
953 NewMI->copyKillDeadInfo(MI);
954 return NewMI;
955 }
956 }
957
958 // No fusion
959 if (PrintFailedFusing)
960 cerr << "We failed to fuse ("
961 << ((i == 1) ? "r" : "s") << "): " << *MI;
962 return NULL;
963 }
964
965
966 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
967 SmallVectorImpl &Ops,
968 int FrameIndex) const {
969 // Check switch flag
970 if (NoFusing) return NULL;
971
972 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
973 unsigned NewOpc = 0;
974 switch (MI->getOpcode()) {
975 default: return NULL;
976 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
977 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
978 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
979 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
980 }
981 // Change to CMPXXri r, 0 first.
982 MI->setInstrDescriptor(TII.get(NewOpc));
983 MI->getOperand(1).ChangeToImmediate(0);
984 } else if (Ops.size() != 1)
985 return NULL;
986
987 SmallVector MOs;
988 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
989 return foldMemoryOperand(MI, Ops[0], MOs);
990 }
991
992 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
993 SmallVectorImpl &Ops,
994 MachineInstr *LoadMI) const {
995 // Check switch flag
996 if (NoFusing) return NULL;
997
998 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
999 unsigned NewOpc = 0;
1000 switch (MI->getOpcode()) {
1001 default: return NULL;
1002 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1003 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1004 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1005 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1006 }
1007 // Change to CMPXXri r, 0 first.
1008 MI->setInstrDescriptor(TII.get(NewOpc));
1009 MI->getOperand(1).ChangeToImmediate(0);
1010 } else if (Ops.size() != 1)
1011 return NULL;
1012
1013 SmallVector MOs;
1014 unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode());
1015 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1016 MOs.push_back(LoadMI->getOperand(i));
1017 return foldMemoryOperand(MI, Ops[0], MOs);
1018 }
1019
1020
1021 bool X86RegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
1022 SmallVectorImpl &Ops) const {
1023 // Check switch flag
1024 if (NoFusing) return 0;
1025
1026 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1027 switch (MI->getOpcode()) {
1028 default: return false;
1029 case X86::TEST8rr:
1030 case X86::TEST16rr:
1031 case X86::TEST32rr:
1032 case X86::TEST64rr:
1033 return true;
1034 }
1035 }
1036
1037 if (Ops.size() != 1)
1038 return false;
1039
1040 unsigned OpNum = Ops[0];
1041 unsigned Opc = MI->getOpcode();
1042 unsigned NumOps = TII.getNumOperands(Opc);
1043 bool isTwoAddr = NumOps > 1 &&
1044 TII.getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
1045
1046 // Folding a memory location into the two-address part of a two-address
1047 // instruction is different than folding it other places. It requires
1048 // replacing the *two* registers with the memory location.
1049 const DenseMap *OpcodeTablePtr = NULL;
1050 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1051 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1052 } else if (OpNum == 0) { // If operand 0
1053 switch (Opc) {
1054 case X86::MOV16r0:
1055 case X86::MOV32r0:
1056 case X86::MOV64r0:
1057 case X86::MOV8r0:
1058 return true;
1059 default: break;
1060 }
1061 OpcodeTablePtr = &RegOp2MemOpTable0;
1062 } else if (OpNum == 1) {
1063 OpcodeTablePtr = &RegOp2MemOpTable1;
1064 } else if (OpNum == 2) {
1065 OpcodeTablePtr = &RegOp2MemOpTable2;
1066 }
1067
1068 if (OpcodeTablePtr) {
1069 // Find the Opcode to fuse
1070 DenseMap::iterator I =
1071 OpcodeTablePtr->find((unsigned*)Opc);
1072 if (I != OpcodeTablePtr->end())
1073 return true;
1074 }
1075 return false;
1076 }
1077
1078 bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1079 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1080 SmallVectorImpl &NewMIs) const {
1081 DenseMap >::iterator I =
1082 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
1083 if (I == MemOp2RegOpTable.end())
1084 return false;
1085 unsigned Opc = I->second.first;
1086 unsigned Index = I->second.second & 0xf;
1087 bool FoldedLoad = I->second.second & (1 << 4);
1088 bool FoldedStore = I->second.second & (1 << 5);
1089 if (UnfoldLoad && !FoldedLoad)
1090 return false;
1091 UnfoldLoad &= FoldedLoad;
1092 if (UnfoldStore && !FoldedStore)
1093 return false;
1094 UnfoldStore &= FoldedStore;
1095
1096 const TargetInstrDescriptor &TID = TII.get(Opc);
1097 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1098 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1099 ? TII.getPointerRegClass() : getRegClass(TOI.RegClass);
1100 SmallVector AddrOps;
1101 SmallVector BeforeOps;
1102 SmallVector AfterOps;
1103 SmallVector ImpOps;
1104 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1105 MachineOperand &Op = MI->getOperand(i);
1106 if (i >= Index && i < Index+4)
1107 AddrOps.push_back(Op);
1108 else if (Op.isRegister() && Op.isImplicit())
1109 ImpOps.push_back(Op);
1110 else if (i < Index)
1111 BeforeOps.push_back(Op);
1112 else if (i > Index)
1113 AfterOps.push_back(Op);
1114 }
1115
1116 // Emit the load instruction.
1117 if (UnfoldLoad) {
1118 TII.loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
1119 if (UnfoldStore) {
1120 // Address operands cannot be marked isKill.
1121 for (unsigned i = 1; i != 5; ++i) {
1122 MachineOperand &MO = NewMIs[0]->getOperand(i);
1123 if (MO.isRegister())
1124 MO.setIsKill(false);
1125 }
1126 }
1127 }
1128
1129 // Emit the data processing instruction.
1130 MachineInstr *DataMI = new MachineInstr(TID, true);
1131 MachineInstrBuilder MIB(DataMI);
1132