llvm.org GIT mirror llvm / 43c2ba7
[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print Work towards the unification of MIR and debug output by refactoring the interfaces. Also add support for printing with a null TargetIntrinsicInfo and no MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321111 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 2 years ago
4 changed file(s) with 45 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
711711 .. code-block:: text
712712
713713 .cfi_offset w30, -16
714
715 IntrinsicID Operands
716 ^^^^^^^^^^^^^^^^^^^^
717
718 An Intrinsic ID operand contains a generic intrinsic ID or a target-specific ID.
719
720 The syntax for the ``returnaddress`` intrinsic is:
721
722 .. code-block:: text
723
724 %x0 = COPY intrinsic(@llvm.returnaddress)
714725
715726 .. TODO: Describe the parsers default behaviour when optional YAML attributes
716727 are missing.
783783 case MachineOperand::MO_RegisterLiveOut:
784784 case MachineOperand::MO_Metadata:
785785 case MachineOperand::MO_MCSymbol:
786 case MachineOperand::MO_CFIIndex: {
786 case MachineOperand::MO_CFIIndex:
787 case MachineOperand::MO_IntrinsicID: {
787788 unsigned TiedOperandIdx = 0;
788789 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
789790 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
810811 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
811812 else
812813 printCustomRegMask(Op.getRegMask(), OS, TRI);
813 break;
814 }
815 case MachineOperand::MO_IntrinsicID: {
816 Intrinsic::ID ID = Op.getIntrinsicID();
817 if (ID < Intrinsic::num_intrinsics)
818 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
819 else {
820 const MachineFunction &MF = *Op.getParent()->getMF();
821 const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
822 OS << "intrinsic(@" << TII->getName(ID) << ')';
823 }
824814 break;
825815 }
826816 case MachineOperand::MO_Predicate: {
797797 case MachineOperand::MO_IntrinsicID: {
798798 Intrinsic::ID ID = getIntrinsicID();
799799 if (ID < Intrinsic::num_intrinsics)
800 OS << "';
800 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
801801 else if (IntrinsicInfo)
802 OS << "getName(ID) << '>';
802 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
803803 else
804 OS << "';
804 OS << "intrinsic(" << ID << ')';
805805 break;
806806 }
807807 case MachineOperand::MO_Predicate: {
352352 ASSERT_TRUE(OS.str() == "");
353353 }
354354
355 TEST(MachineOperandTest, PrintIntrinsicID) {
356 // Create a MachineOperand with a generic intrinsic ID.
357 MachineOperand MO = MachineOperand::CreateIntrinsicID(Intrinsic::bswap);
358
359 // Checking some preconditions on the newly created
360 // MachineOperand.
361 ASSERT_TRUE(MO.isIntrinsicID());
362 ASSERT_TRUE(MO.getIntrinsicID() == Intrinsic::bswap);
363
364 std::string str;
365 {
366 // Print a MachineOperand containing a generic intrinsic ID.
367 raw_string_ostream OS(str);
368 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
369 ASSERT_TRUE(OS.str() == "intrinsic(@llvm.bswap)");
370 }
371
372 str.clear();
373 // Set a target-specific intrinsic.
374 MO = MachineOperand::CreateIntrinsicID((Intrinsic::ID)-1);
375 {
376 // Print a MachineOperand containing a target-specific intrinsic ID but not
377 // IntrinsicInfo.
378 raw_string_ostream OS(str);
379 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
380 ASSERT_TRUE(OS.str() == "intrinsic(4294967295)");
381 }
382 }
383
355384 } // end namespace