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[X86] Test bitfield loadstore tests on i686 as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307182 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 years ago
1 changed file(s) with 162 addition(s) and 89 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
1 ; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s --check-prefix=X86
2 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X64
23
34 define void @i24_or(i24* %a) {
4 ; CHECK-LABEL: i24_or:
5 ; CHECK: # BB#0:
6 ; CHECK-NEXT: movzwl (%rdi), %eax
7 ; CHECK-NEXT: movzbl 2(%rdi), %ecx
8 ; CHECK-NEXT: movb %cl, 2(%rdi)
9 ; CHECK-NEXT: shll $16, %ecx
10 ; CHECK-NEXT: orl %eax, %ecx
11 ; CHECK-NEXT: orl $384, %ecx # imm = 0x180
12 ; CHECK-NEXT: movw %cx, (%rdi)
13 ; CHECK-NEXT: retq
5 ; X86-LABEL: i24_or:
6 ; X86: # BB#0:
7 ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
8 ; X86-NEXT: movzwl (%ecx), %edx
9 ; X86-NEXT: movzbl 2(%ecx), %eax
10 ; X86-NEXT: movb %al, 2(%ecx)
11 ; X86-NEXT: shll $16, %eax
12 ; X86-NEXT: orl %edx, %eax
13 ; X86-NEXT: orl $384, %eax # imm = 0x180
14 ; X86-NEXT: movw %ax, (%ecx)
15 ; X86-NEXT: retl
16 ;
17 ; X64-LABEL: i24_or:
18 ; X64: # BB#0:
19 ; X64-NEXT: movzwl (%rdi), %eax
20 ; X64-NEXT: movzbl 2(%rdi), %ecx
21 ; X64-NEXT: movb %cl, 2(%rdi)
22 ; X64-NEXT: shll $16, %ecx
23 ; X64-NEXT: orl %eax, %ecx
24 ; X64-NEXT: orl $384, %ecx # imm = 0x180
25 ; X64-NEXT: movw %cx, (%rdi)
26 ; X64-NEXT: retq
1427 %aa = load i24, i24* %a, align 1
1528 %b = or i24 %aa, 384
1629 store i24 %b, i24* %a, align 1
1831 }
1932
2033 define void @i24_and_or(i24* %a) {
21 ; CHECK-LABEL: i24_and_or:
22 ; CHECK: # BB#0:
23 ; CHECK-NEXT: movzwl (%rdi), %eax
24 ; CHECK-NEXT: movzbl 2(%rdi), %ecx
25 ; CHECK-NEXT: movb %cl, 2(%rdi)
26 ; CHECK-NEXT: shll $16, %ecx
27 ; CHECK-NEXT: orl %eax, %ecx
28 ; CHECK-NEXT: orl $384, %ecx # imm = 0x180
29 ; CHECK-NEXT: andl $16777088, %ecx # imm = 0xFFFF80
30 ; CHECK-NEXT: movw %cx, (%rdi)
31 ; CHECK-NEXT: retq
34 ; X86-LABEL: i24_and_or:
35 ; X86: # BB#0:
36 ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
37 ; X86-NEXT: movzwl (%ecx), %edx
38 ; X86-NEXT: movzbl 2(%ecx), %eax
39 ; X86-NEXT: movb %al, 2(%ecx)
40 ; X86-NEXT: shll $16, %eax
41 ; X86-NEXT: orl %edx, %eax
42 ; X86-NEXT: orl $384, %eax # imm = 0x180
43 ; X86-NEXT: andl $16777088, %eax # imm = 0xFFFF80
44 ; X86-NEXT: movw %ax, (%ecx)
45 ; X86-NEXT: retl
46 ;
47 ; X64-LABEL: i24_and_or:
48 ; X64: # BB#0:
49 ; X64-NEXT: movzwl (%rdi), %eax
50 ; X64-NEXT: movzbl 2(%rdi), %ecx
51 ; X64-NEXT: movb %cl, 2(%rdi)
52 ; X64-NEXT: shll $16, %ecx
53 ; X64-NEXT: orl %eax, %ecx
54 ; X64-NEXT: orl $384, %ecx # imm = 0x180
55 ; X64-NEXT: andl $16777088, %ecx # imm = 0xFFFF80
56 ; X64-NEXT: movw %cx, (%rdi)
57 ; X64-NEXT: retq
3258 %b = load i24, i24* %a, align 1
3359 %c = and i24 %b, -128
3460 %d = or i24 %c, 384
3763 }
3864
3965 define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
40 ; CHECK-LABEL: i24_insert_bit:
41 ; CHECK: # BB#0:
42 ; CHECK-NEXT: movzbl %sil, %eax
43 ; CHECK-NEXT: movzwl (%rdi), %ecx
44 ; CHECK-NEXT: movzbl 2(%rdi), %edx
45 ; CHECK-NEXT: movb %dl, 2(%rdi)
46 ; CHECK-NEXT: shll $16, %edx
47 ; CHECK-NEXT: orl %ecx, %edx
48 ; CHECK-NEXT: shll $13, %eax
49 ; CHECK-NEXT: andl $16769023, %edx # imm = 0xFFDFFF
50 ; CHECK-NEXT: orl %eax, %edx
51 ; CHECK-NEXT: movw %dx, (%rdi)
52 ; CHECK-NEXT: retq
66 ; X86-LABEL: i24_insert_bit:
67 ; X86: # BB#0:
68 ; X86-NEXT: pushl %esi
69 ; X86-NEXT: .Lcfi0:
70 ; X86-NEXT: .cfi_def_cfa_offset 8
71 ; X86-NEXT: .Lcfi1:
72 ; X86-NEXT: .cfi_offset %esi, -8
73 ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
74 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
75 ; X86-NEXT: movzwl (%ecx), %esi
76 ; X86-NEXT: movzbl 2(%ecx), %eax
77 ; X86-NEXT: movb %al, 2(%ecx)
78 ; X86-NEXT: shll $16, %eax
79 ; X86-NEXT: orl %esi, %eax
80 ; X86-NEXT: shll $13, %edx
81 ; X86-NEXT: andl $16769023, %eax # imm = 0xFFDFFF
82 ; X86-NEXT: orl %edx, %eax
83 ; X86-NEXT: movw %ax, (%ecx)
84 ; X86-NEXT: popl %esi
85 ; X86-NEXT: retl
86 ;
87 ; X64-LABEL: i24_insert_bit:
88 ; X64: # BB#0:
89 ; X64-NEXT: movzbl %sil, %eax
90 ; X64-NEXT: movzwl (%rdi), %ecx
91 ; X64-NEXT: movzbl 2(%rdi), %edx
92 ; X64-NEXT: movb %dl, 2(%rdi)
93 ; X64-NEXT: shll $16, %edx
94 ; X64-NEXT: orl %ecx, %edx
95 ; X64-NEXT: shll $13, %eax
96 ; X64-NEXT: andl $16769023, %edx # imm = 0xFFDFFF
97 ; X64-NEXT: orl %eax, %edx
98 ; X64-NEXT: movw %dx, (%rdi)
99 ; X64-NEXT: retq
53100 %extbit = zext i1 %bit to i24
54101 %b = load i24, i24* %a, align 1
55102 %extbit.shl = shl nuw nsw i24 %extbit, 13
60107 }
61108
62109 define void @i56_or(i56* %a) {
63 ; CHECK-LABEL: i56_or:
64 ; CHECK: # BB#0:
65 ; CHECK-NEXT: movzwl 4(%rdi), %eax
66 ; CHECK-NEXT: movzbl 6(%rdi), %ecx
67 ; CHECK-NEXT: movl (%rdi), %edx
68 ; CHECK-NEXT: movb %cl, 6(%rdi)
69 ; CHECK-NEXT: # kill: %ECX %ECX %RCX %RCX
70 ; CHECK-NEXT: shll $16, %ecx
71 ; CHECK-NEXT: orl %eax, %ecx
72 ; CHECK-NEXT: shlq $32, %rcx
73 ; CHECK-NEXT: orq %rcx, %rdx
74 ; CHECK-NEXT: orq $384, %rdx # imm = 0x180
75 ; CHECK-NEXT: movl %edx, (%rdi)
76 ; CHECK-NEXT: shrq $32, %rdx
77 ; CHECK-NEXT: movw %dx, 4(%rdi)
78 ; CHECK-NEXT: retq
110 ; X86-LABEL: i56_or:
111 ; X86: # BB#0:
112 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
113 ; X86-NEXT: orl $384, (%eax) # imm = 0x180
114 ; X86-NEXT: retl
115 ;
116 ; X64-LABEL: i56_or:
117 ; X64: # BB#0:
118 ; X64-NEXT: movzwl 4(%rdi), %eax
119 ; X64-NEXT: movzbl 6(%rdi), %ecx
120 ; X64-NEXT: movl (%rdi), %edx
121 ; X64-NEXT: movb %cl, 6(%rdi)
122 ; X64-NEXT: # kill: %ECX %ECX %RCX %RCX
123 ; X64-NEXT: shll $16, %ecx
124 ; X64-NEXT: orl %eax, %ecx
125 ; X64-NEXT: shlq $32, %rcx
126 ; X64-NEXT: orq %rcx, %rdx
127 ; X64-NEXT: orq $384, %rdx # imm = 0x180
128 ; X64-NEXT: movl %edx, (%rdi)
129 ; X64-NEXT: shrq $32, %rdx
130 ; X64-NEXT: movw %dx, 4(%rdi)
131 ; X64-NEXT: retq
79132 %aa = load i56, i56* %a, align 1
80133 %b = or i56 %aa, 384
81134 store i56 %b, i56* %a, align 1
83136 }
84137
85138 define void @i56_and_or(i56* %a) {
86 ; CHECK-LABEL: i56_and_or:
87 ; CHECK: # BB#0:
88 ; CHECK-NEXT: movzwl 4(%rdi), %eax
89 ; CHECK-NEXT: movzbl 6(%rdi), %ecx
90 ; CHECK-NEXT: movl (%rdi), %edx
91 ; CHECK-NEXT: movb %cl, 6(%rdi)
92 ; CHECK-NEXT: # kill: %ECX %ECX %RCX %RCX
93 ; CHECK-NEXT: shll $16, %ecx
94 ; CHECK-NEXT: orl %eax, %ecx
95 ; CHECK-NEXT: shlq $32, %rcx
96 ; CHECK-NEXT: orq %rcx, %rdx
97 ; CHECK-NEXT: orq $384, %rdx # imm = 0x180
98 ; CHECK-NEXT: movabsq $72057594037927808, %rax # imm = 0xFFFFFFFFFFFF80
99 ; CHECK-NEXT: andq %rdx, %rax
100 ; CHECK-NEXT: movl %eax, (%rdi)
101 ; CHECK-NEXT: shrq $32, %rax
102 ; CHECK-NEXT: movw %ax, 4(%rdi)
103 ; CHECK-NEXT: retq
139 ; X86-LABEL: i56_and_or:
140 ; X86: # BB#0:
141 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
142 ; X86-NEXT: movl $384, %ecx # imm = 0x180
143 ; X86-NEXT: orl (%eax), %ecx
144 ; X86-NEXT: andl $-128, %ecx
145 ; X86-NEXT: movl %ecx, (%eax)
146 ; X86-NEXT: retl
147 ;
148 ; X64-LABEL: i56_and_or:
149 ; X64: # BB#0:
150 ; X64-NEXT: movzwl 4(%rdi), %eax
151 ; X64-NEXT: movzbl 6(%rdi), %ecx
152 ; X64-NEXT: movl (%rdi), %edx
153 ; X64-NEXT: movb %cl, 6(%rdi)
154 ; X64-NEXT: # kill: %ECX %ECX %RCX %RCX
155 ; X64-NEXT: shll $16, %ecx
156 ; X64-NEXT: orl %eax, %ecx
157 ; X64-NEXT: shlq $32, %rcx
158 ; X64-NEXT: orq %rcx, %rdx
159 ; X64-NEXT: orq $384, %rdx # imm = 0x180
160 ; X64-NEXT: movabsq $72057594037927808, %rax # imm = 0xFFFFFFFFFFFF80
161 ; X64-NEXT: andq %rdx, %rax
162 ; X64-NEXT: movl %eax, (%rdi)
163 ; X64-NEXT: shrq $32, %rax
164 ; X64-NEXT: movw %ax, 4(%rdi)
165 ; X64-NEXT: retq
104166 %b = load i56, i56* %a, align 1
105167 %c = and i56 %b, -128
106168 %d = or i56 %c, 384
109171 }
110172
111173 define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
112 ; CHECK-LABEL: i56_insert_bit:
113 ; CHECK: # BB#0:
114 ; CHECK-NEXT: movzbl %sil, %eax
115 ; CHECK-NEXT: movzwl 4(%rdi), %ecx
116 ; CHECK-NEXT: movzbl 6(%rdi), %edx
117 ; CHECK-NEXT: movl (%rdi), %esi
118 ; CHECK-NEXT: movb %dl, 6(%rdi)
119 ; CHECK-NEXT: # kill: %EDX %EDX %RDX %RDX
120 ; CHECK-NEXT: shll $16, %edx
121 ; CHECK-NEXT: orl %ecx, %edx
122 ; CHECK-NEXT: shlq $32, %rdx
123 ; CHECK-NEXT: orq %rdx, %rsi
124 ; CHECK-NEXT: shlq $13, %rax
125 ; CHECK-NEXT: movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF
126 ; CHECK-NEXT: andq %rsi, %rcx
127 ; CHECK-NEXT: orq %rax, %rcx
128 ; CHECK-NEXT: movl %ecx, (%rdi)
129 ; CHECK-NEXT: shrq $32, %rcx
130 ; CHECK-NEXT: movw %cx, 4(%rdi)
131 ; CHECK-NEXT: retq
174 ; X86-LABEL: i56_insert_bit:
175 ; X86: # BB#0:
176 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
177 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
178 ; X86-NEXT: shll $13, %ecx
179 ; X86-NEXT: movl $-8193, %edx # imm = 0xDFFF
180 ; X86-NEXT: andl (%eax), %edx
181 ; X86-NEXT: orl %ecx, %edx
182 ; X86-NEXT: movl %edx, (%eax)
183 ; X86-NEXT: retl
184 ;
185 ; X64-LABEL: i56_insert_bit:
186 ; X64: # BB#0:
187 ; X64-NEXT: movzbl %sil, %eax
188 ; X64-NEXT: movzwl 4(%rdi), %ecx
189 ; X64-NEXT: movzbl 6(%rdi), %edx
190 ; X64-NEXT: movl (%rdi), %esi
191 ; X64-NEXT: movb %dl, 6(%rdi)
192 ; X64-NEXT: # kill: %EDX %EDX %RDX %RDX
193 ; X64-NEXT: shll $16, %edx
194 ; X64-NEXT: orl %ecx, %edx
195 ; X64-NEXT: shlq $32, %rdx
196 ; X64-NEXT: orq %rdx, %rsi
197 ; X64-NEXT: shlq $13, %rax
198 ; X64-NEXT: movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF
199 ; X64-NEXT: andq %rsi, %rcx
200 ; X64-NEXT: orq %rax, %rcx
201 ; X64-NEXT: movl %ecx, (%rdi)
202 ; X64-NEXT: shrq $32, %rcx
203 ; X64-NEXT: movw %cx, 4(%rdi)
204 ; X64-NEXT: retq
132205 %extbit = zext i1 %bit to i56
133206 %b = load i56, i56* %a, align 1
134207 %extbit.shl = shl nuw nsw i56 %extbit, 13