llvm.org GIT mirror llvm / 4396f5d
Change MCStreamer EmitInstruction interface to take subtarget info git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200345 91177308-0d34-0410-b5e6-96231b3b80d8 David Woodhouse 6 years ago
31 changed file(s) with 187 addition(s) and 162 deletion(s). Raw diff Collapse all Expand all
4141 class MCAsmInfo;
4242 class MCCFIInstruction;
4343 class MCContext;
44 class MCInst;
4445 class MCInstrInfo;
4546 class MCSection;
4647 class MCStreamer;
148149 /// getDataLayout - Return information about data layout.
149150 const DataLayout &getDataLayout() const;
150151
152 /// getSubtargetInfo - Return information about subtarget.
153 const MCSubtargetInfo &getSubtargetInfo() const;
154
155 void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
156
151157 /// getTargetTriple - Return the target triple string.
152158 StringRef getTargetTriple() const;
153159
8282 virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);
8383 virtual void ChangeSection(const MCSection *Section,
8484 const MCExpr *Subsection);
85 virtual void EmitInstruction(const MCInst &Inst);
85 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo& STI);
8686
8787 /// \brief Emit an instruction to a special fragment, because this instruction
8888 /// can change its size during relaxation.
662662
663663 /// EmitInstruction - Emit the given @p Instruction into the current
664664 /// section.
665 virtual void EmitInstruction(const MCInst &Inst) = 0;
665 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) = 0;
666666
667667 /// \brief Set the bundle alignment mode from now on in the section.
668668 /// The argument is the power of 2 to which the alignment is set. The
4747 #include "llvm/Target/TargetLoweringObjectFile.h"
4848 #include "llvm/Target/TargetOptions.h"
4949 #include "llvm/Target/TargetRegisterInfo.h"
50 #include "llvm/Target/TargetSubtargetInfo.h"
5051 #include "llvm/Transforms/Utils/GlobalStatus.h"
5152 #include "WinCodeViewLineTables.h"
5253 using namespace llvm;
134135 /// getDataLayout - Return information about data layout.
135136 const DataLayout &AsmPrinter::getDataLayout() const {
136137 return *TM.getDataLayout();
138 }
139
140 const MCSubtargetInfo &AsmPrinter::getSubtargetInfo() const {
141 return TM.getSubtarget();
142 }
143
144 void AsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
145 S.EmitInstruction(Inst, getSubtargetInfo());
137146 }
138147
139148 StringRef AsmPrinter::getTargetTriple() const {
788797 TM.getInstrInfo()->getNoopForMachoTarget(Noop);
789798 if (Noop.getOpcode()) {
790799 OutStreamer.AddComment("avoids zero-length function");
791 OutStreamer.EmitInstruction(Noop);
800 OutStreamer.EmitInstruction(Noop, getSubtargetInfo());
792801 } else // Target not mc-ized yet.
793802 OutStreamer.EmitRawText(StringRef("\tnop\n"));
794803 }
624624
625625 RecordStreamer(MCContext &Context) : MCStreamer(Context) {}
626626
627 virtual void EmitInstruction(const MCInst &Inst) {
627 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
628628 // Scan for values.
629629 for (unsigned i = Inst.getNumOperands(); i--; )
630630 if (Inst.getOperand(i).isExpr())
245245 virtual void EmitWin64EHPushFrame(bool Code);
246246 virtual void EmitWin64EHEndProlog();
247247
248 virtual void EmitInstruction(const MCInst &Inst);
248 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI);
249249
250250 virtual void EmitBundleAlignMode(unsigned AlignPow2);
251251 virtual void EmitBundleLock(bool AlignToEnd);
13171317 }
13181318 }
13191319
1320 void MCAsmStreamer::EmitInstruction(const MCInst &Inst) {
1320 void MCAsmStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
13211321 assert(getCurrentSection().first &&
13221322 "Cannot emit contents before setting section!");
13231323
9191 unsigned Column, unsigned Flags,
9292 unsigned Isa, unsigned Discriminator,
9393 StringRef FileName) {}
94 virtual void EmitInstruction(const MCInst &Inst) {}
94 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo&) {}
9595
9696 virtual void EmitBundleAlignMode(unsigned AlignPow2) {}
9797 virtual void EmitBundleLock(bool AlignToEnd) {}
186186 Symbol->setVariableValue(AddValueSymbols(Value));
187187 }
188188
189 void MCObjectStreamer::EmitInstruction(const MCInst &Inst) {
189 void MCObjectStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
190190 // Scan for values.
191191 for (unsigned i = Inst.getNumOperands(); i--; )
192192 if (Inst.getOperand(i).isExpr())
263263
264264 MCInst TmpInst;
265265 LowerAArch64MachineInstrToMCInst(MI, TmpInst, *this);
266 OutStreamer.EmitInstruction(TmpInst);
266 EmitToStreamer(OutStreamer, TmpInst);
267267 }
268268
269269 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
23742374 Inst.setOpcode(AArch64::TLSDESCCALL);
23752375 Inst.addOperand(MCOperand::CreateExpr(Expr));
23762376
2377 getParser().getStreamer().EmitInstruction(Inst);
2377 getParser().getStreamer().EmitInstruction(Inst, STI);
23782378 return false;
23792379 }
23802380
23972397 if (validateInstruction(Inst, Operands))
23982398 return true;
23992399
2400 Out.EmitInstruction(Inst);
2400 Out.EmitInstruction(Inst, STI);
24012401 return false;
24022402 case Match_MissingFeature:
24032403 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
7575 /// This function is the one used to emit instruction data into the ELF
7676 /// streamer. We override it to add the appropriate mapping symbol if
7777 /// necessary.
78 virtual void EmitInstruction(const MCInst& Inst) {
78 virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) {
7979 EmitA64MappingSymbol();
80 MCELFStreamer::EmitInstruction(Inst);
80 MCELFStreamer::EmitInstruction(Inst, STI);
8181 }
8282
8383 /// This is one of the functions used to emit data into an ELF section, so the
938938 OutContext);
939939 // If this isn't a TBB or TBH, the entries are direct branch instructions.
940940 if (OffsetWidth == 4) {
941 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
941 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
942942 .addExpr(MBBSymbolExpr)
943943 .addImm(ARMCC::AL)
944944 .addReg(0));
11411141 case ARM::t2LEApcrel: {
11421142 // FIXME: Need to also handle globals and externals
11431143 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1144 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1144 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
11451145 ARM::t2LEApcrel ? ARM::t2ADR
11461146 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
11471147 : ARM::ADR))
11581158 MCSymbol *JTIPICSymbol =
11591159 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
11601160 MI->getOperand(2).getImm());
1161 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1161 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
11621162 ARM::t2LEApcrelJT ? ARM::t2ADR
11631163 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
11641164 : ARM::ADR))
11721172 // Darwin call instructions are just normal call instructions with different
11731173 // clobber semantics (they clobber R9).
11741174 case ARM::BX_CALL: {
1175 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1175 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
11761176 .addReg(ARM::LR)
11771177 .addReg(ARM::PC)
11781178 // Add predicate operands.
11811181 // Add 's' bit operand (always reg0 for this)
11821182 .addReg(0));
11831183
1184 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1184 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
11851185 .addReg(MI->getOperand(0).getReg()));
11861186 return;
11871187 }
11881188 case ARM::tBX_CALL: {
1189 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1189 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
11901190 .addReg(ARM::LR)
11911191 .addReg(ARM::PC)
11921192 // Add predicate operands.
11931193 .addImm(ARMCC::AL)
11941194 .addReg(0));
11951195
1196 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1196 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
11971197 .addReg(MI->getOperand(0).getReg())
11981198 // Add predicate operands.
11991199 .addImm(ARMCC::AL)
12011201 return;
12021202 }
12031203 case ARM::BMOVPCRX_CALL: {
1204 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1204 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
12051205 .addReg(ARM::LR)
12061206 .addReg(ARM::PC)
12071207 // Add predicate operands.
12101210 // Add 's' bit operand (always reg0 for this)
12111211 .addReg(0));
12121212
1213 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1213 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
12141214 .addReg(ARM::PC)
12151215 .addReg(MI->getOperand(0).getReg())
12161216 // Add predicate operands.
12211221 return;
12221222 }
12231223 case ARM::BMOVPCB_CALL: {
1224 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1224 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
12251225 .addReg(ARM::LR)
12261226 .addReg(ARM::PC)
12271227 // Add predicate operands.
12331233 const GlobalValue *GV = MI->getOperand(0).getGlobal();
12341234 MCSymbol *GVSym = getSymbol(GV);
12351235 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1236 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1236 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
12371237 .addExpr(GVSymExpr)
12381238 // Add predicate operands.
12391239 .addImm(ARMCC::AL)
12681268 TmpInst.addOperand(MCOperand::CreateReg(0));
12691269 // Add 's' bit operand (always reg0 for this)
12701270 TmpInst.addOperand(MCOperand::CreateReg(0));
1271 OutStreamer.EmitInstruction(TmpInst);
1271 EmitToStreamer(OutStreamer, TmpInst);
12721272 return;
12731273 }
12741274 case ARM::MOVTi16_ga_pcrel:
13001300 TmpInst.addOperand(MCOperand::CreateReg(0));
13011301 // Add 's' bit operand (always reg0 for this)
13021302 TmpInst.addOperand(MCOperand::CreateReg(0));
1303 OutStreamer.EmitInstruction(TmpInst);
1303 EmitToStreamer(OutStreamer, TmpInst);
13041304 return;
13051305 }
13061306 case ARM::tPICADD: {
13151315 OutContext));
13161316
13171317 // Form and emit the add.
1318 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1318 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
13191319 .addReg(MI->getOperand(0).getReg())
13201320 .addReg(MI->getOperand(0).getReg())
13211321 .addReg(ARM::PC)
13361336 OutContext));
13371337
13381338 // Form and emit the add.
1339 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1339 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
13401340 .addReg(MI->getOperand(0).getReg())
13411341 .addReg(ARM::PC)
13421342 .addReg(MI->getOperand(1).getReg())
13801380 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
13811381 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
13821382 }
1383 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1383 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
13841384 .addReg(MI->getOperand(0).getReg())
13851385 .addReg(ARM::PC)
13861386 .addReg(MI->getOperand(1).getReg())
14171417 }
14181418 case ARM::t2BR_JT: {
14191419 // Lower and emit the instruction itself, then the jump table following it.
1420 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1420 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
14211421 .addReg(ARM::PC)
14221422 .addReg(MI->getOperand(0).getReg())
14231423 // Add predicate operands.
14301430 }
14311431 case ARM::t2TBB_JT: {
14321432 // Lower and emit the instruction itself, then the jump table following it.
1433 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1433 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
14341434 .addReg(ARM::PC)
14351435 .addReg(MI->getOperand(0).getReg())
14361436 // Add predicate operands.
14451445 }
14461446 case ARM::t2TBH_JT: {
14471447 // Lower and emit the instruction itself, then the jump table following it.
1448 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1448 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
14491449 .addReg(ARM::PC)
14501450 .addReg(MI->getOperand(0).getReg())
14511451 // Add predicate operands.
14721472 // Add 's' bit operand (always reg0 for this)
14731473 if (Opc == ARM::MOVr)
14741474 TmpInst.addOperand(MCOperand::CreateReg(0));
1475 OutStreamer.EmitInstruction(TmpInst);
1475 EmitToStreamer(OutStreamer, TmpInst);
14761476
14771477 // Make sure the Thumb jump table is 4-byte aligned.
14781478 if (Opc == ARM::tMOVr)
15021502 // Add predicate operands.
15031503 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
15041504 TmpInst.addOperand(MCOperand::CreateReg(0));
1505 OutStreamer.EmitInstruction(TmpInst);
1505 EmitToStreamer(OutStreamer, TmpInst);
15061506
15071507 // Output the data for the jump table itself
15081508 EmitJumpTable(MI);
15111511 case ARM::BR_JTadd: {
15121512 // Lower and emit the instruction itself, then the jump table following it.
15131513 // add pc, target, idx
1514 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1514 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
15151515 .addReg(ARM::PC)
15161516 .addReg(MI->getOperand(0).getReg())
15171517 .addReg(MI->getOperand(1).getReg())
15711571 unsigned ValReg = MI->getOperand(1).getReg();
15721572 MCSymbol *Label = GetARMSJLJEHLabel();
15731573 OutStreamer.AddComment("eh_setjmp begin");
1574 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1574 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
15751575 .addReg(ValReg)
15761576 .addReg(ARM::PC)
15771577 // Predicate.
15781578 .addImm(ARMCC::AL)
15791579 .addReg(0));
15801580
1581 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1581 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
15821582 .addReg(ValReg)
15831583 // 's' bit operand
15841584 .addReg(ARM::CPSR)
15881588 .addImm(ARMCC::AL)
15891589 .addReg(0));
15901590
1591 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1591 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
15921592 .addReg(ValReg)
15931593 .addReg(SrcReg)
15941594 // The offset immediate is #4. The operand value is scaled by 4 for the
15981598 .addImm(ARMCC::AL)
15991599 .addReg(0));
16001600
1601 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1601 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
16021602 .addReg(ARM::R0)
16031603 .addReg(ARM::CPSR)
16041604 .addImm(0)
16071607 .addReg(0));
16081608
16091609 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1610 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1610 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
16111611 .addExpr(SymbolExpr)
16121612 .addImm(ARMCC::AL)
16131613 .addReg(0));
16141614
16151615 OutStreamer.AddComment("eh_setjmp end");
1616 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1616 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
16171617 .addReg(ARM::R0)
16181618 .addReg(ARM::CPSR)
16191619 .addImm(1)
16371637 unsigned ValReg = MI->getOperand(1).getReg();
16381638
16391639 OutStreamer.AddComment("eh_setjmp begin");
1640 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1640 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
16411641 .addReg(ValReg)
16421642 .addReg(ARM::PC)
16431643 .addImm(8)
16471647 // 's' bit operand (always reg0 for this).
16481648 .addReg(0));
16491649
1650 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1650 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
16511651 .addReg(ValReg)
16521652 .addReg(SrcReg)
16531653 .addImm(4)
16551655 .addImm(ARMCC::AL)
16561656 .addReg(0));
16571657
1658 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1658 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
16591659 .addReg(ARM::R0)
16601660 .addImm(0)
16611661 // Predicate.
16641664 // 's' bit operand (always reg0 for this).
16651665 .addReg(0));
16661666
1667 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1667 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
16681668 .addReg(ARM::PC)
16691669 .addReg(ARM::PC)
16701670 .addImm(0)
16751675 .addReg(0));
16761676
16771677 OutStreamer.AddComment("eh_setjmp end");
1678 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1678 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
16791679 .addReg(ARM::R0)
16801680 .addImm(1)
16811681 // Predicate.
16921692 // bx $scratch
16931693 unsigned SrcReg = MI->getOperand(0).getReg();
16941694 unsigned ScratchReg = MI->getOperand(1).getReg();
1695 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1695 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
16961696 .addReg(ARM::SP)
16971697 .addReg(SrcReg)
16981698 .addImm(8)
17001700 .addImm(ARMCC::AL)
17011701 .addReg(0));
17021702
1703 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1703 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
17041704 .addReg(ScratchReg)
17051705 .addReg(SrcReg)
17061706 .addImm(4)
17081708 .addImm(ARMCC::AL)
17091709 .addReg(0));
17101710
1711 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1711 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
17121712 .addReg(ARM::R7)
17131713 .addReg(SrcReg)
17141714 .addImm(0)
17161716 .addImm(ARMCC::AL)
17171717 .addReg(0));
17181718
1719 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1719 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
17201720 .addReg(ScratchReg)
17211721 // Predicate.
17221722 .addImm(ARMCC::AL)
17311731 // bx $scratch
17321732 unsigned SrcReg = MI->getOperand(0).getReg();
17331733 unsigned ScratchReg = MI->getOperand(1).getReg();
1734 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1734 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
17351735 .addReg(ScratchReg)
17361736 .addReg(SrcReg)
17371737 // The offset immediate is #8. The operand value is scaled by 4 for the
17411741 .addImm(ARMCC::AL)
17421742 .addReg(0));
17431743
1744 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1744 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
17451745 .addReg(ARM::SP)
17461746 .addReg(ScratchReg)
17471747 // Predicate.
17481748 .addImm(ARMCC::AL)
17491749 .addReg(0));
17501750
1751 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1751 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
17521752 .addReg(ScratchReg)
17531753 .addReg(SrcReg)
17541754 .addImm(1)
17561756 .addImm(ARMCC::AL)
17571757 .addReg(0));
17581758
1759 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1759 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
17601760 .addReg(ARM::R7)
17611761 .addReg(SrcReg)
17621762 .addImm(0)
17641764 .addImm(ARMCC::AL)
17651765 .addReg(0));
17661766
1767 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1767 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
17681768 .addReg(ScratchReg)
17691769 // Predicate.
17701770 .addImm(ARMCC::AL)
17761776 MCInst TmpInst;
17771777 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
17781778
1779 OutStreamer.EmitInstruction(TmpInst);
1779 EmitToStreamer(OutStreamer, TmpInst);
17801780 }
17811781
17821782 //===----------------------------------------------------------------------===//
79717971 return false;
79727972
79737973 Inst.setLoc(IDLoc);
7974 Out.EmitInstruction(Inst);
7974 Out.EmitInstruction(Inst, STI);
79757975 return false;
79767976 case Match_MissingFeature: {
79777977 assert(ErrorInfo && "Unknown missing feature!");
457457 /// This function is the one used to emit instruction data into the ELF
458458 /// streamer. We override it to add the appropriate mapping symbol if
459459 /// necessary.
460 virtual void EmitInstruction(const MCInst& Inst) {
460 virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) {
461461 if (IsThumb)
462462 EmitThumbMappingSymbol();
463463 else
464464 EmitARMMappingSymbol();
465465
466 MCELFStreamer::EmitInstruction(Inst);
466 MCELFStreamer::EmitInstruction(Inst, STI);
467467 }
468468
469469 virtual void emitInst(uint32_t Inst, char Suffix) {
198198 MCI.setPacketEnd(Index == (Size-1));
199199
200200 HexagonLowerToMC(BundleMIs[Index], MCI, *this);
201 OutStreamer.EmitInstruction(MCI);
201 EmitToStreamer(OutStreamer, MCI);
202202 }
203203 }
204204 else {
208208 MCI.setPacketEnd(true);
209209 }
210210 HexagonLowerToMC(MI, MCI, *this);
211 OutStreamer.EmitInstruction(MCI);
211 EmitToStreamer(OutStreamer, MCI);
212212 }
213213
214214 return;
150150
151151 MCInst TmpInst;
152152 MCInstLowering.Lower(MI, TmpInst);
153 OutStreamer.EmitInstruction(TmpInst);
153 EmitToStreamer(OutStreamer, TmpInst);
154154 }
155155
156156 // Force static initialization.
905905 if (processInstruction(Inst, IDLoc, Instructions))
906906 return true;
907907 for (unsigned i = 0; i < Instructions.size(); i++)
908 Out.EmitInstruction(Instructions[i]);
908 Out.EmitInstruction(Instructions[i], STI);
909909 return false;
910910 }
911911 case Match_MissingFeature:
130130
131131 MCInst TmpInst0;
132132 MCInstLowering.Lower(I, TmpInst0);
133 OutStreamer.EmitInstruction(TmpInst0);
133 EmitToStreamer(OutStreamer, TmpInst0);
134134 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
135135 }
136136
306306
307307 MCInst Inst;
308308 lowerToMCInst(MI, Inst);
309 OutStreamer.EmitInstruction(Inst);
309 EmitToStreamer(OutStreamer, Inst);
310310 }
311311
312312 void NVPTXAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
872872 // Post-process instructions (typically extended mnemonics)
873873 ProcessInstruction(Inst, Operands);
874874 Inst.setLoc(IDLoc);
875 Out.EmitInstruction(Inst);
875 Out.EmitInstruction(Inst, STI);
876876 return false;
877877 case Match_MissingFeature:
878878 return Error(IDLoc, "instruction use requires an option to be enabled");
316316 MCSymbol *PICBase = MF->getPICBaseSymbol();
317317
318318 // Emit the 'bl'.
319 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL)
319 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL)
320320 // FIXME: We would like an efficient form for this, so we don't have to do
321321 // a lot of extra uniquing.
322322 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
352352 MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
353353 OutContext);
354354 TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
355 OutStreamer.EmitInstruction(TmpInst);
355 EmitToStreamer(OutStreamer, TmpInst);
356356 return;
357357 }
358358
398398 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_HA,
399399 OutContext);
400400 TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
401 OutStreamer.EmitInstruction(TmpInst);
401 EmitToStreamer(OutStreamer, TmpInst);
402402 return;
403403 }
404404 case PPC::LDtocL: {
439439 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
440440 OutContext);
441441 TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
442 OutStreamer.EmitInstruction(TmpInst);
442 EmitToStreamer(OutStreamer, TmpInst);
443443 return;
444444 }
445445 case PPC::ADDItocL: {
475475 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
476476 OutContext);
477477 TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
478 OutStreamer.EmitInstruction(TmpInst);
478 EmitToStreamer(OutStreamer, TmpInst);
479479 return;
480480 }
481481 case PPC::ADDISgotTprelHA: {
488488 const MCExpr *SymGotTprel =
489489 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_HA,
490490 OutContext);
491 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
491 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8)
492492 .addReg(MI->getOperand(0).getReg())
493493 .addReg(PPC::X2)
494494 .addExpr(SymGotTprel));
508508 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO,
509509 OutContext);
510510 TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
511 OutStreamer.EmitInstruction(TmpInst);
511 EmitToStreamer(OutStreamer, TmpInst);
512512 return;
513513 }
514514
520520 const MCExpr *SymGotTlsHA =
521521 MCSymbolRefExpr::Create(GOTSymbol, MCSymbolRefExpr::VK_PPC_HA,
522522 OutContext);
523 OutStreamer.EmitInstruction(MCInstBuilder(PPC::LI)
523 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::LI)
524524 .addReg(MI->getOperand(0).getReg())
525525 .addExpr(SymGotTlsL));
526 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS)
526 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS)
527527 .addReg(MI->getOperand(0).getReg())
528528 .addReg(MI->getOperand(0).getReg())
529529 .addExpr(SymGotTlsHA));
539539 const MCExpr *SymGotTlsGD =
540540 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_HA,
541541 OutContext);
542 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
542 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8)
543543 .addReg(MI->getOperand(0).getReg())
544544 .addReg(PPC::X2)
545545 .addExpr(SymGotTlsGD));
555555 const MCExpr *SymGotTlsGD =
556556 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO,
557557 OutContext);
558 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8)
558 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
559559 .addReg(MI->getOperand(0).getReg())
560560 .addReg(MI->getOperand(1).getReg())
561561 .addExpr(SymGotTlsGD));
576576 const MCExpr *SymVar =
577577 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSGD,
578578 OutContext);
579 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_TLS)
579 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS)
580580 .addExpr(TlsRef)
581581 .addExpr(SymVar));
582582 return;
591591 const MCExpr *SymGotTlsLD =
592592 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_HA,
593593 OutContext);
594 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
594 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8)
595595 .addReg(MI->getOperand(0).getReg())
596596 .addReg(PPC::X2)
597597 .addExpr(SymGotTlsLD));
607607 const MCExpr *SymGotTlsLD =
608608 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO,
609609 OutContext);
610 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8)
610 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
611611 .addReg(MI->getOperand(0).getReg())
612612 .addReg(MI->getOperand(1).getReg())
613613 .addExpr(SymGotTlsLD));
628628 const MCExpr *SymVar =
629629 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSLD,
630630 OutContext);
631 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_TLS)
631 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL8_NOP_TLS)
632632 .addExpr(TlsRef)
633633 .addExpr(SymVar));
634634 return;
643643 const MCExpr *SymDtprel =
644644 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_HA,
645645 OutContext);
646 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
646 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8)
647647 .addReg(MI->getOperand(0).getReg())
648648 .addReg(PPC::X3)
649649 .addExpr(SymDtprel));
659659 const MCExpr *SymDtprel =
660660 MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_LO,
661661 OutContext);
662 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8)
662 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDI8)
663663 .addReg(MI->getOperand(0).getReg())
664664 .addReg(MI->getOperand(1).getReg())
665665 .addExpr(SymDtprel));
674674 MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8;
675675 OutStreamer.AddComment(PPCInstPrinter::
676676 getRegisterName(MI->getOperand(1).getReg()));
677 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode)
677 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
678678 .addReg(MI->getOperand(0).getReg()));
679679 return;
680680 }
690690 ->getEncodingValue(MI->getOperand(0).getReg());
691691 OutStreamer.AddComment(PPCInstPrinter::
692692 getRegisterName(MI->getOperand(0).getReg()));
693 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode)
693 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
694694 .addImm(Mask)
695695 .addReg(MI->getOperand(1).getReg()));
696696 return;
718718 }
719719
720720 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
721 OutStreamer.EmitInstruction(TmpInst);
721 EmitToStreamer(OutStreamer, TmpInst);
722722 }
723723
724724 void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() {
924924 MCBinaryExpr::CreateSub(LazyPtrExpr, Anon, OutContext);
925925
926926 // mflr r0
927 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R0));
927 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MFLR).addReg(PPC::R0));
928928 // bcl 20, 31, AnonSymbol
929 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCLalways).addExpr(Anon));
929 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BCLalways).addExpr(Anon));
930930 OutStreamer.EmitLabel(AnonSymbol);
931931 // mflr r11
932 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R11));
932 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MFLR).addReg(PPC::R11));
933933 // addis r11, r11, ha16(LazyPtr - AnonSymbol)
934934 const MCExpr *SubHa16 = PPCMCExpr::CreateHa(Sub, isDarwin, OutContext);
935 OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS)
935 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS)
936936 .addReg(PPC::R11)
937937 .addReg(PPC::R11)
938938 .addExpr(SubHa16));
939939 // mtlr r0
940 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTLR).addReg(PPC::R0));
940 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTLR).addReg(PPC::R0));
941941
942942 // ldu r12, lo16(LazyPtr - AnonSymbol)(r11)
943943 // lwzu r12, lo16(LazyPtr - AnonSymbol)(r11)
944944 const MCExpr *SubLo16 = PPCMCExpr::CreateLo(Sub, isDarwin, OutContext);
945 OutStreamer.EmitInstruction(MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
945 EmitToStreamer(OutStreamer, MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
946946 .addReg(PPC::R12)
947947 .addExpr(SubLo16).addExpr(SubLo16)
948948 .addReg(PPC::R11));
949949 // mtctr r12
950 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
950 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
951951 // bctr
952 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCTR));
952 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BCTR));
953953
954954 OutStreamer.SwitchSection(LSPSection);
955955 OutStreamer.EmitLabel(LazyPtr);
988988 // lis r11, ha16(LazyPtr)
989989 const MCExpr *LazyPtrHa16 =
990990 PPCMCExpr::CreateHa(LazyPtrExpr, isDarwin, OutContext);
991 OutStreamer.EmitInstruction(MCInstBuilder(PPC::LIS)
991 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::LIS)
992992 .addReg(PPC::R11)
993993 .addExpr(LazyPtrHa16));
994994
996996 // lwzu r12, lo16(LazyPtr)(r11)
997997 const MCExpr *LazyPtrLo16 =
998998 PPCMCExpr::CreateLo(LazyPtrExpr, isDarwin, OutContext);
999 OutStreamer.EmitInstruction(MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
999 EmitToStreamer(OutStreamer, MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
10001000 .addReg(PPC::R12)
10011001 .addExpr(LazyPtrLo16).addExpr(LazyPtrLo16)
10021002 .addReg(PPC::R11));
10031003
10041004 // mtctr r12
1005 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
1005 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
10061006 // bctr
1007 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BCTR));
1007 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BCTR));
10081008
10091009 OutStreamer.SwitchSection(LSPSection);
10101010 OutStreamer.EmitLabel(LazyPtr);
7979 } else {
8080 MCInst TmpInst;
8181 MCInstLowering.lower(MI, TmpInst);
82 OutStreamer.EmitInstruction(TmpInst);
82 EmitToStreamer(OutStreamer, TmpInst);
8383
8484 if (DisasmEnabled) {
8585 // Disassemble instruction/operands to text.
392392
393393 case Match_Success: {
394394 Inst.setLoc(IDLoc);
395 Out.EmitInstruction(Inst);
395 Out.EmitInstruction(Inst, STI);
396396 return false;
397397 }
398398
106106 }
107107
108108 static void EmitCall(MCStreamer &OutStreamer,
109 MCOperand &Callee)
109 MCOperand &Callee,
110 const MCSubtargetInfo &STI)
110111 {
111112 MCInst CallInst;
112113 CallInst.setOpcode(SP::CALL);
113114 CallInst.addOperand(Callee);
114 OutStreamer.EmitInstruction(CallInst);
115 OutStreamer.EmitInstruction(CallInst, STI);
115116 }
116117
117118 static void EmitSETHI(MCStreamer &OutStreamer,
118 MCOperand &Imm, MCOperand &RD)
119 MCOperand &Imm, MCOperand &RD,
120 const MCSubtargetInfo &STI)
119121 {
120122 MCInst SETHIInst;
121123 SETHIInst.setOpcode(SP::SETHIi);
122124 SETHIInst.addOperand(RD);
123125 SETHIInst.addOperand(Imm);
124 OutStreamer.EmitInstruction(SETHIInst);
126 OutStreamer.EmitInstruction(SETHIInst, STI);
125127 }
126128
127129 static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
128 MCOperand &RS1, MCOperand &Src2, MCOperand &RD)
130 MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
131 const MCSubtargetInfo &STI)
129132 {
130133 MCInst Inst;
131134 Inst.setOpcode(Opcode);
132135 Inst.addOperand(RD);
133136 Inst.addOperand(RS1);
134137 Inst.addOperand(Src2);
135 OutStreamer.EmitInstruction(Inst);
138 OutStreamer.EmitInstruction(Inst, STI);
136139 }
137140
138141 static void EmitOR(MCStreamer &OutStreamer,
139 MCOperand &RS1, MCOperand &Imm, MCOperand &RD) {
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD);
142 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
143 const MCSubtargetInfo &STI) {
144 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
141145 }
142146
143147 static void EmitADD(MCStreamer &OutStreamer,
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD) {
145 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD);
148 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
149 const MCSubtargetInfo &STI) {
150 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
146151 }
147152
148153 static void EmitSHL(MCStreamer &OutStreamer,
149 MCOperand &RS1, MCOperand &Imm, MCOperand &RD) {
150 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD);
154 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
155 const MCSubtargetInfo &STI) {
156 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
151157 }
152158
153159
155161 SparcMCExpr::VariantKind HiKind,
156162 SparcMCExpr::VariantKind LoKind,
157163 MCOperand &RD,
158 MCContext &OutContext) {
164 MCContext &OutContext,
165 const MCSubtargetInfo &STI) {
159166
160167 MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
161168 MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
162 EmitSETHI(OutStreamer, hi, RD);
163 EmitOR(OutStreamer, RD, lo, RD);
164 }
165
166 void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI)
169 EmitSETHI(OutStreamer, hi, RD, STI);
170 EmitOR(OutStreamer, RD, lo, RD, STI);
171 }
172
173 void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
174 const MCSubtargetInfo &STI)
167175 {
168176 MCSymbol *GOTLabel =
169177 OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
231239
232240 OutStreamer.EmitLabel(StartLabel);
233241 MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
234 EmitCall(OutStreamer, Callee);
242 EmitCall(OutStreamer, Callee, STI);
235243 OutStreamer.EmitLabel(SethiLabel);
236244 MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_HI,
237245 GOTLabel, StartLabel, SethiLabel,
238246 OutContext);
239 EmitSETHI(OutStreamer, hiImm, MCRegOP);
247 EmitSETHI(OutStreamer, hiImm, MCRegOP, STI);
240248 OutStreamer.EmitLabel(EndLabel);
241249 MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_LO,
242250 GOTLabel, StartLabel, EndLabel,
243251 OutContext);
244 EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP);
245 EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
252 EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP, STI);
253 EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
246254 }
247255
248256 void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
254262 // FIXME: Debug Value.
255263 return;
256264 case SP::GETPCX:
257 LowerGETPCXAndEmitMCInsts(MI);
265 LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
258266 return;
259267 }
260268 MachineBasicBlock::const_instr_iterator I = MI;
262270 do {
263271 MCInst TmpInst;
264272 LowerSparcMachineInstrToMCInst(I, TmpInst, *this);
265 OutStreamer.EmitInstruction(TmpInst);
273 EmitToStreamer(OutStreamer, TmpInst);
266274 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
267275 }
268276
714714 default: break;
715715 case Match_Success:
716716 Inst.setLoc(IDLoc);
717 Out.EmitInstruction(Inst);
717 Out.EmitInstruction(Inst, STI);
718718 return false;
719719
720720 case Match_MissingFeature: {
163163 Lower.lower(MI, LoweredMI);
164164 break;
165165 }
166 OutStreamer.EmitInstruction(LoweredMI);
166 EmitToStreamer(OutStreamer, LoweredMI);
167167 }
168168
169169 // Convert a SystemZ-specific constant pool modifier into the associated
26062606 Inst.setOpcode(X86::WAIT);
26072607 Inst.setLoc(IDLoc);
26082608 if (!MatchingInlineAsm)
2609 Out.EmitInstruction(Inst);
2609 Out.EmitInstruction(Inst, STI);
26102610
26112611 const char *Repl =
26122612 StringSwitch(Op->getToken())
26422642
26432643 Inst.setLoc(IDLoc);
26442644 if (!MatchingInlineAsm)
2645 Out.EmitInstruction(Inst);
2645 Out.EmitInstruction(Inst, STI);
26462646 Opcode = Inst.getOpcode();
26472647 return false;
26482648 case Match_MissingFeature: {
27292729 if (NumSuccessfulMatches == 1) {
27302730 Inst.setLoc(IDLoc);
27312731 if (!MatchingInlineAsm)
2732 Out.EmitInstruction(Inst);
2732 Out.EmitInstruction(Inst, STI);
27332733 Opcode = Inst.getOpcode();
27342734 return false;
27352735 }
601601
602602 static void LowerTlsAddr(MCStreamer &OutStreamer,
603603 X86MCInstLower &MCInstLowering,
604 const MachineInstr &MI) {
604 const MachineInstr &MI,
605 const MCSubtargetInfo& STI) {
605606
606607 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
607608 MI.getOpcode() == X86::TLS_base_addr64;
611612 MCContext &context = OutStreamer.getContext();
612613
613614 if (needsPadding)
614 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
615 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
615616
616617 MCSymbolRefExpr::VariantKind SRVK;
617618 switch (MI.getOpcode()) {
658659 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
659660 LEA.addOperand(MCOperand::CreateReg(0)); // seg
660661 }
661 OutStreamer.EmitInstruction(LEA);
662 OutStreamer.EmitInstruction(LEA, STI);
662663
663664 if (needsPadding) {
664 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
665 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
666 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
665 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
666 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
667 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI);
667668 }
668669
669670 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
675676
676677 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
677678 : X86::CALLpcrel32)
678 .addExpr(tlsRef));
679 .addExpr(tlsRef), STI);
679680 }
680681
681682 /// \brief Emit the optimal amount of multi-byte nops on X86.
682 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) {
683 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
683684 // This works only for 64bit. For 32bit we have to do additional checking if
684685 // the CPU supports multi-byte nops.
685686 assert(Is64Bit && "EmitNops only supports X86-64");
714715 switch (Opc) {
715716 default: llvm_unreachable("Unexpected opcode"); break;
716717 case X86::NOOP:
717 OS.EmitInstruction(MCInstBuilder(Opc));
718 OS.EmitInstruction(MCInstBuilder(Opc), STI);
718719 break;
719720 case X86::XCHG16ar:
720 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX));
721 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
721722 break;
722723 case X86::NOOPL:
723724 case X86::NOOPW:
724725 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
725726 .addReg(IndexReg)
726727 .addImm(Displacement)
727 .addReg(SegmentReg));
728 .addReg(SegmentReg), STI);
728729 break;
729730 }
730731 } // while (NumBytes)
733734 // Lower a stackmap of the form:
734735 // , , ...
735736 static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,
736 const MachineInstr &MI, bool Is64Bit) {
737 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
737738 unsigned NumBytes = MI.getOperand(1).getImm();
738739 SM.recordStackMap(MI);
739740 // Emit padding.
740741 // FIXME: These nops ensure that the stackmap's shadow is covered by
741742 // instructions from the same basic block, but the nops should not be
742743 // necessary if instructions from the same block follow the stackmap.
743 EmitNops(OS, NumBytes, Is64Bit);
744 EmitNops(OS, NumBytes, Is64Bit, STI);
744745 }
745746
746747 // Lower a patchpoint of the form:
747748 // [], , , , , , ...
748749 static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,
749 const MachineInstr &MI, bool Is64Bit) {
750 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
750751 assert(Is64Bit && "Patchpoint currently only supports X86-64");
751752 SM.recordPatchPoint(MI);
752753
763764 else
764765 EncodedBytes = 12;
765766 OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
766 .addImm(CallTarget));
767 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
767 .addImm(CallTarget), STI);
768 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI);
768769 }
769770 // Emit padding.
770771 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
771772 assert(NumBytes >= EncodedBytes &&
772773 "Patchpoint can't request size less than the length of a call.");
773774
774 EmitNops(OS, NumBytes - EncodedBytes, Is64Bit);
775 EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI);
775776 }
776777
777778 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
805806 case X86::TLS_addr64:
806807 case X86::TLS_base_addr32:
807808 case X86::TLS_base_addr64:
808 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
809 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo());
809810
810811 case X86::MOVPC32r: {
811812 // This is a pseudo op for a two instruction sequence with a label, which
818819 MCSymbol *PICBase = MF->getPICBaseSymbol();
819820 // FIXME: We would like an efficient form for this, so we don't have to do a
820821 // lot of extra uniquing.
821 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
822 EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32)
822823 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
823824
824825 // Emit the label.
825826 OutStreamer.EmitLabel(PICBase);
826827
827828 // popl $reg
828 OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
829 EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r)
829830 .addReg(MI->getOperand(0).getReg()));
830831 return;
831832 }
856857 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
857858 DotExpr, OutContext);
858859
859 OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
860 EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri)
860861 .addReg(MI->getOperand(0).getReg())
861862 .addReg(MI->getOperand(1).getReg())
862863 .addExpr(DotExpr));
864865 }
865866
866867 case TargetOpcode::STACKMAP:
867 return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit());
868 return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
868869
869870 case TargetOpcode::PATCHPOINT:
870 return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit());
871 return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
871872
872873 case X86::MORESTACK_RET:
873 OutStreamer.EmitInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
874 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
874875 return;
875876
876877 case X86::MORESTACK_RET_RESTORE_R10:
877878 // Return, then restore R10.
878 OutStreamer.EmitInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
879 OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64rr)
879 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
880 EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr)
880881 .addReg(X86::R10)
881882 .addReg(X86::RAX));
882883 return;
884885
885886 MCInst TmpInst;
886887 MCInstLowering.Lower(MI, TmpInst);
887 OutStreamer.EmitInstruction(TmpInst);
888 }
888 EmitToStreamer(OutStreamer, TmpInst);
889 }
276276 MCInst TmpInst;
277277 MCInstLowering.Lower(MI, TmpInst);
278278
279 OutStreamer.EmitInstruction(TmpInst);
279 EmitToStreamer(OutStreamer, TmpInst);
280280 }
281281
282282 // Force static initialization.
5050 static bool PrintInsts(const MCDisassembler &DisAsm,
5151 const ByteArrayTy &Bytes,
5252 SourceMgr &SM, raw_ostream &Out,
53 MCStreamer &Streamer, bool InAtomicBlock) {
53 MCStreamer &Streamer, bool InAtomicBlock,
54 const MCSubtargetInfo &STI) {
5455 // Wrap the vector in a MemoryObject.
5556 VectorMemoryObject memoryObject(Bytes);
5657
8586 // Fall through
8687
8788 case MCDisassembler::Success:
88 Streamer.EmitInstruction(Inst);
89 Streamer.EmitInstruction(Inst, STI);
8990 break;
9091 }
9192 }
201202
202203 if (!ByteArray.empty())
203204 ErrorOccurred |= PrintInsts(*DisAsm, ByteArray, SM, Out, Streamer,
204 InAtomicBlock);
205 InAtomicBlock, STI);
205206 }
206207
207208 if (InAtomicBlock) {
258258 << " if (lowerOperand(MI->getOperand(i), MCOp))\n"
259259 << " TmpInst.addOperand(MCOp);\n";
260260 }
261 o << " OutStreamer.EmitInstruction(TmpInst);\n"
261 o << " EmitToStreamer(OutStreamer, TmpInst);\n"
262262 << " break;\n"
263263 << " }\n";
264264 }