llvm.org GIT mirror llvm / 4383a51
CodeGen: Use MachineInstr& in LiveVariables API, NFC Change all the methods in LiveVariables that expect non-null MachineInstr* to take MachineInstr& and update the call sites. This clarifies the API, and designs away a class of iterator to pointer implicit conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274319 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan P. N. Exon Smith 4 years ago
8 changed file(s) with 80 addition(s) and 81 deletion(s). Raw diff Collapse all Expand all
9090 /// removeKill - Delete a kill corresponding to the specified
9191 /// machine instruction. Returns true if there was a kill
9292 /// corresponding to this instruction, false otherwise.
93 bool removeKill(MachineInstr *MI) {
94 std::vector::iterator
95 I = std::find(Kills.begin(), Kills.end(), MI);
93 bool removeKill(MachineInstr &MI) {
94 std::vector::iterator I =
95 std::find(Kills.begin(), Kills.end(), &MI);
9696 if (I == Kills.end())
9797 return false;
9898 Kills.erase(I);
154154 /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
155155 void HandleRegMask(const MachineOperand&);
156156
157 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
157 void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
158158 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
159159 SmallVectorImpl &Defs);
160 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl &Defs);
160 void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl &Defs);
161161
162162 /// FindLastRefOrPartRef - Return the last reference or partial reference of
163163 /// the specified register.
175175 /// is coming from.
176176 void analyzePHINodes(const MachineFunction& Fn);
177177
178 void runOnInstr(MachineInstr *MI, SmallVectorImpl &Defs);
178 void runOnInstr(MachineInstr &MI, SmallVectorImpl &Defs);
179179
180180 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
181181 public:
184184
185185 /// RegisterDefIsDead - Return true if the specified instruction defines the
186186 /// specified register, but that definition is dead.
187 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
187 bool RegisterDefIsDead(MachineInstr &MI, unsigned Reg) const;
188188
189189 //===--------------------------------------------------------------------===//
190190 // API to update live variable information
191191
192192 /// replaceKillInstruction - Update register kill info by replacing a kill
193193 /// instruction with a new one.
194 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
195 MachineInstr *NewMI);
194 void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
195 MachineInstr &NewMI);
196196
197197 /// addVirtualRegisterKilled - Add information about the fact that the
198198 /// specified register is killed after being used by the specified
199199 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
200200 /// not found.
201 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
201 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI,
202202 bool AddIfNotFound = false) {
203 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
204 getVarInfo(IncomingReg).Kills.push_back(MI);
203 if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
204 getVarInfo(IncomingReg).Kills.push_back(&MI);
205205 }
206206
207207 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
208208 /// register from the live variable information. Returns true if the
209209 /// variable was marked as killed by the specified instruction,
210210 /// false otherwise.
211 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
211 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) {
212212 if (!getVarInfo(reg).removeKill(MI))
213213 return false;
214214
215215 bool Removed = false;
216 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
217 MachineOperand &MO = MI->getOperand(i);
216 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
217 MachineOperand &MO = MI.getOperand(i);
218218 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
219219 MO.setIsKill(false);
220220 Removed = true;
229229
230230 /// removeVirtualRegistersKilled - Remove all killed info for the specified
231231 /// instruction.
232 void removeVirtualRegistersKilled(MachineInstr *MI);
232 void removeVirtualRegistersKilled(MachineInstr &MI);
233233
234234 /// addVirtualRegisterDead - Add information about the fact that the specified
235235 /// register is dead after being used by the specified instruction. If
236236 /// AddIfNotFound is true, add a implicit operand if it's not found.
237 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
237 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI,
238238 bool AddIfNotFound = false) {
239 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
240 getVarInfo(IncomingReg).Kills.push_back(MI);
239 if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound))
240 getVarInfo(IncomingReg).Kills.push_back(&MI);
241241 }
242242
243243 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
244244 /// register from the live variable information. Returns true if the
245245 /// variable was marked dead at the specified instruction, false
246246 /// otherwise.
247 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
247 bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) {
248248 if (!getVarInfo(reg).removeKill(MI))
249249 return false;
250250
251251 bool Removed = false;
252 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
253 MachineOperand &MO = MI->getOperand(i);
252 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
253 MachineOperand &MO = MI.getOperand(i);
254254 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
255255 MO.setIsDead(false);
256256 Removed = true;
277277 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
278278 MachineBasicBlock *BB,
279279 std::vector &WorkList);
280 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
281 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
282 MachineInstr *MI);
280 void HandleVirtRegDef(unsigned reg, MachineInstr &MI);
281 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI);
283282
284283 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
285284 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
128128 }
129129
130130 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
131 MachineInstr *MI) {
131 MachineInstr &MI) {
132132 assert(MRI->getVRegDef(reg) && "Register use before def!");
133133
134134 unsigned BBNum = MBB->getNumber();
139139 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
140140 // Yes, this register is killed in this basic block already. Increase the
141141 // live range by updating the kill instruction.
142 VRInfo.Kills.back() = MI;
142 VRInfo.Kills.back() = &MI;
143143 return;
144144 }
145145
170170 // already marked as alive in this basic block, that means it is alive in at
171171 // least one of the successor blocks, it's not a kill.
172172 if (!VRInfo.AliveBlocks.test(BBNum))
173 VRInfo.Kills.push_back(MI);
173 VRInfo.Kills.push_back(&MI);
174174
175175 // Update all dominating blocks to mark them as "known live".
176176 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
178178 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
179179 }
180180
181 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
181 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) {
182182 VarInfo &VRInfo = getVarInfo(Reg);
183183
184184 if (VRInfo.AliveBlocks.empty())
185185 // If vr is not alive in any block, then defaults to dead.
186 VRInfo.Kills.push_back(MI);
186 VRInfo.Kills.push_back(&MI);
187187 }
188188
189189 /// FindLastPartialDef - Return the last partial def of the specified register.
227227 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
228228 /// implicit defs to a machine instruction if there was an earlier def of its
229229 /// super-register.
230 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
230 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
231231 MachineInstr *LastDef = PhysRegDef[Reg];
232232 // If there was a previous use or a "full" def all is well.
233233 if (!LastDef && !PhysRegUse[Reg]) {
272272 // Remember this use.
273273 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
274274 SubRegs.isValid(); ++SubRegs)
275 PhysRegUse[*SubRegs] = MI;
275 PhysRegUse[*SubRegs] = &MI;
276276 }
277277
278278 /// FindLastRefOrPartRef - Return the last reference or partial reference of
482482 Defs.push_back(Reg); // Remember this def.
483483 }
484484
485 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
485 void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
486486 SmallVectorImpl &Defs) {
487487 while (!Defs.empty()) {
488488 unsigned Reg = Defs.back();
490490 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
491491 SubRegs.isValid(); ++SubRegs) {
492492 unsigned SubReg = *SubRegs;
493 PhysRegDef[SubReg] = MI;
493 PhysRegDef[SubReg] = &MI;
494494 PhysRegUse[SubReg] = nullptr;
495495 }
496496 }
497497 }
498498
499 void LiveVariables::runOnInstr(MachineInstr *MI,
499 void LiveVariables::runOnInstr(MachineInstr &MI,
500500 SmallVectorImpl &Defs) {
501 assert(!MI->isDebugValue());
501 assert(!MI.isDebugValue());
502502 // Process all of the operands of the instruction...
503 unsigned NumOperandsToProcess = MI->getNumOperands();
503 unsigned NumOperandsToProcess = MI.getNumOperands();
504504
505505 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
506506 // of the uses. They will be handled in other basic blocks.
507 if (MI->isPHI())
507 if (MI.isPHI())
508508 NumOperandsToProcess = 1;
509509
510510 // Clear kill and dead markers. LV will recompute them.
512512 SmallVector DefRegs;
513513 SmallVector RegMasks;
514514 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
515 MachineOperand &MO = MI->getOperand(i);
515 MachineOperand &MO = MI.getOperand(i);
516516 if (MO.isRegMask()) {
517517 RegMasks.push_back(i);
518518 continue;
537537 }
538538 }
539539
540 MachineBasicBlock *MBB = MI->getParent();
540 MachineBasicBlock *MBB = MI.getParent();
541541 // Process all uses.
542542 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
543543 unsigned MOReg = UseRegs[i];
549549
550550 // Process all masked registers. (Call clobbers).
551551 for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
552 HandleRegMask(MI->getOperand(RegMasks[i]));
552 HandleRegMask(MI.getOperand(RegMasks[i]));
553553
554554 // Process all defs.
555555 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
557557 if (TargetRegisterInfo::isVirtualRegister(MOReg))
558558 HandleVirtRegDef(MOReg, MI);
559559 else if (!MRI->isReserved(MOReg))
560 HandlePhysRegDef(MOReg, MI, Defs);
560 HandlePhysRegDef(MOReg, &MI, Defs);
561561 }
562562 UpdatePhysRegDefs(MI, Defs);
563563 }
579579 continue;
580580 DistanceMap.insert(std::make_pair(&MI, Dist++));
581581
582 runOnInstr(&MI, Defs);
582 runOnInstr(MI, Defs);
583583 }
584584
585585 // Handle any virtual assignments from PHI nodes which might be at the
679679
680680 /// replaceKillInstruction - Update register kill info by replacing a kill
681681 /// instruction with a new one.
682 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
683 MachineInstr *NewMI) {
682 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
683 MachineInstr &NewMI) {
684684 VarInfo &VI = getVarInfo(Reg);
685 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
685 std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);
686686 }
687687
688688 /// removeVirtualRegistersKilled - Remove all killed info for the specified
689689 /// instruction.
690 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
691 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
692 MachineOperand &MO = MI->getOperand(i);
690 void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) {
691 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
692 MachineOperand &MO = MI.getOperand(i);
693693 if (MO.isReg() && MO.isKill()) {
694694 MO.setIsKill(false);
695695 unsigned Reg = MO.getReg();
744744 continue;
745745 unsigned Reg = OI->getReg();
746746 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
747 LV->getVarInfo(Reg).removeKill(MI)) {
747 LV->getVarInfo(Reg).removeKill(*MI)) {
748748 KilledRegs.push_back(Reg);
749749 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
750750 OI->setIsKill(false);
282282 if (reusedIncoming)
283283 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
284284 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
285 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
285 LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
286286 DEBUG(MBB.dump());
287287 }
288288
290290 // killed. Note that because the value is defined in several places (once
291291 // each for each incoming block), the "def" block and instruction fields
292292 // for the VarInfo is not filled in.
293 LV->addVirtualRegisterKilled(IncomingReg, &PHICopy);
293 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
294294 }
295295
296296 // Since we are going to be deleting the PHI node, if it is the last use of
297297 // any registers, or if the value itself is dead, we need to move this
298298 // information over to the new copy we just inserted.
299 LV->removeVirtualRegistersKilled(MPhi);
299 LV->removeVirtualRegistersKilled(*MPhi);
300300
301301 // If the result is dead, update LV.
302302 if (isDead) {
303 LV->addVirtualRegisterDead(DestReg, &PHICopy);
304 LV->removeVirtualRegisterDead(DestReg, MPhi);
303 LV->addVirtualRegisterDead(DestReg, PHICopy);
304 LV->removeVirtualRegisterDead(DestReg, *MPhi);
305305 }
306306 }
307307
451451 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
452452
453453 // Finally, mark it killed.
454 LV->addVirtualRegisterKilled(SrcReg, &*KillInst);
454 LV->addVirtualRegisterKilled(SrcReg, *KillInst);
455455
456456 // This vreg no longer lives all of the way through opBlock.
457457 unsigned opBlockNum = opBlock.getNumber();
297297 KillMO->setIsKill(true);
298298
299299 if (LV)
300 LV->replaceKillInstruction(SavedReg, KillMI, MI);
300 LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
301301 }
302302
303303 // Move instruction to its destination.
970970 if (LIS) {
971971 LIS->handleMove(*MI);
972972 } else {
973 LV->removeVirtualRegisterKilled(Reg, KillMI);
974 LV->addVirtualRegisterKilled(Reg, MI);
973 LV->removeVirtualRegisterKilled(Reg, *KillMI);
974 LV->addVirtualRegisterKilled(Reg, *MI);
975975 }
976976
977977 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
11381138 if (LIS) {
11391139 LIS->handleMove(*KillMI);
11401140 } else {
1141 LV->removeVirtualRegisterKilled(Reg, KillMI);
1142 LV->addVirtualRegisterKilled(Reg, MI);
1141 LV->removeVirtualRegisterKilled(Reg, *KillMI);
1142 LV->addVirtualRegisterKilled(Reg, *MI);
11431143 }
11441144
11451145 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
13451345 if (MO.isUse()) {
13461346 if (MO.isKill()) {
13471347 if (NewMIs[0]->killsRegister(MO.getReg()))
1348 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1348 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
13491349 else {
13501350 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
13511351 "Kill missing after load unfold!");
1352 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1352 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
13531353 }
13541354 }
1355 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1355 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
13561356 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1357 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1357 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
13581358 else {
13591359 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
13601360 "Dead flag missing after load unfold!");
1361 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1361 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
13621362 }
13631363 }
13641364 }
13651365 }
1366 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1366 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
13671367 }
13681368
13691369 SmallVector OrigRegs;
15721572 }
15731573
15741574 // Update live variables for regB.
1575 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1575 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
15761576 MachineBasicBlock::iterator PrevMI = MI;
15771577 --PrevMI;
1578 LV->addVirtualRegisterKilled(RegB, PrevMI);
1578 LV->addVirtualRegisterKilled(RegB, *PrevMI);
15791579 }
15801580
15811581 // Update LiveIntervals.
17851785
17861786 // Update LiveVariables' kill info.
17871787 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1788 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1788 LV->replaceKillInstruction(SrcReg, *MI, *CopyMI);
17891789
17901790 DEBUG(dbgs() << "Inserted: " << *CopyMI);
17911791 }
273273 if (MO.isDef()) {
274274 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
275275 if (MO.isDead())
276 LV->addVirtualRegisterDead(Reg, NewMI);
276 LV->addVirtualRegisterDead(Reg, *NewMI);
277277 }
278278 if (MO.isUse() && MO.isKill()) {
279279 for (unsigned j = 0; j < 2; ++j) {
281281 MachineInstr *NewMI = NewMIs[j];
282282 if (!NewMI->readsRegister(Reg))
283283 continue;
284 LV->addVirtualRegisterKilled(Reg, NewMI);
285 if (VI.removeKill(&MI))
284 LV->addVirtualRegisterKilled(Reg, *NewMI);
285 if (VI.removeKill(MI))
286286 VI.Kills.push_back(NewMI);
287287 break;
288288 }
759759 for (unsigned I = 1; I < NumOps; ++I) {
760760 MachineOperand &Op = OldMI->getOperand(I);
761761 if (Op.isReg() && Op.isKill())
762 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
762 LV->replaceKillInstruction(Op.getReg(), *OldMI, *NewMI);
763763 }
764764 }
765765 transferDeadCC(OldMI, NewMI);
27122712 addRegReg(MIB, leaInReg, true, leaInReg2, true);
27132713 }
27142714 if (LV && isKill2 && InsMI2)
2715 LV->replaceKillInstruction(Src2, &MI, InsMI2);
2715 LV->replaceKillInstruction(Src2, MI, *InsMI2);
27162716 break;
27172717 }
27182718 }
27282728 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
27292729 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
27302730 if (isKill)
2731 LV->replaceKillInstruction(Src, &MI, InsMI);
2731 LV->replaceKillInstruction(Src, MI, *InsMI);
27322732 if (isDead)
2733 LV->replaceKillInstruction(Dest, &MI, ExtMI);
2733 LV->replaceKillInstruction(Dest, MI, *ExtMI);
27342734 }
27352735
27362736 return ExtMI;
29432943 NewMI->getOperand(3).setIsUndef(isUndef2);
29442944
29452945 if (LV && Src2.isKill())
2946 LV->replaceKillInstruction(SrcReg2, &MI, NewMI);
2946 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
29472947 break;
29482948 }
29492949 case X86::ADD16rr:
29652965 NewMI->getOperand(3).setIsUndef(isUndef2);
29662966
29672967 if (LV && isKill2)
2968 LV->replaceKillInstruction(Src2, &MI, NewMI);
2968 LV->replaceKillInstruction(Src2, MI, *NewMI);
29692969 break;
29702970 }
29712971 case X86::ADD64ri32:
30213021
30223022 if (LV) { // Update live variables
30233023 if (Src.isKill())
3024 LV->replaceKillInstruction(Src.getReg(), &MI, NewMI);
3024 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
30253025 if (Dest.isDead())
3026 LV->replaceKillInstruction(Dest.getReg(), &MI, NewMI);
3026 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
30273027 }
30283028
30293029 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst