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[InstSimplify] allow or-of-icmps folds with vector splat constants git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282592 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 3 years ago
2 changed file(s) with 17 addition(s) and 44 deletion(s). Raw diff Collapse all Expand all
16861686 if (Value *X = simplifyUnsignedRangeCheck(Op0, Op1, /*IsAnd=*/false))
16871687 return X;
16881688
1689 // FIXME: Use m_APInt to allow vector splat matches.
1689 // (icmp (add V, C0), C1) | (icmp V, C0)
16901690 ICmpInst::Predicate Pred0, Pred1;
1691 ConstantInt *CI1, *CI2;
1691 const APInt *C0, *C1;
16921692 Value *V;
1693 if (!match(Op0, m_ICmp(Pred0, m_Add(m_Value(V), m_ConstantInt(CI1)),
1694 m_ConstantInt(CI2))))
1693 if (!match(Op0, m_ICmp(Pred0, m_Add(m_Value(V), m_APInt(C0)), m_APInt(C1))))
16951694 return nullptr;
16961695
1697 if (!match(Op1, m_ICmp(Pred1, m_Specific(V), m_Specific(CI1))))
1696 if (!match(Op1, m_ICmp(Pred1, m_Specific(V), m_Value())))
16981697 return nullptr;
16991698
1699 auto *AddInst = cast(Op0->getOperand(0));
1700 if (AddInst->getOperand(1) != Op1->getOperand(1))
1701 return nullptr;
1702
17001703 Type *ITy = Op0->getType();
1701
1702 auto *AddInst = cast(Op0->getOperand(0));
17031704 bool isNSW = AddInst->hasNoSignedWrap();
17041705 bool isNUW = AddInst->hasNoUnsignedWrap();
17051706
1706 const APInt &CI1V = CI1->getValue();
1707 const APInt &CI2V = CI2->getValue();
1708 const APInt Delta = CI2V - CI1V;
1709 if (CI1V.isStrictlyPositive()) {
1707 const APInt Delta = *C1 - *C0;
1708 if (C0->isStrictlyPositive()) {
17101709 if (Delta == 2) {
17111710 if (Pred0 == ICmpInst::ICMP_UGE && Pred1 == ICmpInst::ICMP_SLE)
17121711 return getTrue(ITy);
17201719 return getTrue(ITy);
17211720 }
17221721 }
1723 if (CI1V.getBoolValue() && isNUW) {
1722 if (C0->getBoolValue() && isNUW) {
17241723 if (Delta == 2)
17251724 if (Pred0 == ICmpInst::ICMP_UGE && Pred1 == ICmpInst::ICMP_ULE)
17261725 return getTrue(ITy);
169169 ret <2 x i1> %cmp
170170 }
171171
172 ; FIXME: Vector splats should fold the same way as scalars in the next 6 pairs of tests.
173
174172 define i1 @or_of_icmps0(i32 %b) {
175173 ; CHECK-LABEL: @or_of_icmps0(
176174 ; CHECK-NEXT: ret i1 true
184182
185183 define <2 x i1> @or_of_icmps0_vec(<2 x i32> %b) {
186184 ; CHECK-LABEL: @or_of_icmps0_vec(
187 ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> %b,
188 ; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <2 x i32> [[TMP1]],
189 ; CHECK-NEXT: [[CMP3:%.*]] = icmp sle <2 x i32> %b,
190 ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP2]], [[CMP:%.*]]3
191 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
185 ; CHECK-NEXT: ret <2 x i1>
192186 ;
193187 %1 = add <2 x i32> %b,
194188 %2 = icmp uge <2 x i32> %1,
210204
211205 define <2 x i1> @or_of_icmps1_vec(<2 x i32> %b) {
212206 ; CHECK-LABEL: @or_of_icmps1_vec(
213 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> %b,
214 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sge <2 x i32> [[TMP1]],
215 ; CHECK-NEXT: [[CMP3:%.*]] = icmp sle <2 x i32> %b,
216 ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP2]], [[CMP:%.*]]3
217 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
207 ; CHECK-NEXT: ret <2 x i1>
218208 ;
219209 %1 = add nsw <2 x i32> %b,
220210 %2 = icmp sge <2 x i32> %1,
236226
237227 define <2 x i1> @or_of_icmps2_vec(<2 x i32> %b) {
238228 ; CHECK-LABEL: @or_of_icmps2_vec(
239 ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> %b,
240 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt <2 x i32> [[TMP1]],
241 ; CHECK-NEXT: [[CMP3:%.*]] = icmp sle <2 x i32> %b,
242 ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP2]], [[CMP:%.*]]3
243 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
229 ; CHECK-NEXT: ret <2 x i1>
244230 ;
245231 %1 = add <2 x i32> %b,
246232 %2 = icmp ugt <2 x i32> %1,
262248
263249 define <2 x i1> @or_of_icmps3_vec(<2 x i32> %b) {
264250 ; CHECK-LABEL: @or_of_icmps3_vec(
265 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> %b,
266 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i32> [[TMP1]],
267 ; CHECK-NEXT: [[CMP3:%.*]] = icmp sle <2 x i32> %b,
268 ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP2]], [[CMP:%.*]]3
269 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
251 ; CHECK-NEXT: ret <2 x i1>
270252 ;
271253 %1 = add nsw <2 x i32> %b,
272254 %2 = icmp sgt <2 x i32> %1,
288270
289271 define <2 x i1> @or_of_icmps4_vec(<2 x i32> %b) {
290272 ; CHECK-LABEL: @or_of_icmps4_vec(
291 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw <2 x i32> %b,
292 ; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <2 x i32> [[TMP1]],
293 ; CHECK-NEXT: [[CMP3:%.*]] = icmp ule <2 x i32> %b,
294 ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP2]], [[CMP:%.*]]3
295 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
273 ; CHECK-NEXT: ret <2 x i1>
296274 ;
297275 %1 = add nuw <2 x i32> %b,
298276 %2 = icmp uge <2 x i32> %1,
314292
315293 define <2 x i1> @or_of_icmps5_vec(<2 x i32> %b) {
316294 ; CHECK-LABEL: @or_of_icmps5_vec(
317 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw <2 x i32> %b,
318 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt <2 x i32> [[TMP1]],
319 ; CHECK-NEXT: [[CMP3:%.*]] = icmp ule <2 x i32> %b,
320 ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP2]], [[CMP:%.*]]3
321 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
295 ; CHECK-NEXT: ret <2 x i1>
322296 ;
323297 %1 = add nuw <2 x i32> %b,
324298 %2 = icmp ugt <2 x i32> %1,