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Merging r321791 and r321862: ------------------------------------------------------------------------ r321791 | sam_parker | 2018-01-04 01:42:27 -0800 (Thu, 04 Jan 2018) | 4 lines [X86] Codegen test for PR37563 Adding test to ease review of D41628. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r321862 | sam_parker | 2018-01-05 00:47:23 -0800 (Fri, 05 Jan 2018) | 10 lines [DAGCombine] Fix for PR37563 While searching for loads to be narrowed, equal sized loads were not added to the list, resulting in anyext loads not being converted to zext loads. https://bugs.llvm.org/show_bug.cgi?id=35763 Differential Revision: https://reviews.llvm.org/D41628 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322671 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 years ago
3 changed file(s) with 59 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
38413841 EVT ExtVT;
38423842 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
38433843 isLegalNarrowLoad(Load, ISD::ZEXTLOAD, ExtVT)) {
3844 // Only add this load if we can make it more narrow.
3845 if (ExtVT.bitsLT(Load->getMemoryVT()))
3844
3845 // ZEXTLOAD is already small enough.
3846 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
3847 ExtVT.bitsGE(Load->getMemoryVT()))
3848 continue;
3849
3850 // Use LE to convert equal sized loads to zext.
3851 if (ExtVT.bitsLE(Load->getMemoryVT()))
38463852 Loads.insert(Load);
3853
38473854 continue;
38483855 }
38493856 return false;
38983905 if (Loads.size() == 0)
38993906 return false;
39003907
3908 DEBUG(dbgs() << "Backwards propagate AND: "; N->dump());
39013909 SDValue MaskOp = N->getOperand(1);
39023910
39033911 // If it exists, fixup the single node we allow in the tree that needs
39043912 // masking.
39053913 if (FixupNode) {
3914 DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump());
39063915 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
39073916 FixupNode->getValueType(0),
39083917 SDValue(FixupNode, 0), MaskOp);
39273936
39283937 // Create narrow loads.
39293938 for (auto *Load : Loads) {
3939 DEBUG(dbgs() << "Propagate AND back to: "; Load->dump());
39303940 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
39313941 SDValue(Load, 0), MaskOp);
39323942 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
851851 ; ARM: @ %bb.0: @ %entry
852852 ; ARM-NEXT: ldrb r0, [r0]
853853 ; ARM-NEXT: uxtb r2, r2
854 ; ARM-NEXT: and r0, r0, r1
855 ; ARM-NEXT: uxtb r1, r0
854 ; ARM-NEXT: and r1, r0, r1
856855 ; ARM-NEXT: mov r0, #0
857856 ; ARM-NEXT: cmp r1, r2
858857 ; ARM-NEXT: movweq r0, #1
862861 ; ARMEB: @ %bb.0: @ %entry
863862 ; ARMEB-NEXT: ldrb r0, [r0]
864863 ; ARMEB-NEXT: uxtb r2, r2
865 ; ARMEB-NEXT: and r0, r0, r1
866 ; ARMEB-NEXT: uxtb r1, r0
864 ; ARMEB-NEXT: and r1, r0, r1
867865 ; ARMEB-NEXT: mov r0, #0
868866 ; ARMEB-NEXT: cmp r1, r2
869867 ; ARMEB-NEXT: movweq r0, #1
871869 ;
872870 ; THUMB1-LABEL: test6:
873871 ; THUMB1: @ %bb.0: @ %entry
874 ; THUMB1-NEXT: ldrb r0, [r0]
875 ; THUMB1-NEXT: ands r0, r1
876 ; THUMB1-NEXT: uxtb r3, r0
872 ; THUMB1-NEXT: ldrb r3, [r0]
873 ; THUMB1-NEXT: ands r3, r1
877874 ; THUMB1-NEXT: uxtb r2, r2
878875 ; THUMB1-NEXT: movs r0, #1
879876 ; THUMB1-NEXT: movs r1, #0
888885 ; THUMB2: @ %bb.0: @ %entry
889886 ; THUMB2-NEXT: ldrb r0, [r0]
890887 ; THUMB2-NEXT: uxtb r2, r2
891 ; THUMB2-NEXT: ands r0, r1
892 ; THUMB2-NEXT: uxtb r1, r0
888 ; THUMB2-NEXT: ands r1, r0
893889 ; THUMB2-NEXT: movs r0, #0
894890 ; THUMB2-NEXT: cmp r1, r2
895891 ; THUMB2-NEXT: it eq
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s
2
3 %struct.S = type <{ i16, i24, [5 x i8], i8, i16, [2 x i8] }>
4
5 @z = global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
6 @tf_3_var_136 = global i64 0, align 8
7 @.str = private unnamed_addr constant [6 x i8] c"%llu\0A\00", align 1
8
9 define void @PR35763() {
10 ; CHECK-LABEL: PR35763:
11 ; CHECK: # %bb.0: # %entry
12 ; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
13 ; CHECK-NEXT: movzwl z+{{.*}}(%rip), %ecx
14 ; CHECK-NEXT: orl %eax, %ecx
15 ; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
16 ; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
17 ; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
18 ; CHECK-NEXT: shlq $32, %rcx
19 ; CHECK-NEXT: orq %rax, %rcx
20 ; CHECK-NEXT: movabsq $1090921758719, %rax # imm = 0xFE0000FFFF
21 ; CHECK-NEXT: andq %rcx, %rax
22 ; CHECK-NEXT: movl %eax, z+{{.*}}(%rip)
23 ; CHECK-NEXT: shrq $32, %rax
24 ; CHECK-NEXT: movb %al, z+{{.*}}(%rip)
25 ; CHECK-NEXT: retq
26 entry:
27 %0 = load i16, i16* getelementptr inbounds (%struct.S, %struct.S* bitcast ({ i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] }* @z to %struct.S*), i32 0, i32 0), align 8
28 %conv = sext i16 %0 to i32
29 %bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.S, %struct.S* bitcast ({ i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] }* @z to %struct.S*), i32 0, i32 1) to i32*), align 2
30 %bf.clear = and i32 %bf.load, 2097151
31 %bf.cast = zext i32 %bf.clear to i64
32 %conv1 = trunc i64 %bf.cast to i32
33 %or = or i32 %conv, %conv1
34 %conv2 = trunc i32 %or to i16
35 %conv3 = zext i16 %conv2 to i64
36 store i64 %conv3, i64* @tf_3_var_136, align 8
37 %bf.load4 = load i40, i40* bitcast ([5 x i8]* getelementptr inbounds (%struct.S, %struct.S* bitcast ({ i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] }* @z to %struct.S*), i32 0, i32 2) to i40*), align 2
38 %bf.clear5 = and i40 %bf.load4, -8589869057
39 store i40 %bf.clear5, i40* bitcast ([5 x i8]* getelementptr inbounds (%struct.S, %struct.S* bitcast ({ i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] }* @z to %struct.S*), i32 0, i32 2) to i40*), align 2
40 ret void
41 }