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Merging r309302: ------------------------------------------------------------------------ r309302 | rksimon | 2017-07-27 11:15:54 -0700 (Thu, 27 Jul 2017) | 3 lines [SelectionDAG] Improve DAGTypeLegalizer::convertMask assertion (PR33960) Improve DAGTypeLegalizer::convertMask's isSETCCorConvertedSETCC assertion to properly check for any mixture of SETCC or BUILD_VECTOR of constants, or a logical mask op of them. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@309348 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 3 years ago
2 changed file(s) with 48 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
29642964 else if (N.getOpcode() == ISD::SIGN_EXTEND)
29652965 N = N.getOperand(0);
29662966
2967 return (N.getOpcode() == ISD::SETCC);
2967 if (isLogicalMaskOp(N.getOpcode()))
2968 return isSETCCorConvertedSETCC(N.getOperand(0)) &&
2969 isSETCCorConvertedSETCC(N.getOperand(1));
2970
2971 return (N.getOpcode() == ISD::SETCC ||
2972 ISD::isBuildVectorOfConstantSDNodes(N.getNode()));
29682973 }
29692974 #endif
29702975
29722977 // to ToMaskVT if needed with vector extension or truncation.
29732978 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
29742979 EVT ToMaskVT) {
2975 LLVMContext &Ctx = *DAG.getContext();
2976
29772980 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
2978 unsigned InMaskOpc = InMask->getOpcode();
2979
29802981 // FIXME: This code seems to be too restrictive, we might consider
29812982 // generalizing it or dropping it.
2982 assert((InMaskOpc == ISD::SETCC ||
2983 ISD::isBuildVectorOfConstantSDNodes(InMask.getNode()) ||
2984 (isLogicalMaskOp(InMaskOpc) &&
2985 isSETCCorConvertedSETCC(InMask->getOperand(0)) &&
2986 isSETCCorConvertedSETCC(InMask->getOperand(1)))) &&
2987 "Unexpected mask argument.");
2983 assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.");
29882984
29892985 // Make a new Mask node, with a legal result VT.
29902986 SmallVector Ops;
29912987 for (unsigned i = 0; i < InMask->getNumOperands(); ++i)
29922988 Ops.push_back(InMask->getOperand(i));
2993 SDValue Mask = DAG.getNode(InMaskOpc, SDLoc(InMask), MaskVT, Ops);
2989 SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
29942990
29952991 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
29962992 // extend or truncate is needed.
2993 LLVMContext &Ctx = *DAG.getContext();
29972994 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
29982995 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
29992996 if (MaskScalarBits < ToMaskScalBits) {
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X86
2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
3
4 @b = external local_unnamed_addr global i32, align 4
5
6 define void @PR33960() {
7 ; X86-LABEL: PR33960:
8 ; X86: # BB#0: # %entry
9 ; X86-NEXT: movl $0, b
10 ; X86-NEXT: retl
11 ;
12 ; X64-LABEL: PR33960:
13 ; X64: # BB#0: # %entry
14 ; X64-NEXT: movl $0, {{.*}}(%rip)
15 ; X64-NEXT: retq
16 entry:
17 %tmp = insertelement <4 x i32> , i32 -2, i32 3
18 %predphi26 = insertelement <4 x i32> %tmp, i32 -7, i32 0
19 %tmp1 = trunc <4 x i32> %predphi26 to <4 x i16>
20 %tmp2 = icmp eq <4 x i16> %tmp1, zeroinitializer
21 %tmp3 = icmp eq <4 x i32> undef, zeroinitializer
22 %tmp4 = and <4 x i1> %tmp2, %tmp3
23 %predphi17 = select <4 x i1> %tmp4, <4 x i32> undef, <4 x i32> zeroinitializer
24 %tmp5 = shl <4 x i32> %predphi17,
25 %tmp6 = ashr exact <4 x i32> %tmp5,
26 %tmp7 = or <4 x i32> %tmp6, undef
27 %tmp8 = or <4 x i32> undef, %tmp7
28 %tmp9 = or <4 x i32> undef, %tmp8
29 %tmp10 = or <4 x i32> undef, %tmp9
30 %tmp11 = or <4 x i32> undef, %tmp10
31 %tmp12 = or <4 x i32> undef, %tmp11
32 %bin.rdx = or <4 x i32> %tmp12, undef
33 %bin.rdx19 = or <4 x i32> %bin.rdx, undef
34 %tmp13 = extractelement <4 x i32> %bin.rdx19, i32 0
35 %or = or i32 0, %tmp13
36 store i32 %or, i32* @b, align 4
37 ret void
38 }