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[Hexagon] Add an early if-conversion pass git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249423 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 4 years ago
9 changed file(s) with 1711 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
1717 HexagonCFGOptimizer.cpp
1818 HexagonCommonGEP.cpp
1919 HexagonCopyToCombine.cpp
20 HexagonEarlyIfConv.cpp
2021 HexagonExpandCondsets.cpp
2122 HexagonExpandPredSpillCode.cpp
2223 HexagonFixupHwLoops.cpp
0 //===--- HexagonEarlyIfConv.cpp -------------------------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements a Hexagon-specific if-conversion pass that runs on the
10 // SSA form.
11 // In SSA it is not straightforward to represent instructions that condi-
12 // tionally define registers, since a conditionally-defined register may
13 // only be used under the same condition on which the definition was based.
14 // To avoid complications of this nature, this patch will only generate
15 // predicated stores, and speculate other instructions from the "if-conver-
16 // ted" block.
17 // The code will recognize CFG patterns where a block with a conditional
18 // branch "splits" into a "true block" and a "false block". Either of these
19 // could be omitted (in case of a triangle, for example).
20 // If after conversion of the side block(s) the CFG allows it, the resul-
21 // ting blocks may be merged. If the "join" block contained PHI nodes, they
22 // will be replaced with MUX (or MUX-like) instructions to maintain the
23 // semantics of the PHI.
24 //
25 // Example:
26 //
27 // %vreg40 = L2_loadrub_io %vreg39, 1
28 // %vreg41 = S2_tstbit_i %vreg40, 0
29 // J2_jumpt %vreg41, , %PC
30 // J2_jump , %PC
31 // Successors according to CFG: BB#4(62) BB#5(62)
32 //
33 // BB#4: derived from LLVM BB %if.then
34 // Predecessors according to CFG: BB#3
35 // %vreg11 = A2_addp %vreg6, %vreg10
36 // S2_storerd_io %vreg32, 16, %vreg11
37 // Successors according to CFG: BB#5
38 //
39 // BB#5: derived from LLVM BB %if.end
40 // Predecessors according to CFG: BB#3 BB#4
41 // %vreg12 = PHI %vreg6, , %vreg11,
42 // %vreg13 = A2_addp %vreg7, %vreg12
43 // %vreg42 = C2_cmpeqi %vreg9, 10
44 // J2_jumpf %vreg42, , %PC
45 // J2_jump , %PC
46 // Successors according to CFG: BB#6(4) BB#3(124)
47 //
48 // would become:
49 //
50 // %vreg40 = L2_loadrub_io %vreg39, 1
51 // %vreg41 = S2_tstbit_i %vreg40, 0
52 // spec-> %vreg11 = A2_addp %vreg6, %vreg10
53 // pred-> S2_pstorerdf_io %vreg41, %vreg32, 16, %vreg11
54 // %vreg46 = MUX64_rr %vreg41, %vreg6, %vreg11
55 // %vreg13 = A2_addp %vreg7, %vreg46
56 // %vreg42 = C2_cmpeqi %vreg9, 10
57 // J2_jumpf %vreg42, , %PC
58 // J2_jump , %PC
59 // Successors according to CFG: BB#6 BB#3
60
61 #define DEBUG_TYPE "hexagon-eif"
62
63 #include "llvm/ADT/DenseSet.h"
64 #include "llvm/ADT/SetVector.h"
65 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
66 #include "llvm/CodeGen/MachineDominators.h"
67 #include "llvm/CodeGen/MachineFunctionPass.h"
68 #include "llvm/CodeGen/MachineInstrBuilder.h"
69 #include "llvm/CodeGen/MachineLoopInfo.h"
70 #include "llvm/CodeGen/MachineRegisterInfo.h"
71 #include "llvm/CodeGen/Passes.h"
72 #include "llvm/Support/CommandLine.h"
73 #include "llvm/Support/Debug.h"
74 #include "llvm/Support/raw_ostream.h"
75 #include "llvm/Target/TargetInstrInfo.h"
76 #include "llvm/Target/TargetMachine.h"
77 #include "HexagonTargetMachine.h"
78
79 #include
80 #include
81 #include
82
83 using namespace llvm;
84
85 static cl::opt EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
86 cl::init(false), cl::ZeroOrMore, cl::desc("Enable branch probability info"));
87
88 namespace llvm {
89 FunctionPass *createHexagonEarlyIfConversion();
90 void initializeHexagonEarlyIfConversionPass(PassRegistry& Registry);
91 }
92
93 namespace {
94 cl::opt SizeLimit("eif-limit", cl::init(6), cl::Hidden,
95 cl::ZeroOrMore, cl::desc("Size limit in Hexagon early if-conversion"));
96
97 struct PrintMB {
98 PrintMB(const MachineBasicBlock *B) : MB(B) {}
99 const MachineBasicBlock *MB;
100 };
101 raw_ostream &operator<< (raw_ostream &OS, const PrintMB &P) {
102 if (!P.MB)
103 return OS << "";
104 return OS << '#' << P.MB->getNumber();
105 }
106
107 struct FlowPattern {
108 FlowPattern() : SplitB(0), TrueB(0), FalseB(0), JoinB(0), PredR(0) {}
109 FlowPattern(MachineBasicBlock *B, unsigned PR, MachineBasicBlock *TB,
110 MachineBasicBlock *FB, MachineBasicBlock *JB)
111 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {}
112
113 MachineBasicBlock *SplitB;
114 MachineBasicBlock *TrueB, *FalseB, *JoinB;
115 unsigned PredR;
116 };
117 struct PrintFP {
118 PrintFP(const FlowPattern &P, const TargetRegisterInfo &T)
119 : FP(P), TRI(T) {}
120 const FlowPattern &FP;
121 const TargetRegisterInfo &TRI;
122 friend raw_ostream &operator<< (raw_ostream &OS, const PrintFP &P);
123 };
124 raw_ostream &operator<<(raw_ostream &OS,
125 const PrintFP &P) LLVM_ATTRIBUTE_UNUSED;
126 raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) {
127 OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
128 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
129 << ", TrueB:" << PrintMB(P.FP.TrueB) << ", FalseB:"
130 << PrintMB(P.FP.FalseB)
131 << ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
132 return OS;
133 }
134
135 class HexagonEarlyIfConversion : public MachineFunctionPass {
136 public:
137 static char ID;
138 HexagonEarlyIfConversion() : MachineFunctionPass(ID),
139 TII(0), TRI(0), MFN(0), MRI(0), MDT(0), MLI(0) {
140 initializeHexagonEarlyIfConversionPass(*PassRegistry::getPassRegistry());
141 }
142 const char *getPassName() const override {
143 return "Hexagon early if conversion";
144 }
145 void getAnalysisUsage(AnalysisUsage &AU) const override {
146 AU.addRequired();
147 AU.addRequired();
148 AU.addPreserved();
149 AU.addRequired();
150 MachineFunctionPass::getAnalysisUsage(AU);
151 }
152 bool runOnMachineFunction(MachineFunction &MF) override;
153
154 private:
155 typedef DenseSet BlockSetType;
156
157 bool isPreheader(const MachineBasicBlock *B) const;
158 bool matchFlowPattern(MachineBasicBlock *B, MachineLoop *L,
159 FlowPattern &FP);
160 bool visitBlock(MachineBasicBlock *B, MachineLoop *L);
161 bool visitLoop(MachineLoop *L);
162
163 bool hasEHLabel(const MachineBasicBlock *B) const;
164 bool hasUncondBranch(const MachineBasicBlock *B) const;
165 bool isValidCandidate(const MachineBasicBlock *B) const;
166 bool usesUndefVReg(const MachineInstr *MI) const;
167 bool isValid(const FlowPattern &FP) const;
168 unsigned countPredicateDefs(const MachineBasicBlock *B) const;
169 unsigned computePhiCost(MachineBasicBlock *B) const;
170 bool isProfitable(const FlowPattern &FP) const;
171 bool isPredicableStore(const MachineInstr *MI) const;
172 bool isSafeToSpeculate(const MachineInstr *MI) const;
173
174 unsigned getCondStoreOpcode(unsigned Opc, bool IfTrue) const;
175 void predicateInstr(MachineBasicBlock *ToB, MachineBasicBlock::iterator At,
176 MachineInstr *MI, unsigned PredR, bool IfTrue);
177 void predicateBlockNB(MachineBasicBlock *ToB,
178 MachineBasicBlock::iterator At, MachineBasicBlock *FromB,
179 unsigned PredR, bool IfTrue);
180
181 void updatePhiNodes(MachineBasicBlock *WhereB, const FlowPattern &FP);
182 void convert(const FlowPattern &FP);
183
184 void removeBlock(MachineBasicBlock *B);
185 void eliminatePhis(MachineBasicBlock *B);
186 void replacePhiEdges(MachineBasicBlock *OldB, MachineBasicBlock *NewB);
187 void mergeBlocks(MachineBasicBlock *PredB, MachineBasicBlock *SuccB);
188 void simplifyFlowGraph(const FlowPattern &FP);
189
190 const TargetInstrInfo *TII;
191 const TargetRegisterInfo *TRI;
192 MachineFunction *MFN;
193 MachineRegisterInfo *MRI;
194 MachineDominatorTree *MDT;
195 MachineLoopInfo *MLI;
196 BlockSetType Deleted;
197 const MachineBranchProbabilityInfo *MBPI;
198 };
199
200 char HexagonEarlyIfConversion::ID = 0;
201 }
202
203 INITIALIZE_PASS(HexagonEarlyIfConversion, "hexagon-eif",
204 "Hexagon early if conversion", false, false)
205
206 bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const {
207 if (B->succ_size() != 1)
208 return false;
209 MachineBasicBlock *SB = *B->succ_begin();
210 MachineLoop *L = MLI->getLoopFor(SB);
211 return L && SB == L->getHeader();
212 }
213
214
215 bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
216 MachineLoop *L, FlowPattern &FP) {
217 DEBUG(dbgs() << "Checking flow pattern at BB#" << B->getNumber() << "\n");
218
219 // Interested only in conditional branches, no .new, no new-value, etc.
220 // Check the terminators directly, it's easier than handling all responses
221 // from AnalyzeBranch.
222 MachineBasicBlock *TB = 0, *FB = 0;
223 MachineBasicBlock::const_iterator T1I = B->getFirstTerminator();
224 if (T1I == B->end())
225 return false;
226 unsigned Opc = T1I->getOpcode();
227 if (Opc != Hexagon::J2_jumpt && Opc != Hexagon::J2_jumpf)
228 return false;
229 unsigned PredR = T1I->getOperand(0).getReg();
230
231 // Get the layout successor, or 0 if B does not have one.
232 MachineFunction::iterator NextBI = std::next(MachineFunction::iterator(B));
233 MachineBasicBlock *NextB = (NextBI != MFN->end()) ? &*NextBI : 0;
234
235 MachineBasicBlock *T1B = T1I->getOperand(1).getMBB();
236 MachineBasicBlock::const_iterator T2I = std::next(T1I);
237 // The second terminator should be an unconditional branch.
238 assert(T2I == B->end() || T2I->getOpcode() == Hexagon::J2_jump);
239 MachineBasicBlock *T2B = (T2I == B->end()) ? NextB
240 : T2I->getOperand(0).getMBB();
241 if (T1B == T2B) {
242 // XXX merge if T1B == NextB, or convert branch to unconditional.
243 // mark as diamond with both sides equal?
244 return false;
245 }
246 // Loop could be null for both.
247 if (MLI->getLoopFor(T1B) != L || MLI->getLoopFor(T2B) != L)
248 return false;
249
250 // Record the true/false blocks in such a way that "true" means "if (PredR)",
251 // and "false" means "if (!PredR)".
252 if (Opc == Hexagon::J2_jumpt)
253 TB = T1B, FB = T2B;
254 else
255 TB = T2B, FB = T1B;
256
257 if (!MDT->properlyDominates(B, TB) || !MDT->properlyDominates(B, FB))
258 return false;
259
260 // Detect triangle first. In case of a triangle, one of the blocks TB/FB
261 // can fall through into the other, in other words, it will be executed
262 // in both cases. We only want to predicate the block that is executed
263 // conditionally.
264 unsigned TNP = TB->pred_size(), FNP = FB->pred_size();
265 unsigned TNS = TB->succ_size(), FNS = FB->succ_size();
266
267 // A block is predicable if it has one predecessor (it must be B), and
268 // it has a single successor. In fact, the block has to end either with
269 // an unconditional branch (which can be predicated), or with a fall-
270 // through.
271 bool TOk = (TNP == 1) && (TNS == 1);
272 bool FOk = (FNP == 1) && (FNS == 1);
273
274 // If neither is predicable, there is nothing interesting.
275 if (!TOk && !FOk)
276 return false;
277
278 MachineBasicBlock *TSB = (TNS > 0) ? *TB->succ_begin() : 0;
279 MachineBasicBlock *FSB = (FNS > 0) ? *FB->succ_begin() : 0;
280 MachineBasicBlock *JB = 0;
281
282 if (TOk) {
283 if (FOk) {
284 if (TSB == FSB)
285 JB = TSB;
286 // Diamond: "if (P) then TB; else FB;".
287 } else {
288 // TOk && !FOk
289 if (TSB == FB) {
290 JB = FB;
291 FB = 0;
292 }
293 }
294 } else {
295 // !TOk && FOk (at least one must be true by now).
296 if (FSB == TB) {
297 JB = TB;
298 TB = 0;
299 }
300 }
301 // Don't try to predicate loop preheaders.
302 if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) {
303 DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB)
304 << " is a loop preheader. Skipping.\n");
305 return false;
306 }
307
308 FP = FlowPattern(B, PredR, TB, FB, JB);
309 DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n");
310 return true;
311 }
312
313
314 // KLUDGE: HexagonInstrInfo::AnalyzeBranch won't work on a block that
315 // contains EH_LABEL.
316 bool HexagonEarlyIfConversion::hasEHLabel(const MachineBasicBlock *B) const {
317 for (auto &I : *B)
318 if (I.isEHLabel())
319 return true;
320 return false;
321 }
322
323
324 // KLUDGE: HexagonInstrInfo::AnalyzeBranch may be unable to recognize
325 // that a block can never fall-through.
326 bool HexagonEarlyIfConversion::hasUncondBranch(const MachineBasicBlock *B)
327 const {
328 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
329 while (I != E) {
330 if (I->isBarrier())
331 return true;
332 ++I;
333 }
334 return false;
335 }
336
337
338 bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
339 const {
340 if (!B)
341 return true;
342 if (B->isEHPad() || B->hasAddressTaken())
343 return false;
344 if (B->succ_size() == 0)
345 return false;
346
347 for (auto &MI : *B) {
348 if (MI.isDebugValue())
349 continue;
350 if (MI.isConditionalBranch())
351 return false;
352 unsigned Opc = MI.getOpcode();
353 bool IsJMP = (Opc == Hexagon::J2_jump);
354 if (!isPredicableStore(&MI) && !IsJMP && !isSafeToSpeculate(&MI))
355 return false;
356 // Look for predicate registers defined by this instruction. It's ok
357 // to speculate such an instruction, but the predicate register cannot
358 // be used outside of this block (or else it won't be possible to
359 // update the use of it after predication). PHI uses will be updated
360 // to use a result of a MUX, and a MUX cannot be created for predicate
361 // registers.
362 for (ConstMIOperands MO(&MI); MO.isValid(); ++MO) {
363 if (!MO->isReg() || !MO->isDef())
364 continue;
365 unsigned R = MO->getReg();
366 if (!TargetRegisterInfo::isVirtualRegister(R))
367 continue;
368 if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass)
369 continue;
370 for (auto U = MRI->use_begin(R); U != MRI->use_end(); ++U)
371 if (U->getParent()->isPHI())
372 return false;
373 }
374 }
375 return true;
376 }
377
378
379 bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const {
380 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
381 if (!MO->isReg() || !MO->isUse())
382 continue;
383 unsigned R = MO->getReg();
384 if (!TargetRegisterInfo::isVirtualRegister(R))
385 continue;
386 const MachineInstr *DefI = MRI->getVRegDef(R);
387 // "Undefined" virtual registers are actually defined via IMPLICIT_DEF.
388 assert(DefI && "Expecting a reaching def in MRI");
389 if (DefI->isImplicitDef())
390 return true;
391 }
392 return false;
393 }
394
395
396 bool HexagonEarlyIfConversion::isValid(const FlowPattern &FP) const {
397 if (hasEHLabel(FP.SplitB)) // KLUDGE: see function definition
398 return false;
399 if (FP.TrueB && !isValidCandidate(FP.TrueB))
400 return false;
401 if (FP.FalseB && !isValidCandidate(FP.FalseB))
402 return false;
403 // Check the PHIs in the join block. If any of them use a register
404 // that is defined as IMPLICIT_DEF, do not convert this. This can
405 // legitimately happen if one side of the split never executes, but
406 // the compiler is unable to prove it. That side may then seem to
407 // provide an "undef" value to the join block, however it will never
408 // execute at run-time. If we convert this case, the "undef" will
409 // be used in a MUX instruction, and that may seem like actually
410 // using an undefined value to other optimizations. This could lead
411 // to trouble further down the optimization stream, cause assertions
412 // to fail, etc.
413 if (FP.JoinB) {
414 const MachineBasicBlock &B = *FP.JoinB;
415 for (auto &MI : B) {
416 if (!MI.isPHI())
417 break;
418 if (usesUndefVReg(&MI))
419 return false;
420 unsigned DefR = MI.getOperand(0).getReg();
421 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
422 if (RC == &Hexagon::PredRegsRegClass)
423 return false;
424 }
425 }
426 return true;
427 }
428
429
430 unsigned HexagonEarlyIfConversion::computePhiCost(MachineBasicBlock *B) const {
431 assert(B->pred_size() <= 2);
432 if (B->pred_size() < 2)
433 return 0;
434
435 unsigned Cost = 0;
436 MachineBasicBlock::const_iterator I, E = B->getFirstNonPHI();
437 for (I = B->begin(); I != E; ++I) {
438 const MachineOperand &RO1 = I->getOperand(1);
439 const MachineOperand &RO3 = I->getOperand(3);
440 assert(RO1.isReg() && RO3.isReg());
441 // Must have a MUX if the phi uses a subregister.
442 if (RO1.getSubReg() != 0 || RO3.getSubReg() != 0) {
443 Cost++;
444 continue;
445 }
446 MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg());
447 MachineInstr *Def3 = MRI->getVRegDef(RO3.getReg());
448 if (!TII->isPredicable(Def1) || !TII->isPredicable(Def3))
449 Cost++;
450 }
451 return Cost;
452 }
453
454
455 unsigned HexagonEarlyIfConversion::countPredicateDefs(
456 const MachineBasicBlock *B) const {
457 unsigned PredDefs = 0;
458 for (auto &MI : *B) {
459 for (ConstMIOperands MO(&MI); MO.isValid(); ++MO) {
460 if (!MO->isReg() || !MO->isDef())
461 continue;
462 unsigned R = MO->getReg();
463 if (!TargetRegisterInfo::isVirtualRegister(R))
464 continue;
465 if (MRI->getRegClass(R) == &Hexagon::PredRegsRegClass)
466 PredDefs++;
467 }
468 }
469 return PredDefs;
470 }
471
472
473 bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const {
474 if (FP.TrueB && FP.FalseB) {
475
476 // Do not IfCovert if the branch is one sided.
477 if (MBPI) {
478 BranchProbability Prob(9, 10);
479 if (MBPI->getEdgeProbability(FP.SplitB, FP.TrueB) > Prob)
480 return false;
481 if (MBPI->getEdgeProbability(FP.SplitB, FP.FalseB) > Prob)
482 return false;
483 }
484
485 // If both sides are predicable, convert them if they join, and the
486 // join block has no other predecessors.
487 MachineBasicBlock *TSB = *FP.TrueB->succ_begin();
488 MachineBasicBlock *FSB = *FP.FalseB->succ_begin();
489 if (TSB != FSB)
490 return false;
491 if (TSB->pred_size() != 2)
492 return false;
493 }
494
495 // Calculate the total size of the predicated blocks.
496 // Assume instruction counts without branches to be the approximation of
497 // the code size. If the predicated blocks are smaller than a packet size,
498 // approximate the spare room in the packet that could be filled with the
499 // predicated/speculated instructions.
500 unsigned TS = 0, FS = 0, Spare = 0;
501 if (FP.TrueB) {
502 TS = std::distance(FP.TrueB->begin(), FP.TrueB->getFirstTerminator());
503 if (TS < HEXAGON_PACKET_SIZE)
504 Spare += HEXAGON_PACKET_SIZE-TS;
505 }
506 if (FP.FalseB) {
507 FS = std::distance(FP.FalseB->begin(), FP.FalseB->getFirstTerminator());
508 if (FS < HEXAGON_PACKET_SIZE)
509 Spare += HEXAGON_PACKET_SIZE-TS;
510 }
511 unsigned TotalIn = TS+FS;
512 DEBUG(dbgs() << "Total number of instructions to be predicated/speculated: "
513 << TotalIn << ", spare room: " << Spare << "\n");
514 if (TotalIn >= SizeLimit+Spare)
515 return false;
516
517 // Count the number of PHI nodes that will need to be updated (converted
518 // to MUX). Those can be later converted to predicated instructions, so
519 // they aren't always adding extra cost.
520 // KLUDGE: Also, count the number of predicate register definitions in
521 // each block. The scheduler may increase the pressure of these and cause
522 // expensive spills (e.g. bitmnp01).
523 unsigned TotalPh = 0;
524 unsigned PredDefs = countPredicateDefs(FP.SplitB);
525 if (FP.JoinB) {
526 TotalPh = computePhiCost(FP.JoinB);
527 PredDefs += countPredicateDefs(FP.JoinB);
528 } else {
529 if (FP.TrueB && FP.TrueB->succ_size() > 0) {
530 MachineBasicBlock *SB = *FP.TrueB->succ_begin();
531 TotalPh += computePhiCost(SB);
532 PredDefs += countPredicateDefs(SB);
533 }
534 if (FP.FalseB && FP.FalseB->succ_size() > 0) {
535 MachineBasicBlock *SB = *FP.FalseB->succ_begin();
536 TotalPh += computePhiCost(SB);
537 PredDefs += countPredicateDefs(SB);
538 }
539 }
540 DEBUG(dbgs() << "Total number of extra muxes from converted phis: "
541 << TotalPh << "\n");
542 if (TotalIn+TotalPh >= SizeLimit+Spare)
543 return false;
544
545 DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs << "\n");
546 if (PredDefs > 4)
547 return false;
548
549 return true;
550 }
551
552
553 bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
554 MachineLoop *L) {
555 bool Changed = false;
556
557 // Visit all dominated blocks from the same loop first, then process B.
558 MachineDomTreeNode *N = MDT->getNode(B);
559 typedef GraphTraits GTN;
560 // We will change CFG/DT during this traversal, so take precautions to
561 // avoid problems related to invalidated iterators. In fact, processing
562 // a child C of B cannot cause another child to be removed, but it can
563 // cause a new child to be added (which was a child of C before C itself
564 // was removed. This new child C, however, would have been processed
565 // prior to processing B, so there is no need to process it again.
566 // Simply keep a list of children of B, and traverse that list.
567 typedef SmallVector DTNodeVectType;
568 DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
569 for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
570 MachineBasicBlock *SB = (*I)->getBlock();
571 if (!Deleted.count(SB))
572 Changed |= visitBlock(SB, L);
573 }
574 // When walking down the dominator tree, we want to traverse through
575 // blocks from nested (other) loops, because they can dominate blocks
576 // that are in L. Skip the non-L blocks only after the tree traversal.
577 if (MLI->getLoopFor(B) != L)
578 return Changed;
579
580 FlowPattern FP;
581 if (!matchFlowPattern(B, L, FP))
582 return Changed;
583
584 if (!isValid(FP)) {
585 DEBUG(dbgs() << "Conversion is not valid\n");
586 return Changed;
587 }
588 if (!isProfitable(FP)) {
589 DEBUG(dbgs() << "Conversion is not profitable\n");
590 return Changed;
591 }
592
593 convert(FP);
594 simplifyFlowGraph(FP);
595 return true;
596 }
597
598
599 bool HexagonEarlyIfConversion::visitLoop(MachineLoop *L) {
600 MachineBasicBlock *HB = L ? L->getHeader() : 0;
601 DEBUG((L ? dbgs() << "Visiting loop H:" << PrintMB(HB)
602 : dbgs() << "Visiting function") << "\n");
603 bool Changed = false;
604 if (L) {
605 for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I)
606 Changed |= visitLoop(*I);
607 }
608
609 MachineBasicBlock *EntryB = GraphTraits::getEntryNode(MFN);
610 Changed |= visitBlock(L ? HB : EntryB, L);
611 return Changed;
612 }
613
614
615 bool HexagonEarlyIfConversion::isPredicableStore(const MachineInstr *MI)
616 const {
617 // Exclude post-increment stores. Those return a value, so we cannot
618 // predicate them.
619 unsigned Opc = MI->getOpcode();
620 using namespace Hexagon;
621 switch (Opc) {
622 // Store byte:
623 case S2_storerb_io: case S4_storerb_rr:
624 case S2_storerbabs: case S4_storeirb_io: case S2_storerbgp:
625 // Store halfword:
626 case S2_storerh_io: case S4_storerh_rr:
627 case S2_storerhabs: case S4_storeirh_io: case S2_storerhgp:
628 // Store upper halfword:
629 case S2_storerf_io: case S4_storerf_rr:
630 case S2_storerfabs: case S2_storerfgp:
631 // Store word:
632 case S2_storeri_io: case S4_storeri_rr:
633 case S2_storeriabs: case S4_storeiri_io: case S2_storerigp:
634 // Store doubleword:
635 case S2_storerd_io: case S4_storerd_rr:
636 case S2_storerdabs: case S2_storerdgp:
637 return true;
638 }
639 return false;
640 }
641
642
643 bool HexagonEarlyIfConversion::isSafeToSpeculate(const MachineInstr *MI)
644 const {
645 if (MI->mayLoad() || MI->mayStore())
646 return false;
647 if (MI->isCall() || MI->isBarrier() || MI->isBranch())
648 return false;
649 if (MI->hasUnmodeledSideEffects())
650 return false;
651
652 return true;
653 }
654
655
656 unsigned HexagonEarlyIfConversion::getCondStoreOpcode(unsigned Opc,
657 bool IfTrue) const {
658 // Exclude post-increment stores.
659 using namespace Hexagon;
660 switch (Opc) {
661 case S2_storerb_io:
662 return IfTrue ? S2_pstorerbt_io : S2_pstorerbf_io;
663 case S4_storerb_rr:
664 return IfTrue ? S4_pstorerbt_rr : S4_pstorerbf_rr;
665 case S2_storerbabs:
666 case S2_storerbgp:
667 return IfTrue ? S4_pstorerbt_abs : S4_pstorerbf_abs;
668 case S4_storeirb_io:
669 return IfTrue ? S4_storeirbt_io : S4_storeirbf_io;
670 case S2_storerh_io:
671 return IfTrue ? S2_pstorerht_io : S2_pstorerhf_io;
672 case S4_storerh_rr:
673 return IfTrue ? S4_pstorerht_rr : S4_pstorerhf_rr;
674 case S2_storerhabs:
675 case S2_storerhgp:
676 return IfTrue ? S4_pstorerht_abs : S4_pstorerhf_abs;
677 case S2_storerf_io:
678 return IfTrue ? S2_pstorerft_io : S2_pstorerff_io;
679 case S4_storerf_rr:
680 return IfTrue ? S4_pstorerft_rr : S4_pstorerff_rr;
681 case S2_storerfabs:
682 case S2_storerfgp:
683 return IfTrue ? S4_pstorerft_abs : S4_pstorerff_abs;
684 case S4_storeirh_io:
685 return IfTrue ? S4_storeirht_io : S4_storeirhf_io;
686 case S2_storeri_io:
687 return IfTrue ? S2_pstorerit_io : S2_pstorerif_io;
688 case S4_storeri_rr:
689 return IfTrue ? S4_pstorerit_rr : S4_pstorerif_rr;
690 case S2_storeriabs:
691 case S2_storerigp:
692 return IfTrue ? S4_pstorerit_abs : S4_pstorerif_abs;
693 case S4_storeiri_io:
694 return IfTrue ? S4_storeirit_io : S4_storeirif_io;
695 case S2_storerd_io:
696 return IfTrue ? S2_pstorerdt_io : S2_pstorerdf_io;
697 case S4_storerd_rr:
698 return IfTrue ? S4_pstorerdt_rr : S4_pstorerdf_rr;
699 case S2_storerdabs:
700 case S2_storerdgp:
701 return IfTrue ? S4_pstorerdt_abs : S4_pstorerdf_abs;
702 }
703 llvm_unreachable("Unexpected opcode");
704 return 0;
705 }
706
707
708 void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB,
709 MachineBasicBlock::iterator At, MachineInstr *MI,
710 unsigned PredR, bool IfTrue) {
711 DebugLoc DL;
712 if (At != ToB->end())
713 DL = At->getDebugLoc();
714 else if (!ToB->empty())
715 DL = ToB->back().getDebugLoc();
716
717 unsigned Opc = MI->getOpcode();
718
719 if (isPredicableStore(MI)) {
720 unsigned COpc = getCondStoreOpcode(Opc, IfTrue);
721 assert(COpc);
722 MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, TII->get(COpc))
723 .addReg(PredR);
724 for (MIOperands MO(MI); MO.isValid(); ++MO)
725 MIB.addOperand(*MO);
726
727 // Set memory references.
728 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
729 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
730 MIB.setMemRefs(MMOBegin, MMOEnd);
731
732 MI->eraseFromParent();
733 return;
734 }
735
736 if (Opc == Hexagon::J2_jump) {
737 MachineBasicBlock *TB = MI->getOperand(0).getMBB();
738 const MCInstrDesc &D = TII->get(IfTrue ? Hexagon::J2_jumpt
739 : Hexagon::J2_jumpf);
740 BuildMI(*ToB, At, DL, D)
741 .addReg(PredR)
742 .addMBB(TB);
743 MI->eraseFromParent();
744 return;
745 }
746
747 // Print the offending instruction unconditionally as we are about to
748 // abort.
749 dbgs() << *MI;
750 llvm_unreachable("Unexpected instruction");
751 }
752
753
754 // Predicate/speculate non-branch instructions from FromB into block ToB.
755 // Leave the branches alone, they will be handled later. Btw, at this point
756 // FromB should have at most one branch, and it should be unconditional.
757 void HexagonEarlyIfConversion::predicateBlockNB(MachineBasicBlock *ToB,
758 MachineBasicBlock::iterator At, MachineBasicBlock *FromB,
759 unsigned PredR, bool IfTrue) {
760 DEBUG(dbgs() << "Predicating block " << PrintMB(FromB) << "\n");
761 MachineBasicBlock::iterator End = FromB->getFirstTerminator();
762 MachineBasicBlock::iterator I, NextI;
763
764 for (I = FromB->begin(); I != End; I = NextI) {
765 assert(!I->isPHI());
766 NextI = std::next(I);
767 if (isSafeToSpeculate(&*I))
768 ToB->splice(At, FromB, I);
769 else
770 predicateInstr(ToB, At, &*I, PredR, IfTrue);
771 }
772 }
773
774
775 void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB,
776 const FlowPattern &FP) {
777 // Visit all PHI nodes in the WhereB block and generate MUX instructions
778 // in the split block. Update the PHI nodes with the values of the MUX.
779 auto NonPHI = WhereB->getFirstNonPHI();
780 for (auto I = WhereB->begin(); I != NonPHI; ++I) {
781 MachineInstr *PN = &*I;
782 // Registers and subregisters corresponding to TrueB, FalseB and SplitB.
783 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;
784 for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
785 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1);
786 if (BO.getMBB() == FP.SplitB)
787 SR = RO.getReg(), SSR = RO.getSubReg();
788 else if (BO.getMBB() == FP.TrueB)
789 TR = RO.getReg(), TSR = RO.getSubReg();
790 else if (BO.getMBB() == FP.FalseB)
791 FR = RO.getReg(), FSR = RO.getSubReg();
792 else
793 continue;
794 PN->RemoveOperand(i+1);
795 PN->RemoveOperand(i);
796 }
797 if (TR == 0)
798 TR = SR, TSR = SSR;
799 else if (FR == 0)
800 FR = SR, FSR = SSR;
801 assert(TR && FR);
802
803 using namespace Hexagon;
804 unsigned DR = PN->getOperand(0).getReg();
805 const TargetRegisterClass *RC = MRI->getRegClass(DR);
806 const MCInstrDesc &D = RC == &IntRegsRegClass ? TII->get(C2_mux)
807 : TII->get(MUX64_rr);
808
809 MachineBasicBlock::iterator MuxAt = FP.SplitB->getFirstTerminator();
810 DebugLoc DL;
811 if (MuxAt != FP.SplitB->end())
812 DL = MuxAt->getDebugLoc();
813 unsigned MuxR = MRI->createVirtualRegister(RC);
814 BuildMI(*FP.SplitB, MuxAt, DL, D, MuxR)
815 .addReg(FP.PredR)
816 .addReg(TR, 0, TSR)
817 .addReg(FR, 0, FSR);
818
819 PN->addOperand(MachineOperand::CreateReg(MuxR, false));
820 PN->addOperand(MachineOperand::CreateMBB(FP.SplitB));
821 }
822 }
823
824
825 void HexagonEarlyIfConversion::convert(const FlowPattern &FP) {
826 MachineBasicBlock *TSB = 0, *FSB = 0;
827 MachineBasicBlock::iterator OldTI = FP.SplitB->getFirstTerminator();
828 assert(OldTI != FP.SplitB->end());
829 DebugLoc DL = OldTI->getDebugLoc();
830
831 if (FP.TrueB) {
832 TSB = *FP.TrueB->succ_begin();
833 predicateBlockNB(FP.SplitB, OldTI, FP.TrueB, FP.PredR, true);
834 }
835 if (FP.FalseB) {
836 FSB = *FP.FalseB->succ_begin();
837 MachineBasicBlock::iterator At = FP.SplitB->getFirstTerminator();
838 predicateBlockNB(FP.SplitB, At, FP.FalseB, FP.PredR, false);
839 }
840
841 // Regenerate new terminators in the split block and update the successors.
842 // First, remember any information that may be needed later and remove the
843 // existing terminators/successors from the split block.
844 MachineBasicBlock *SSB = 0;
845 FP.SplitB->erase(OldTI, FP.SplitB->end());
846 while (FP.SplitB->succ_size() > 0) {
847 MachineBasicBlock *T = *FP.SplitB->succ_begin();
848 // It's possible that the split block had a successor that is not a pre-
849 // dicated block. This could only happen if there was only one block to
850 // be predicated. Example:
851 // split_b:
852 // if (p) jump true_b
853 // jump unrelated2_b
854 // unrelated1_b:
855 // ...
856 // unrelated2_b: ; can have other predecessors, so it's not "false_b"
857 // jump other_b
858 // true_b: ; only reachable from split_b, can be predicated
859 // ...
860 //
861 // Find this successor (SSB) if it exists.
862 if (T != FP.TrueB && T != FP.FalseB) {
863 assert(!SSB);
864 SSB = T;
865 }
866 FP.SplitB->removeSuccessor(FP.SplitB->succ_begin());
867 }
868
869 // Insert new branches and update the successors of the split block. This
870 // may create unconditional branches to the layout successor, etc., but
871 // that will be cleaned up later. For now, make sure that correct code is
872 // generated.
873 if (FP.JoinB) {
874 assert(!SSB || SSB == FP.JoinB);
875 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, TII->get(Hexagon::J2_jump))
876 .addMBB(FP.JoinB);
877 FP.SplitB->addSuccessor(FP.JoinB);
878 } else {
879 bool HasBranch = false;
880 if (TSB) {
881 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, TII->get(Hexagon::J2_jumpt))
882 .addReg(FP.PredR)
883 .addMBB(TSB);
884 FP.SplitB->addSuccessor(TSB);
885 HasBranch = true;
886 }
887 if (FSB) {
888 const MCInstrDesc &D = HasBranch ? TII->get(Hexagon::J2_jump)
889 : TII->get(Hexagon::J2_jumpf);
890 MachineInstrBuilder MIB = BuildMI(*FP.SplitB, FP.SplitB->end(), DL, D);
891 if (!HasBranch)
892 MIB.addReg(FP.PredR);
893 MIB.addMBB(FSB);
894 FP.SplitB->addSuccessor(FSB);
895 }
896 if (SSB) {
897 // This cannot happen if both TSB and FSB are set. [TF]SB are the
898 // successor blocks of the TrueB and FalseB (or null of the TrueB
899 // or FalseB block is null). SSB is the potential successor block
900 // of the SplitB that is neither TrueB nor FalseB.
901 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, TII->get(Hexagon::J2_jump))
902 .addMBB(SSB);
903 FP.SplitB->addSuccessor(SSB);
904 }
905 }
906
907 // What is left to do is to update the PHI nodes that could have entries
908 // referring to predicated blocks.
909 if (FP.JoinB) {
910 updatePhiNodes(FP.JoinB, FP);
911 } else {
912 if (TSB)
913 updatePhiNodes(TSB, FP);
914 if (FSB)
915 updatePhiNodes(FSB, FP);
916 // Nothing to update in SSB, since SSB's predecessors haven't changed.
917 }
918 }
919
920
921 void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) {
922 DEBUG(dbgs() << "Removing block " << PrintMB(B) << "\n");
923
924 // Transfer the immediate dominator information from B to its descendants.
925 MachineDomTreeNode *N = MDT->getNode(B);
926 MachineDomTreeNode *IDN = N->getIDom();
927 if (IDN) {
928 MachineBasicBlock *IDB = IDN->getBlock();
929 typedef GraphTraits GTN;
930 typedef SmallVector DTNodeVectType;
931 DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
932 for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
933 MachineBasicBlock *SB = (*I)->getBlock();
934 MDT->changeImmediateDominator(SB, IDB);
935 }
936 }
937
938 while (B->succ_size() > 0)
939 B->removeSuccessor(B->succ_begin());
940
941 for (auto I = B->pred_begin(), E = B->pred_end(); I != E; ++I)
942 (*I)->removeSuccessor(B);
943
944 Deleted.insert(B);
945 MDT->eraseNode(B);
946 MachineFunction::iterator BI = B;
947 MFN->erase(BI);
948 }
949
950
951 void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) {
952 DEBUG(dbgs() << "Removing phi nodes from block " << PrintMB(B) << "\n");
953 MachineBasicBlock::iterator I, NextI, NonPHI = B->getFirstNonPHI();
954 for (I = B->begin(); I != NonPHI; I = NextI) {
955 NextI = std::next(I);
956 MachineInstr *PN = &*I;
957 assert(PN->getNumOperands() == 3 && "Invalid phi node");
958 MachineOperand &UO = PN->getOperand(1);
959 unsigned UseR = UO.getReg(), UseSR = UO.getSubReg();
960 unsigned DefR = PN->getOperand(0).getReg();
961 unsigned NewR = UseR;
962 if (UseSR) {
963 // MRI.replaceVregUsesWith does not allow to update the subregister,
964 // so instead of doing the use-iteration here, create a copy into a
965 // "non-subregistered" register.
966 DebugLoc DL = PN->getDebugLoc();
967 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
968 NewR = MRI->createVirtualRegister(RC);
969 NonPHI = BuildMI(*B, NonPHI, DL, TII->get(TargetOpcode::COPY), NewR)
970 .addReg(UseR, 0, UseSR);
971 }
972 MRI->replaceRegWith(DefR, NewR);
973 B->erase(I);
974 }
975 }
976
977
978 void HexagonEarlyIfConversion::replacePhiEdges(MachineBasicBlock *OldB,
979 MachineBasicBlock *NewB) {
980 for (auto I = OldB->succ_begin(), E = OldB->succ_end(); I != E; ++I) {
981 MachineBasicBlock *SB = *I;
982 MachineBasicBlock::iterator P, N = SB->getFirstNonPHI();
983 for (P = SB->begin(); P != N; ++P) {
984 MachineInstr *PN = &*P;
985 for (MIOperands MO(PN); MO.isValid(); ++MO)
986 if (MO->isMBB() && MO->getMBB() == OldB)
987 MO->setMBB(NewB);
988 }
989 }
990 }
991
992
993 void HexagonEarlyIfConversion::mergeBlocks(MachineBasicBlock *PredB,
994 MachineBasicBlock *SuccB) {
995 DEBUG(dbgs() << "Merging blocks " << PrintMB(PredB) << " and "
996 << PrintMB(SuccB) << "\n");
997 bool TermOk = hasUncondBranch(SuccB);
998 eliminatePhis(SuccB);
999 TII->RemoveBranch(*PredB);
1000 PredB->removeSuccessor(SuccB);
1001 PredB->splice(PredB->end(), SuccB, SuccB->begin(), SuccB->end());
1002 MachineBasicBlock::succ_iterator I, E = SuccB->succ_end();
1003 for (I = SuccB->succ_begin(); I != E; ++I)
1004 PredB->addSuccessor(*I);
1005 replacePhiEdges(SuccB, PredB);
1006 removeBlock(SuccB);
1007 if (!TermOk)
1008 PredB->updateTerminator();
1009 }
1010
1011
1012 void HexagonEarlyIfConversion::simplifyFlowGraph(const FlowPattern &FP) {
1013 if (FP.TrueB)
1014 removeBlock(FP.TrueB);
1015 if (FP.FalseB)
1016 removeBlock(FP.FalseB);
1017
1018 FP.SplitB->updateTerminator();
1019 if (FP.SplitB->succ_size() != 1)
1020 return;
1021
1022 MachineBasicBlock *SB = *FP.SplitB->succ_begin();
1023 if (SB->pred_size() != 1)
1024 return;
1025
1026 // By now, the split block has only one successor (SB), and SB has only
1027 // one predecessor. We can try to merge them. We will need to update ter-
1028 // minators in FP.Split+SB, and that requires working AnalyzeBranch, which
1029 // fails on Hexagon for blocks that have EH_LABELs. However, if SB ends
1030 // with an unconditional branch, we won't need to touch the terminators.
1031 if (!hasEHLabel(SB) || hasUncondBranch(SB))
1032 mergeBlocks(FP.SplitB, SB);
1033 }
1034
1035
1036 bool HexagonEarlyIfConversion::runOnMachineFunction(MachineFunction &MF) {
1037 auto &ST = MF.getSubtarget();
1038 TII = ST.getInstrInfo();
1039 TRI = ST.getRegisterInfo();
1040 MFN = &MF;
1041 MRI = &MF.getRegInfo();
1042 MDT = &getAnalysis();
1043 MLI = &getAnalysis();
1044 MBPI = EnableHexagonBP ? &getAnalysis() :
1045 nullptr;
1046
1047 Deleted.clear();
1048 bool Changed = false;
1049
1050 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I)
1051 Changed |= visitLoop(*I);
1052 Changed |= visitLoop(0);
1053
1054 return Changed;
1055 }
1056
1057 //===----------------------------------------------------------------------===//
1058 // Public Constructor Functions
1059 //===----------------------------------------------------------------------===//
1060 FunctionPass *llvm::createHexagonEarlyIfConversion() {
1061 return new HexagonEarlyIfConversion();
1062 }
1063
683683 }
684684 bool
685685 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
686 const HexagonRegisterInfo &TRI = getRegisterInfo();
686 const HexagonRegisterInfo &HRI = getRegisterInfo();
687687 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
688688 MachineBasicBlock &MBB = *MI->getParent();
689689 DebugLoc DL = MI->getDebugLoc();
692692 switch (Opc) {
693693 case Hexagon::ALIGNA:
694694 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
695 .addReg(TRI.getFrameRegister())
695 .addReg(HRI.getFrameRegister())
696696 .addImm(-MI->getOperand(1).getImm());
697697 MBB.erase(MI);
698698 return true;
717717 unsigned DstReg = MI->getOperand(0).getReg();
718718 unsigned Src1Reg = MI->getOperand(1).getReg();
719719 unsigned Src2Reg = MI->getOperand(2).getReg();
720 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
721 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
722 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
723 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
720 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
721 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
722 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
723 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
724724 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
725 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
725 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
726726 .addReg(Src2SubHi);
727727 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
728 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
728 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
729729 .addReg(Src2SubLo);
730730 MBB.erase(MI);
731731 MRI.clearKillFlags(Src1SubHi);
740740 unsigned Src1Reg = MI->getOperand(1).getReg();
741741 unsigned Src2Reg = MI->getOperand(2).getReg();
742742 unsigned Src3Reg = MI->getOperand(3).getReg();
743 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
744 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
745 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
746 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
747 unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
748 unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
743 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
744 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
745 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
746 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
747 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
748 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
749749 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
750 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
750 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
751751 .addReg(Src2SubHi).addReg(Src3SubHi);
752752 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
753 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
753 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
754754 .addReg(Src2SubLo).addReg(Src3SubLo);
755755 MBB.erase(MI);
756756 MRI.clearKillFlags(Src1SubHi);
759759 MRI.clearKillFlags(Src2SubLo);
760760 MRI.clearKillFlags(Src3SubHi);
761761 MRI.clearKillFlags(Src3SubLo);
762 return true;
763 }
764 case Hexagon::MUX64_rr: {
765 const MachineOperand &Op0 = MI->getOperand(0);
766 const MachineOperand &Op1 = MI->getOperand(1);
767 const MachineOperand &Op2 = MI->getOperand(2);
768 const MachineOperand &Op3 = MI->getOperand(3);
769 unsigned Rd = Op0.getReg();
770 unsigned Pu = Op1.getReg();
771 unsigned Rs = Op2.getReg();
772 unsigned Rt = Op3.getReg();
773 DebugLoc DL = MI->getDebugLoc();
774 unsigned K1 = getKillRegState(Op1.isKill());
775 unsigned K2 = getKillRegState(Op2.isKill());
776 unsigned K3 = getKillRegState(Op3.isKill());
777 if (Rd != Rs)
778 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
779 .addReg(Pu, (Rd == Rt) ? K1 : 0)
780 .addReg(Rs, K2);
781 if (Rd != Rt)
782 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
783 .addReg(Pu, K1)
784 .addReg(Rt, K3);
785 MBB.erase(MI);
762786 return true;
763787 }
764788 case Hexagon::TCRETURNi:
12841308 case Hexagon::TFR_FIA:
12851309 case Hexagon::INLINEASM:
12861310 return true;
1287 }
1311
1312 case Hexagon::L2_ploadrbt_io:
1313 case Hexagon::L2_ploadrbf_io:
1314 case Hexagon::L2_ploadrubt_io:
1315 case Hexagon::L2_ploadrubf_io:
1316 case Hexagon::S2_pstorerbt_io:
1317 case Hexagon::S2_pstorerbf_io:
1318 case Hexagon::S4_storeirb_io:
1319 case Hexagon::S4_storeirbt_io:
1320 case Hexagon::S4_storeirbf_io:
1321 return isUInt<6>(Offset);
1322
1323 case Hexagon::L2_ploadrht_io:
1324 case Hexagon::L2_ploadrhf_io:
1325 case Hexagon::L2_ploadruht_io:
1326 case Hexagon::L2_ploadruhf_io:
1327 case Hexagon::S2_pstorerht_io:
1328 case Hexagon::S2_pstorerhf_io:
1329 case Hexagon::S4_storeirh_io:
1330 case Hexagon::S4_storeirht_io:
1331 case Hexagon::S4_storeirhf_io:
1332 return isShiftedUInt<6,1>(Offset);
1333
1334 case Hexagon::L2_ploadrit_io:
1335 case Hexagon::L2_ploadrif_io:
1336 case Hexagon::S2_pstorerit_io:
1337 case Hexagon::S2_pstorerif_io:
1338 case Hexagon::S4_storeiri_io:
1339 case Hexagon::S4_storeirit_io:
1340 case Hexagon::S4_storeirif_io:
1341 return isShiftedUInt<6,2>(Offset);
1342
1343 case Hexagon::L2_ploadrdt_io:
1344 case Hexagon::L2_ploadrdf_io:
1345 case Hexagon::S2_pstorerdt_io:
1346 case Hexagon::S2_pstorerdf_io:
1347 return isShiftedUInt<6,3>(Offset);
1348 } // switch
12881349
12891350 llvm_unreachable("No offset range is defined for this opcode. "
12901351 "Please define it in the above switch statement!");
3636 cl::init(true), cl::Hidden, cl::ZeroOrMore,
3737 cl::desc("Early expansion of MUX"));
3838
39 static cl::opt EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
40 cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
41
3942 static cl::opt EnableGenInsert("hexagon-insert", cl::init(true),
4043 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
4144
7780 FunctionPass *createHexagonCFGOptimizer();
7881 FunctionPass *createHexagonCommonGEP();
7982 FunctionPass *createHexagonCopyToCombine();
83 FunctionPass *createHexagonEarlyIfConversion();
8084 FunctionPass *createHexagonExpandCondsets();
8185 FunctionPass *createHexagonExpandPredSpillCode();
8286 FunctionPass *createHexagonFixupHwLoops();
213217 printAndVerify("After hexagon peephole pass");
214218 if (EnableGenInsert)
215219 addPass(createHexagonGenInsert(), false);
220 if (EnableEarlyIf)
221 addPass(createHexagonEarlyIfConversion(), false);
216222 }
217223
218224 return false;
0 ; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
1 ; we do not want to see a segv.
2 ; CHECK-NOT: segmentation
3 ; CHECK: call
4
5 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
6 target triple = "hexagon"
7
8 %"class.std::__1::basic_string" = type { %"class.std::__1::__compressed_pair" }
9 %"class.std::__1::__compressed_pair" = type { %"class.std::__1::__libcpp_compressed_pair_imp" }
10 %"class.std::__1::__libcpp_compressed_pair_imp" = type { %"struct.std::__1::basic_string, std::__1::allocator >::__rep" }
11 %"struct.std::__1::basic_string, std::__1::allocator >::__rep" = type { %union.anon }
12 %union.anon = type { %"struct.std::__1::basic_string, std::__1::allocator >::__long" }
13 %"struct.std::__1::basic_string, std::__1::allocator >::__long" = type { i32, i32, i8* }
14 %"class.std::__1::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, i8*, i8*, void (i8, %"class.std::__1::ios_base"*, i32)**, i32*, i32, i32, i32*, i32, i32, i8**, i32, i32 }
15 %"class.std::__1::basic_streambuf" = type { i32 (...)**, %"class.std::__1::locale", i8*, i8*, i8*, i8*, i8*, i8* }
16 %"class.std::__1::locale" = type { %"class.std::__1::locale::__imp"* }
17 %"class.std::__1::locale::__imp" = type opaque
18 %"class.std::__1::allocator" = type { i8 }
19 %"class.std::__1::ostreambuf_iterator" = type { %"class.std::__1::basic_streambuf"* }
20 %"class.std::__1::__basic_string_common" = type { i8 }
21 %"struct.std::__1::basic_string, std::__1::allocator >::__short" = type { %union.anon.0, [11 x i8] }
22 %union.anon.0 = type { i8 }
23
24 ; Function Attrs: nounwind
25 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
26
27 declare i32 @__gxx_personality_v0(...)
28
29 ; Function Attrs: nounwind
30 declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"*) #1
31
32 define weak_odr hidden i32 @_ZNSt3__116__pad_and_outputIcNS_11char_traitsIcEEEENS_19ostreambuf_iteratorIT_T0_EES6_PKS4_S8_S8_RNS_8ios_baseES4_(i32 %__s.coerce, i8* %__ob, i8* %__op, i8* %__oe, %"class.std::__1::ios_base"* nonnull %__iob, i8 zeroext %__fl) #2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
33 entry:
34 %this.addr.i66 = alloca %"class.std::__1::basic_streambuf"*, align 4
35 %__s.addr.i67 = alloca i8*, align 4
36 %__n.addr.i68 = alloca i32, align 4
37 %__p.addr.i.i = alloca i8*, align 4
38 %this.addr.i.i.i13.i.i = alloca %"class.std::__1::__libcpp_compressed_pair_imp"*, align 4
39 %this.addr.i.i14.i.i = alloca %"class.std::__1::__compressed_pair"*, align 4
40 %this.addr.i15.i.i = alloca %"class.std::__1::basic_string"*, align 4
41 %__x.addr.i.i.i.i.i = alloca i8*, align 4
42 %__r.addr.i.i.i.i = alloca i8*, align 4
43 %this.addr.i.i.i4.i.i = alloca %"class.std::__1::__libcpp_compressed_pair_imp"*, align 4
44 %this.addr.i.i5.i.i = alloca %"class.std::__1::__compressed_pair"*, align 4
45 %this.addr.i6.i.i = alloca %"class.std::__1::basic_string"*, align 4
46 %this.addr.i.i.i.i.i56 = alloca %"class.std::__1::__libcpp_compressed_pair_imp"*, align 4
47 %this.addr.i.i.i.i57 = alloca %"class.std::__1::__compressed_pair"*, align 4
48 %this.addr.i.i.i58 = alloca %"class.std::__1::basic_string"*, align 4
49 %this.addr.i.i59 = alloca %"class.std::__1::basic_string"*, align 4
50 %this.addr.i60 = alloca %"class.std::__1::basic_string"*, align 4
51 %this.addr.i.i.i.i.i = alloca %"class.std::__1::allocator"*, align 4
52 %this.addr.i.i.i.i = alloca %"class.std::__1::__libcpp_compressed_pair_imp"*, align 4
53 %this.addr.i.i.i = alloca %"class.std::__1::__compressed_pair"*, align 4
54 %this.addr.i.i = alloca %"class.std::__1::basic_string"*, align 4
55 %__n.addr.i.i = alloca i32, align 4
56 %__c.addr.i.i = alloca i8, align 1
57 %this.addr.i53 = alloca %"class.std::__1::basic_string"*, align 4
58 %__n.addr.i54 = alloca i32, align 4
59 %__c.addr.i = alloca i8, align 1
60 %this.addr.i46 = alloca %"class.std::__1::basic_streambuf"*, align 4
61 %__s.addr.i47 = alloca i8*, align 4
62 %__n.addr.i48 = alloca i32, align 4
63 %this.addr.i44 = alloca %"class.std::__1::basic_streambuf"*, align 4
64 %__s.addr.i = alloca i8*, align 4
65 %__n.addr.i = alloca i32, align 4
66 %this.addr.i41 = alloca %"class.std::__1::ios_base"*, align 4
67 %__wide.addr.i = alloca i32, align 4
68 %__r.i = alloca i32, align 4
69 %this.addr.i = alloca %"class.std::__1::ios_base"*, align 4
70 %retval = alloca %"class.std::__1::ostreambuf_iterator", align 4
71 %__s = alloca %"class.std::__1::ostreambuf_iterator", align 4
72 %__ob.addr = alloca i8*, align 4
73 %__op.addr = alloca i8*, align 4
74 %__oe.addr = alloca i8*, align 4
75 %__iob.addr = alloca %"class.std::__1::ios_base"*, align 4
76 %__fl.addr = alloca i8, align 1
77 %__sz = alloca i32, align 4
78 %__ns = alloca i32, align 4
79 %__np = alloca i32, align 4
80 %__sp = alloca %"class.std::__1::basic_string", align 4
81 %exn.slot = alloca i8*
82 %ehselector.slot = alloca i32
83 %cleanup.dest.slot = alloca i32
84 %coerce.dive = getelementptr %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
85 %coerce.val.ip = inttoptr i32 %__s.coerce to %"class.std::__1::basic_streambuf"*
86 store %"class.std::__1::basic_streambuf"* %coerce.val.ip, %"class.std::__1::basic_streambuf"** %coerce.dive
87 store i8* %__ob, i8** %__ob.addr, align 4
88 store i8* %__op, i8** %__op.addr, align 4
89 store i8* %__oe, i8** %__oe.addr, align 4
90 store %"class.std::__1::ios_base"* %__iob, %"class.std::__1::ios_base"** %__iob.addr, align 4
91 store i8 %__fl, i8* %__fl.addr, align 1
92 %__sbuf_ = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
93 %0 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %__sbuf_, align 4
94 %cmp = icmp eq %"class.std::__1::basic_streambuf"* %0, null
95 br i1 %cmp, label %if.then, label %if.end
96
97 if.then: ; preds = %entry
98 %1 = bitcast %"class.std::__1::ostreambuf_iterator"* %retval to i8*
99 %2 = bitcast %"class.std::__1::ostreambuf_iterator"* %__s to i8*
100 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %2, i32 4, i32 4, i1 false)
101 br label %return
102
103 if.end: ; preds = %entry
104 %3 = load i8*, i8** %__oe.addr, align 4
105 %4 = load i8*, i8** %__ob.addr, align 4
106 %sub.ptr.lhs.cast = ptrtoint i8* %3 to i32
107 %sub.ptr.rhs.cast = ptrtoint i8* %4 to i32
108 %sub.ptr.sub = sub i32 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
109 store i32 %sub.ptr.sub, i32* %__sz, align 4
110 %5 = load %"class.std::__1::ios_base"*, %"class.std::__1::ios_base"** %__iob.addr, align 4
111 store %"class.std::__1::ios_base"* %5, %"class.std::__1::ios_base"** %this.addr.i, align 4
112 %this1.i = load %"class.std::__1::ios_base"*, %"class.std::__1::ios_base"** %this.addr.i
113 %__width_.i = getelementptr inbounds %"class.std::__1::ios_base", %"class.std::__1::ios_base"* %this1.i, i32 0, i32 3
114 %6 = load i32, i32* %__width_.i, align 4
115 store i32 %6, i32* %__ns, align 4
116 %7 = load i32, i32* %__ns, align 4
117 %8 = load i32, i32* %__sz, align 4
118 %cmp1 = icmp sgt i32 %7, %8
119 br i1 %cmp1, label %if.then2, label %if.else
120
121 if.then2: ; preds = %if.end
122 %9 = load i32, i32* %__sz, align 4
123 %10 = load i32, i32* %__ns, align 4
124 %sub = sub nsw i32 %10, %9
125 store i32 %sub, i32* %__ns, align 4
126 br label %if.end3
127
128 if.else: ; preds = %if.end
129 store i32 0, i32* %__ns, align 4
130 br label %if.end3
131
132 if.end3: ; preds = %if.else, %if.then2
133 %11 = load i8*, i8** %__op.addr, align 4
134 %12 = load i8*, i8** %__ob.addr, align 4
135 %sub.ptr.lhs.cast4 = ptrtoint i8* %11 to i32
136 %sub.ptr.rhs.cast5 = ptrtoint i8* %12 to i32
137 %sub.ptr.sub6 = sub i32 %sub.ptr.lhs.cast4, %sub.ptr.rhs.cast5
138 store i32 %sub.ptr.sub6, i32* %__np, align 4
139 %13 = load i32, i32* %__np, align 4
140 %cmp7 = icmp sgt i32 %13, 0
141 br i1 %cmp7, label %if.then8, label %if.end15
142
143 if.then8: ; preds = %if.end3
144 %__sbuf_9 = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
145 %14 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %__sbuf_9, align 4
146 %15 = load i8*, i8** %__ob.addr, align 4
147 %16 = load i32, i32* %__np, align 4
148 store %"class.std::__1::basic_streambuf"* %14, %"class.std::__1::basic_streambuf"** %this.addr.i46, align 4
149 store i8* %15, i8** %__s.addr.i47, align 4
150 store i32 %16, i32* %__n.addr.i48, align 4
151 %this1.i49 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %this.addr.i46
152 %17 = bitcast %"class.std::__1::basic_streambuf"* %this1.i49 to i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)***
153 %vtable.i50 = load i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)**, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*** %17
154 %vfn.i51 = getelementptr inbounds i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)** %vtable.i50, i64 12
155 %18 = load i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)** %vfn.i51
156 %19 = load i8*, i8** %__s.addr.i47, align 4
157 %20 = load i32, i32* %__n.addr.i48, align 4
158 %call.i52 = call i32 %18(%"class.std::__1::basic_streambuf"* %this1.i49, i8* %19, i32 %20)
159 %21 = load i32, i32* %__np, align 4
160 %cmp11 = icmp ne i32 %call.i52, %21
161 br i1 %cmp11, label %if.then12, label %if.end14
162
163 if.then12: ; preds = %if.then8
164 %__sbuf_13 = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
165 store %"class.std::__1::basic_streambuf"* null, %"class.std::__1::basic_streambuf"** %__sbuf_13, align 4
166 %22 = bitcast %"class.std::__1::ostreambuf_iterator"* %retval to i8*
167 %23 = bitcast %"class.std::__1::ostreambuf_iterator"* %__s to i8*
168 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %22, i8* %23, i32 4, i32 4, i1 false)
169 br label %return
170
171 if.end14: ; preds = %if.then8
172 br label %if.end15
173
174 if.end15: ; preds = %if.end14, %if.end3
175 %24 = load i32, i32* %__ns, align 4
176 %cmp16 = icmp sgt i32 %24, 0
177 br i1 %cmp16, label %if.then17, label %if.end25
178
179 if.then17: ; preds = %if.end15
180 %25 = load i32, i32* %__ns, align 4
181 %26 = load i8, i8* %__fl.addr, align 1
182 store %"class.std::__1::basic_string"* %__sp, %"class.std::__1::basic_string"** %this.addr.i53, align 4
183 store i32 %25, i32* %__n.addr.i54, align 4
184 store i8 %26, i8* %__c.addr.i, align 1
185 %this1.i55 = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i53
186 %27 = load i32, i32* %__n.addr.i54, align 4
187 %28 = load i8, i8* %__c.addr.i, align 1
188 store %"class.std::__1::basic_string"* %this1.i55, %"class.std::__1::basic_string"** %this.addr.i.i, align 4
189 store i32 %27, i32* %__n.addr.i.i, align 4
190 store i8 %28, i8* %__c.addr.i.i, align 1
191 %this1.i.i = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i.i
192 %29 = bitcast %"class.std::__1::basic_string"* %this1.i.i to %"class.std::__1::__basic_string_common"*
193 %__r_.i.i = getelementptr inbounds %"class.std::__1::basic_string", %"class.std::__1::basic_string"* %this1.i.i, i32 0, i32 0
194 store %"class.std::__1::__compressed_pair"* %__r_.i.i, %"class.std::__1::__compressed_pair"** %this.addr.i.i.i, align 4
195 %this1.i.i.i = load %"class.std::__1::__compressed_pair"*, %"class.std::__1::__compressed_pair"** %this.addr.i.i.i
196 %30 = bitcast %"class.std::__1::__compressed_pair"* %this1.i.i.i to %"class.std::__1::__libcpp_compressed_pair_imp"*
197 store %"class.std::__1::__libcpp_compressed_pair_imp"* %30, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i.i, align 4
198 %this1.i.i.i.i = load %"class.std::__1::__libcpp_compressed_pair_imp"*, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i.i
199 %31 = bitcast %"class.std::__1::__libcpp_compressed_pair_imp"* %this1.i.i.i.i to %"class.std::__1::allocator"*
200 store %"class.std::__1::allocator"* %31, %"class.std::__1::allocator"** %this.addr.i.i.i.i.i, align 4
201 %this1.i.i.i.i.i = load %"class.std::__1::allocator"*, %"class.std::__1::allocator"** %this.addr.i.i.i.i.i
202 %__first_.i.i.i.i = getelementptr inbounds %"class.std::__1::__libcpp_compressed_pair_imp", %"class.std::__1::__libcpp_compressed_pair_imp"* %this1.i.i.i.i, i32 0, i32 0
203 %32 = load i32, i32* %__n.addr.i.i, align 4
204 %33 = load i8, i8* %__c.addr.i.i, align 1
205 call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEjc(%"class.std::__1::basic_string"* %this1.i.i, i32 %32, i8 zeroext %33)
206 %__sbuf_18 = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
207 %34 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %__sbuf_18, align 4
208 store %"class.std::__1::basic_string"* %__sp, %"class.std::__1::basic_string"** %this.addr.i60, align 4
209 %this1.i61 = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i60
210 store %"class.std::__1::basic_string"* %this1.i61, %"class.std::__1::basic_string"** %this.addr.i.i59, align 4
211 %this1.i.i62 = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i.i59
212 store %"class.std::__1::basic_string"* %this1.i.i62, %"class.std::__1::basic_string"** %this.addr.i.i.i58, align 4
213 %this1.i.i.i63 = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i.i.i58
214 %__r_.i.i.i = getelementptr inbounds %"class.std::__1::basic_string", %"class.std::__1::basic_string"* %this1.i.i.i63, i32 0, i32 0
215 store %"class.std::__1::__compressed_pair"* %__r_.i.i.i, %"class.std::__1::__compressed_pair"** %this.addr.i.i.i.i57, align 4
216 %this1.i.i.i.i64 = load %"class.std::__1::__compressed_pair"*, %"class.std::__1::__compressed_pair"** %this.addr.i.i.i.i57
217 %35 = bitcast %"class.std::__1::__compressed_pair"* %this1.i.i.i.i64 to %"class.std::__1::__libcpp_compressed_pair_imp"*
218 store %"class.std::__1::__libcpp_compressed_pair_imp"* %35, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i.i.i56, align 4
219 %this1.i.i.i.i.i65 = load %"class.std::__1::__libcpp_compressed_pair_imp"*, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i.i.i56
220 %__first_.i.i.i.i.i = getelementptr inbounds %"class.std::__1::__libcpp_compressed_pair_imp", %"class.std::__1::__libcpp_compressed_pair_imp"* %this1.i.i.i.i.i65, i32 0, i32 0
221 %36 = getelementptr inbounds %"struct.std::__1::basic_string, std::__1::allocator >::__rep", %"struct.std::__1::basic_string, std::__1::allocator >::__rep"* %__first_.i.i.i.i.i, i32 0, i32 0
222 %__s.i.i.i = bitcast %union.anon* %36 to %"struct.std::__1::basic_string, std::__1::allocator >::__short"*
223 %37 = getelementptr inbounds %"struct.std::__1::basic_string, std::__1::allocator >::__short", %"struct.std::__1::basic_string, std::__1::allocator >::__short"* %__s.i.i.i, i32 0, i32 0
224 %__size_.i.i.i = bitcast %union.anon.0* %37 to i8*
225 %38 = load i8, i8* %__size_.i.i.i, align 1
226 %conv.i.i.i = zext i8 %38 to i32
227 %and.i.i.i = and i32 %conv.i.i.i, 1
228 %tobool.i.i.i = icmp ne i32 %and.i.i.i, 0
229 br i1 %tobool.i.i.i, label %cond.true.i.i, label %cond.false.i.i
230
231 cond.true.i.i: ; preds = %if.then17
232 store %"class.std::__1::basic_string"* %this1.i.i62, %"class.std::__1::basic_string"** %this.addr.i15.i.i, align 4
233 %this1.i16.i.i = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i15.i.i
234 %__r_.i17.i.i = getelementptr inbounds %"class.std::__1::basic_string", %"class.std::__1::basic_string"* %this1.i16.i.i, i32 0, i32 0
235 store %"class.std::__1::__compressed_pair"* %__r_.i17.i.i, %"class.std::__1::__compressed_pair"** %this.addr.i.i14.i.i, align 4
236 %this1.i.i18.i.i = load %"class.std::__1::__compressed_pair"*, %"class.std::__1::__compressed_pair"** %this.addr.i.i14.i.i
237 %39 = bitcast %"class.std::__1::__compressed_pair"* %this1.i.i18.i.i to %"class.std::__1::__libcpp_compressed_pair_imp"*
238 store %"class.std::__1::__libcpp_compressed_pair_imp"* %39, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i13.i.i, align 4
239 %this1.i.i.i19.i.i = load %"class.std::__1::__libcpp_compressed_pair_imp"*, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i13.i.i
240 %__first_.i.i.i20.i.i = getelementptr inbounds %"class.std::__1::__libcpp_compressed_pair_imp", %"class.std::__1::__libcpp_compressed_pair_imp"* %this1.i.i.i19.i.i, i32 0, i32 0
241 %40 = getelementptr inbounds %"struct.std::__1::basic_string, std::__1::allocator >::__rep", %"struct.std::__1::basic_string, std::__1::allocator >::__rep"* %__first_.i.i.i20.i.i, i32 0, i32 0
242 %__l.i.i.i = bitcast %union.anon* %40 to %"struct.std::__1::basic_string, std::__1::allocator >::__long"*
243 %__data_.i21.i.i = getelementptr inbounds %"struct.std::__1::basic_string, std::__1::allocator >::__long", %"struct.std::__1::basic_string, std::__1::allocator >::__long"* %__l.i.i.i, i32 0, i32 2
244 %41 = load i8*, i8** %__data_.i21.i.i, align 4
245 br label %_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv.exit
246
247 cond.false.i.i: ; preds = %if.then17
248 store %"class.std::__1::basic_string"* %this1.i.i62, %"class.std::__1::basic_string"** %this.addr.i6.i.i, align 4
249 %this1.i7.i.i = load %"class.std::__1::basic_string"*, %"class.std::__1::basic_string"** %this.addr.i6.i.i
250 %__r_.i8.i.i = getelementptr inbounds %"class.std::__1::basic_string", %"class.std::__1::basic_string"* %this1.i7.i.i, i32 0, i32 0
251 store %"class.std::__1::__compressed_pair"* %__r_.i8.i.i, %"class.std::__1::__compressed_pair"** %this.addr.i.i5.i.i, align 4
252 %this1.i.i9.i.i = load %"class.std::__1::__compressed_pair"*, %"class.std::__1::__compressed_pair"** %this.addr.i.i5.i.i
253 %42 = bitcast %"class.std::__1::__compressed_pair"* %this1.i.i9.i.i to %"class.std::__1::__libcpp_compressed_pair_imp"*
254 store %"class.std::__1::__libcpp_compressed_pair_imp"* %42, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i4.i.i, align 4
255 %this1.i.i.i10.i.i = load %"class.std::__1::__libcpp_compressed_pair_imp"*, %"class.std::__1::__libcpp_compressed_pair_imp"** %this.addr.i.i.i4.i.i
256 %__first_.i.i.i11.i.i = getelementptr inbounds %"class.std::__1::__libcpp_compressed_pair_imp", %"class.std::__1::__libcpp_compressed_pair_imp"* %this1.i.i.i10.i.i, i32 0, i32 0
257 %43 = getelementptr inbounds %"struct.std::__1::basic_string, std::__1::allocator >::__rep", %"struct.std::__1::basic_string, std::__1::allocator >::__rep"* %__first_.i.i.i11.i.i, i32 0, i32 0
258 %__s.i12.i.i = bitcast %union.anon* %43 to %"struct.std::__1::basic_string, std::__1::allocator >::__short"*
259 %__data_.i.i.i = getelementptr inbounds %"struct.std::__1::basic_string, std::__1::allocator >::__short", %"struct.std::__1::basic_string, std::__1::allocator >::__short"* %__s.i12.i.i, i32 0, i32 1
260 %arrayidx.i.i.i = getelementptr inbounds [11 x i8], [11 x i8]* %__data_.i.i.i, i32 0, i32 0
261 store i8* %arrayidx.i.i.i, i8** %__r.addr.i.i.i.i, align 4
262 %44 = load i8*, i8** %__r.addr.i.i.i.i, align 4
263 store i8* %44, i8** %__x.addr.i.i.i.i.i, align 4
264 %45 = load i8*, i8** %__x.addr.i.i.i.i.i, align 4
265 br label %_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv.exit
266
267 _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv.exit: ; preds = %cond.false.i.i, %cond.true.i.i
268 %cond.i.i = phi i8* [ %41, %cond.true.i.i ], [ %45, %cond.false.i.i ]
269 store i8* %cond.i.i, i8** %__p.addr.i.i, align 4
270 %46 = load i8*, i8** %__p.addr.i.i, align 4
271 %47 = load i32, i32* %__ns, align 4
272 store %"class.std::__1::basic_streambuf"* %34, %"class.std::__1::basic_streambuf"** %this.addr.i66, align 4
273 store i8* %46, i8** %__s.addr.i67, align 4
274 store i32 %47, i32* %__n.addr.i68, align 4
275 %this1.i69 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %this.addr.i66
276 %48 = bitcast %"class.std::__1::basic_streambuf"* %this1.i69 to i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)***
277 %vtable.i70 = load i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)**, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*** %48
278 %vfn.i71 = getelementptr inbounds i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)** %vtable.i70, i64 12
279 %49 = load i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)** %vfn.i71
280 %50 = load i8*, i8** %__s.addr.i67, align 4
281 %51 = load i32, i32* %__n.addr.i68, align 4
282 %call.i7273 = invoke i32 %49(%"class.std::__1::basic_streambuf"* %this1.i69, i8* %50, i32 %51)
283 to label %_ZNSt3__115basic_streambufIcNS_11char_traitsIcEEE5sputnEPKci.exit unwind label %lpad
284
285 _ZNSt3__115basic_streambufIcNS_11char_traitsIcEEE5sputnEPKci.exit: ; preds = %_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv.exit
286 br label %invoke.cont
287
288 invoke.cont: ; preds = %_ZNSt3__115basic_streambufIcNS_11char_traitsIcEEE5sputnEPKci.exit
289 %52 = load i32, i32* %__ns, align 4
290 %cmp21 = icmp ne i32 %call.i7273, %52
291 br i1 %cmp21, label %if.then22, label %if.end24
292
293 if.then22: ; preds = %invoke.cont
294 %__sbuf_23 = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
295 store %"class.std::__1::basic_streambuf"* null, %"class.std::__1::basic_streambuf"** %__sbuf_23, align 4
296 %53 = bitcast %"class.std::__1::ostreambuf_iterator"* %retval to i8*
297 %54 = bitcast %"class.std::__1::ostreambuf_iterator"* %__s to i8*
298 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %53, i8* %54, i32 4, i32 4, i1 false)
299 store i32 1, i32* %cleanup.dest.slot
300 br label %cleanup
301
302 lpad: ; preds = %_ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv.exit
303 %55 = landingpad { i8*, i32 }
304 cleanup
305 %56 = extractvalue { i8*, i32 } %55, 0
306 store i8* %56, i8** %exn.slot
307 %57 = extractvalue { i8*, i32 } %55, 1
308 store i32 %57, i32* %ehselector.slot
309 call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %__sp) #0
310 br label %eh.resume
311
312 if.end24: ; preds = %invoke.cont
313 store i32 0, i32* %cleanup.dest.slot
314 br label %cleanup
315
316 cleanup: ; preds = %if.end24, %if.then22
317 call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %__sp) #0
318 %cleanup.dest = load i32, i32* %cleanup.dest.slot
319 switch i32 %cleanup.dest, label %unreachable [
320 i32 0, label %cleanup.cont
321 i32 1, label %return
322 ]
323
324 cleanup.cont: ; preds = %cleanup
325 br label %if.end25
326
327 if.end25: ; preds = %cleanup.cont, %if.end15
328 %58 = load i8*, i8** %__oe.addr, align 4
329 %59 = load i8*, i8** %__op.addr, align 4
330 %sub.ptr.lhs.cast26 = ptrtoint i8* %58 to i32
331 %sub.ptr.rhs.cast27 = ptrtoint i8* %59 to i32
332 %sub.ptr.sub28 = sub i32 %sub.ptr.lhs.cast26, %sub.ptr.rhs.cast27
333 store i32 %sub.ptr.sub28, i32* %__np, align 4
334 %60 = load i32, i32* %__np, align 4
335 %cmp29 = icmp sgt i32 %60, 0
336 br i1 %cmp29, label %if.then30, label %if.end37
337
338 if.then30: ; preds = %if.end25
339 %__sbuf_31 = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
340 %61 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %__sbuf_31, align 4
341 %62 = load i8*, i8** %__op.addr, align 4
342 %63 = load i32, i32* %__np, align 4
343 store %"class.std::__1::basic_streambuf"* %61, %"class.std::__1::basic_streambuf"** %this.addr.i44, align 4
344 store i8* %62, i8** %__s.addr.i, align 4
345 store i32 %63, i32* %__n.addr.i, align 4
346 %this1.i45 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %this.addr.i44
347 %64 = bitcast %"class.std::__1::basic_streambuf"* %this1.i45 to i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)***
348 %vtable.i = load i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)**, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*** %64
349 %vfn.i = getelementptr inbounds i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)** %vtable.i, i64 12
350 %65 = load i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)*, i32 (%"class.std::__1::basic_streambuf"*, i8*, i32)** %vfn.i
351 %66 = load i8*, i8** %__s.addr.i, align 4
352 %67 = load i32, i32* %__n.addr.i, align 4
353 %call.i = call i32 %65(%"class.std::__1::basic_streambuf"* %this1.i45, i8* %66, i32 %67)
354 %68 = load i32, i32* %__np, align 4
355 %cmp33 = icmp ne i32 %call.i, %68
356 br i1 %cmp33, label %if.then34, label %if.end36
357
358 if.then34: ; preds = %if.then30
359 %__sbuf_35 = getelementptr inbounds %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %__s, i32 0, i32 0
360 store %"class.std::__1::basic_streambuf"* null, %"class.std::__1::basic_streambuf"** %__sbuf_35, align 4
361 %69 = bitcast %"class.std::__1::ostreambuf_iterator"* %retval to i8*
362 %70 = bitcast %"class.std::__1::ostreambuf_iterator"* %__s to i8*
363 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %69, i8* %70, i32 4, i32 4, i1 false)
364 br label %return
365
366 if.end36: ; preds = %if.then30
367 br label %if.end37
368
369 if.end37: ; preds = %if.end36, %if.end25
370 %71 = load %"class.std::__1::ios_base"*, %"class.std::__1::ios_base"** %__iob.addr, align 4
371 store %"class.std::__1::ios_base"* %71, %"class.std::__1::ios_base"** %this.addr.i41, align 4
372 store i32 0, i32* %__wide.addr.i, align 4
373 %this1.i42 = load %"class.std::__1::ios_base"*, %"class.std::__1::ios_base"** %this.addr.i41
374 %__width_.i43 = getelementptr inbounds %"class.std::__1::ios_base", %"class.std::__1::ios_base"* %this1.i42, i32 0, i32 3
375 %72 = load i32, i32* %__width_.i43, align 4
376 store i32 %72, i32* %__r.i, align 4
377 %73 = load i32, i32* %__wide.addr.i, align 4
378 %__width_2.i = getelementptr inbounds %"class.std::__1::ios_base", %"class.std::__1::ios_base"* %this1.i42, i32 0, i32 3
379 store i32 %73, i32* %__width_2.i, align 4
380 %74 = load i32, i32* %__r.i, align 4
381 %75 = bitcast %"class.std::__1::ostreambuf_iterator"* %retval to i8*
382 %76 = bitcast %"class.std::__1::ostreambuf_iterator"* %__s to i8*
383 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %75, i8* %76, i32 4, i32 4, i1 false)
384 br label %return
385
386 return: ; preds = %if.end37, %if.then34, %cleanup, %if.then12, %if.then
387 %coerce.dive39 = getelementptr %"class.std::__1::ostreambuf_iterator", %"class.std::__1::ostreambuf_iterator"* %retval, i32 0, i32 0
388 %77 = load %"class.std::__1::basic_streambuf"*, %"class.std::__1::basic_streambuf"** %coerce.dive39
389 %coerce.val.pi = ptrtoint %"class.std::__1::basic_streambuf"* %77 to i32
390 ret i32 %coerce.val.pi
391
392 eh.resume: ; preds = %lpad
393 %exn = load i8*, i8** %exn.slot
394 %sel = load i32, i32* %ehselector.slot
395 %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
396 %lpad.val40 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
397 resume { i8*, i32 } %lpad.val40
398
399 unreachable: ; preds = %cleanup
400 unreachable
401 }
402
403 declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEjc(%"class.std::__1::basic_string"*, i32, i8 zeroext) #2
404
405 attributes #0 = { nounwind }
406 attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
407 attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
408
409 !llvm.ident = !{!0}
410
411 !0 = !{!"Clang 3.1"}
0 ; RUN: llc < %s
1 ; REQUIRES: asserts
2 ; Check that the early if-conversion does not predicate block1 (where the
3 ; join block has a phi node of type i1).
4
5 define i1 @foo(i32 %x, i32* %p) {
6 entry:
7 %c = icmp sgt i32 %x, 0
8 %c1 = icmp sgt i32 %x, 10
9 br i1 %c, label %block2, label %block1
10 block1:
11 store i32 1, i32* %p, align 4
12 br label %block2
13 block2:
14 %b = phi i1 [ 0, %entry ], [ %c1, %block1 ]
15 ret i1 %b
16 }
0 ; RUN: llc -O2 -mcpu=hexagonv5 < %s | FileCheck %s
1 ; Check if the three stores in the loop were predicated.
2 ; CHECK: if{{.*}}memw
3 ; CHECK: if{{.*}}memw
4 ; CHECK: if{{.*}}memw
5
6 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
7 target triple = "hexagon"
8
9 define void @fred(i32 %n, i32* %bp) nounwind {
10 entry:
11 %cmp16 = icmp eq i32 %n, 0
12 br i1 %cmp16, label %for.end, label %for.body.lr.ph
13
14 for.body.lr.ph: ; preds = %entry
15 %cmp2 = icmp ugt i32 %n, 32
16 br label %for.body
17
18 for.body: ; preds = %for.inc, %for.body.lr.ph
19 %i.017 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ]
20 %call = tail call i32 @foo(i32* %bp) nounwind
21 %call1 = tail call i32 @bar(i32* %bp) nounwind
22 br i1 %cmp2, label %if.then, label %if.else
23
24 if.then: ; preds = %for.body
25 %arrayidx = getelementptr inbounds i32, i32* %bp, i32 %i.017
26 store i32 %call, i32* %arrayidx, align 4, !tbaa !0
27 %add = add i32 %i.017, 2
28 %arrayidx3 = getelementptr inbounds i32, i32* %bp, i32 %add
29 store i32 %call1, i32* %arrayidx3, align 4, !tbaa !0
30 br label %for.inc
31
32 if.else: ; preds = %for.body
33 %or = or i32 %call1, %call
34 %arrayidx4 = getelementptr inbounds i32, i32* %bp, i32 %i.017
35 store i32 %or, i32* %arrayidx4, align 4, !tbaa !0
36 br label %for.inc
37
38 for.inc: ; preds = %if.then, %if.else
39 %inc = add i32 %i.017, 1
40 %exitcond = icmp eq i32 %inc, %n
41 br i1 %exitcond, label %for.end.loopexit, label %for.body
42
43 for.end.loopexit: ; preds = %for.inc
44 br label %for.end
45
46 for.end: ; preds = %for.end.loopexit, %entry
47 ret void
48 }
49
50 declare i32 @foo(i32*) nounwind
51
52 declare i32 @bar(i32*) nounwind
53
54 !0 = !{!"int", !1}
55 !1 = !{!"omnipotent char", !2}
56 !2 = !{!"Simple C/C++ TBAA"}
0 ; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
1 ; Rely on the comments generated by llc. Check that "if.then" was predicated.
2 ; CHECK: while.body13
3 ; CHECK: if{{.*}}memd
4 ; CHECK: while.end
5
6 %struct.1 = type { i32, i32 }
7 %struct.2 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %struct.1], [5 x i32] }
8
9 @A1 = global i64 zeroinitializer
10 @A2 = global i64 zeroinitializer
11 @B1 = global i32 zeroinitializer
12 @B2 = global i32 zeroinitializer
13 @C1 = global i8 zeroinitializer
14
15 declare i32 @llvm.hexagon.S2.cl0(i32) nounwind readnone
16 declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) nounwind readnone
17 declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) nounwind readnone
18 declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) nounwind readnone
19 declare i64 @llvm.hexagon.A2.vaddws(i64, i64) nounwind readnone
20 declare i64 @llvm.hexagon.A2.vsubws(i64, i64) nounwind readnone
21 declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) nounwind readnone
22
23 define void @foo(i32 %n, i64* %ptr) nounwind {
24 entry:
25 br label %while.body
26
27 while.body:
28 %count = phi i32 [ 0, %entry ], [ %next, %while.end ]
29 %idx = phi i32 [ 0, %entry ], [ %15, %while.end ]
30 %0 = load i32, i32* @B1, align 4
31 %1 = load i32, i32* @B2, align 8
32 %2 = and i32 %1, %0
33 br label %while.body13
34
35 while.body13: ; preds = %while.body, %if.end
36 %3 = phi i64 [ %13, %if.end ], [ 0, %while.body ]
37 %4 = phi i64 [ %14, %if.end ], [ 0, %while.body ]
38 %m = phi i32 [ %6, %if.end ], [ %2, %while.body ]
39 %5 = tail call i32 @llvm.hexagon.S2.cl0(i32 %m)
40 %6 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %m, i32 %5)
41 %cgep85 = getelementptr [10 x %struct.2], [10 x %struct.2]* inttoptr (i32 -121502345 to [10 x %struct.2]*), i32 0, i32 %idx
42 %cgep90 = getelementptr %struct.2, %struct.2* %cgep85, i32 0, i32 12, i32 %5
43 %7 = load i32, i32* %cgep90, align 4
44 %8 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %7, i32 %7)
45 %cgep91 = getelementptr %struct.2, %struct.2* %cgep85, i32 0, i32 13, i32 %5
46 %9 = load i32, i32* %cgep91, align 4
47 %10 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %8, i32 %9, i32 %9)
48 %11 = load i8, i8* @C1, align 1
49 %and24 = and i8 %11, 1
50 %cmp = icmp eq i8 %and24, 0
51 br i1 %cmp, label %if.then, label %if.end
52
53 if.then: ; preds = %while.body13
54 %12 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %3, i64 %10)
55 store i64 %12, i64* %ptr, align 8
56 br label %if.end
57
58 if.end: ; preds = %if.then, %while.body13
59 %13 = phi i64 [ %12, %if.then ], [ %3, %while.body13 ]
60 %14 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %4, i64 %10)
61 %tobool12 = icmp eq i32 %6, 0
62 br i1 %tobool12, label %while.end, label %while.body13
63
64 while.end:
65 %add40 = add i32 %idx, 1
66 %15 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %add40, i32 10) nounwind
67 %next = add i32 %count, 1
68 %cc = icmp eq i32 %next, %n
69 br i1 %cc, label %end, label %while.body
70
71 end:
72 store i64 %10, i64* @A2, align 8
73 ret void
74 }
None ; RUN: llc -march=hexagon -mcpu=hexagonv5 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s
0 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s
11 ; Check that the edge weights are updated correctly after if-conversion.
22
33 ; CHECK: BB#3: