llvm.org GIT mirror llvm / 42b7a71
Renamed MachineScheduler to ScheduleTopDownLive. Responding to code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148290 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
6 changed file(s) with 74 addition(s) and 62 deletion(s). Raw diff Collapse all Expand all
8484 extern char &RegisterCoalescerPassID;
8585
8686 /// MachineScheduler pass - This pass schedules machine instructions.
87 extern char &MachineSchedulerPassID;
87 extern char &MachineSchedulerID;
8888
8989 /// SpillPlacement analysis. Suggest optimal placement of spill code between
9090 /// basic blocks.
155155 void initializeMachineLoopInfoPass(PassRegistry&);
156156 void initializeMachineLoopRangesPass(PassRegistry&);
157157 void initializeMachineModuleInfoPass(PassRegistry&);
158 void initializeMachineSchedulerPassPass(PassRegistry&);
158 void initializeMachineSchedulerPass(PassRegistry&);
159159 void initializeMachineSinkingPass(PassRegistry&);
160160 void initializeMachineVerifierPassPass(PassRegistry&);
161161 void initializeMemCpyOptPass(PassRegistry&);
4242 initializeProcessImplicitDefsPass(Registry);
4343 initializePEIPass(Registry);
4444 initializeRegisterCoalescerPass(Registry);
45 initializeMachineSchedulerPassPass(Registry);
45 initializeMachineSchedulerPass(Registry);
4646 initializeRenderMachineFunctionPass(Registry);
4747 initializeSlotIndexesPass(Registry);
4848 initializeStackProtectorPass(Registry);
3333 //===----------------------------------------------------------------------===//
3434
3535 namespace {
36 /// MachineSchedulerPass runs after coalescing and before register allocation.
37 class MachineSchedulerPass : public MachineFunctionPass {
36 /// MachineScheduler runs after coalescing and before register allocation.
37 class MachineScheduler : public MachineFunctionPass {
3838 public:
3939 MachineFunction *MF;
4040 const TargetInstrInfo *TII;
4141 const MachineLoopInfo *MLI;
4242 const MachineDominatorTree *MDT;
4343
44 MachineSchedulerPass();
44 MachineScheduler();
4545
4646 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
4747
5555 };
5656 } // namespace
5757
58 char MachineSchedulerPass::ID = 0;
59
60 char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
61
62 INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
58 char MachineScheduler::ID = 0;
59
60 char &llvm::MachineSchedulerID = MachineScheduler::ID;
61
62 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
6363 "Machine Instruction Scheduler", false, false)
6464 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
6565 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
6767 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
6868 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
6969 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
70 INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
70 INITIALIZE_PASS_END(MachineScheduler, "misched",
7171 "Machine Instruction Scheduler", false, false)
7272
73 MachineSchedulerPass::MachineSchedulerPass()
73 MachineScheduler::MachineScheduler()
7474 : MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
75 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
76 }
77
78 void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
75 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
76 }
77
78 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
7979 AU.setPreservesCFG();
8080 AU.addRequiredID(MachineDominatorsID);
8181 AU.addRequired();
101101 /// schedulers.
102102 class MachineSchedRegistry : public MachinePassRegistryNode {
103103 public:
104 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
104 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
105105
106106 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
107107 typedef ScheduleDAGCtor FunctionPassCtor;
136136
137137 MachinePassRegistry MachineSchedRegistry::Registry;
138138
139 static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
139 static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
140140
141141 /// MachineSchedOpt allows command line selection of the scheduler.
142142 static cl::opt
146146 cl::desc("Machine instruction scheduler to use"));
147147
148148 //===----------------------------------------------------------------------===//
149 // Machine Instruction Scheduling Implementation
149 // Machine Instruction Scheduling Common Implementation
150150 //===----------------------------------------------------------------------===//
151151
152152 namespace {
153153 /// MachineScheduler is an implementation of ScheduleDAGInstrs that schedules
154154 /// machine instructions while updating LiveIntervals.
155 class MachineScheduler : public ScheduleDAGInstrs {
156 MachineSchedulerPass *Pass;
157 public:
158 MachineScheduler(MachineSchedulerPass *P):
155 class ScheduleTopDownLive : public ScheduleDAGInstrs {
156 protected:
157 MachineScheduler *Pass;
158 public:
159 ScheduleTopDownLive(MachineScheduler *P):
159160 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
160
161 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
162 /// time to do some work.
163 virtual void Schedule();
164 };
165 } // namespace
166
167 static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
168 return new MachineScheduler(P);
169 }
170 static MachineSchedRegistry
171 SchedDefaultRegistry("default", "Activate the scheduler pass, "
172 "but don't reorder instructions",
173 createDefaultMachineSched);
174
175 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
176 /// time to do some work.
177 void MachineScheduler::Schedule() {
178 BuildSchedGraph(&Pass->getAnalysis());
179
180 DEBUG(dbgs() << "********** MI Scheduling **********\n");
181 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
182 SUnits[su].dumpAll(this));
183
184 // TODO: Put interesting things here.
185 }
186
187 bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
161 };
162 } // namespace
163
164 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
188165 // Initialize the context of the pass.
189166 MF = &mf;
190167 MLI = &getAnalysis();
240217 return true;
241218 }
242219
243 void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
220 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
244221 // unimplemented
245222 }
246223
247224 //===----------------------------------------------------------------------===//
225 // Placeholder for extending the machine instruction scheduler.
226 //===----------------------------------------------------------------------===//
227
228 namespace {
229 class DefaultMachineScheduler : public ScheduleTopDownLive {
230 public:
231 DefaultMachineScheduler(MachineScheduler *P):
232 ScheduleTopDownLive(P) {}
233
234 void Schedule();
235 };
236 } // namespace
237
238 static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
239 return new DefaultMachineScheduler(P);
240 }
241 static MachineSchedRegistry
242 SchedDefaultRegistry("default", "Activate the scheduler pass, "
243 "but don't reorder instructions",
244 createDefaultMachineSched);
245
246
247 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
248 /// time to do some work.
249 void DefaultMachineScheduler::Schedule() {
250 BuildSchedGraph(&Pass->getAnalysis());
251
252 DEBUG(dbgs() << "********** MI Scheduling **********\n");
253 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
254 SUnits[su].dumpAll(this));
255
256 // TODO: Put interesting things here.
257 }
258
259 //===----------------------------------------------------------------------===//
248260 // Machine Instruction Shuffler for Correctness Testing
249261 //===----------------------------------------------------------------------===//
250262
251263 #ifndef NDEBUG
252264 namespace {
253265 /// Reorder instructions as much as possible.
254 class InstructionShuffler : public ScheduleDAGInstrs {
255 MachineSchedulerPass *Pass;
256 public:
257 InstructionShuffler(MachineSchedulerPass *P):
258 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
266 class InstructionShuffler : public ScheduleTopDownLive {
267 MachineScheduler *Pass;
268 public:
269 InstructionShuffler(MachineScheduler *P):
270 ScheduleTopDownLive(P) {}
259271
260272 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
261273 /// time to do some work.
265277 };
266278 } // namespace
267279
268 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
280 static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
269281 return new InstructionShuffler(P);
270282 }
271283 static MachineSchedRegistry ShufflerRegistry("shuffle",
128128 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
129129 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
130130 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
131 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
131 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
132132 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
133133 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
134134 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
315315 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
316316 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
317317 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
318 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
318 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
319319 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
320320 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
321321 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
338338 AU.addRequiredID(StrongPHIEliminationID);
339339 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
340340 if (EnableMachineSched)
341 AU.addRequiredID(MachineSchedulerPassID);
341 AU.addRequiredID(MachineSchedulerID);
342342 AU.addRequired();
343343 AU.addRequired();
344344 AU.addPreserved();