llvm.org GIT mirror llvm / 42aa501
Minor updates: - Fix typo in SPUCallingConv.td - Credit myself for CellSPU work - Add CellSPU to 'all' host target list git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44627 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Michel 11 years ago
3 changed file(s) with 6 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
256256 D: Darwin exception handling
257257 D: MMX & SSSE3 instructions
258258 D: SPEC2006 support
259
260 N: Scott Michel
261 E: scottm@aero.org
262 D: Added STI Cell SPU backend.
362362 [Build specific host targets: all,host-only,{target-name} (default=all)]),,
363363 enableval=all)
364364 case "$enableval" in
365 # Note: Add "CellSPU" to all when fully functional.
366 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips" ;;
365 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU" ;;
367366 host-only)
368367 case "$llvm_cv_target_arch" in
369368 x86) TARGETS_TO_BUILD="X86" ;;
4747 // The first 12 Vector arguments are passed in altivec registers.
4848 CCIfType<[v16i8, v8i16, v4i32, v4f32],
4949 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
50 */
5150 /*
5251 // Integer/FP values get stored in stack slots that are 8 bytes in size and
5352 // 8-byte aligned if there are no more registers to hold them.
5554
5655 // Vectors get 16-byte stack slots that are 16-byte aligned.
5756 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
58 CCAssignToStack<16, 16>>
57 CCAssignToStack<16, 16>>*/
5958 ]>;
6059 */