llvm.org GIT mirror llvm / 4274e40
For PR1370: Rearrange some tests so that if PowerPC is not being built we don't try to run PowerPC specific tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36587 91177308-0d34-0410-b5e6-96231b3b80d8 Reid Spencer 13 years ago
8 changed file(s) with 59 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llvm-as < %s | llc -march=arm | grep {mov r0, r0, lsr #31}
1 ; RUN: llvm-as < %s | llc -march=thumb | grep {lsr r0, r0, #31}
2
3 define i32 @test1(i32 %X) {
4 entry:
5 icmp slt i32 %X, 0 ; :0 [#uses=1]
6 zext i1 %0 to i32 ; :1 [#uses=1]
7 ret i32 %1
8 }
9
+0
-14
test/CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll less more
None ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwimi
1
2 void %test(short %div.0.i.i.i.i, int %L_num.0.i.i.i.i, int %tmp1.i.i206.i.i, short* %P) {
3 %X = shl short %div.0.i.i.i.i, ubyte 1 ; [#uses=1]
4 %tmp28.i.i.i.i = shl int %L_num.0.i.i.i.i, ubyte 1 ; [#uses=2]
5 %tmp31.i.i.i.i = setlt int %tmp28.i.i.i.i, %tmp1.i.i206.i.i ; [#uses=2]
6
7 %tmp31.i.i.i.i = cast bool %tmp31.i.i.i.i to short ; [#uses=1]
8 %tmp371.i.i.i.i1 = or short %tmp31.i.i.i.i, %X ; [#uses=1]
9 %div.0.be.i.i.i.i = xor short %tmp371.i.i.i.i1, 1 ; [#uses=1]
10 store short %div.0.be.i.i.i.i, short* %P
11 ret void
12 }
13
+0
-13
test/CodeGen/Generic/ispositive.ll less more
None ; RUN: llvm-as < %s | llc -march=x86 | grep {shrl.*31}
1 ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
2 ; RUN: grep {srwi r3, r3, 31}
3 ; RUN: llvm-as < %s | llc -march=arm | grep {mov r0, r0, lsr #31}
4 ; RUN: llvm-as < %s | llc -march=thumb | grep {lsr r0, r0, #31}
5
6 define i32 @test1(i32 %X) {
7 entry:
8 icmp slt i32 %X, 0 ; :0 [#uses=1]
9 zext i1 %0 to i32 ; :1 [#uses=1]
10 ret i32 %1
11 }
12
None ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep test:
1 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm
2 ; RUN: llvm-upgrade < %s | llvm-as | llc
31
42 void %test(<4 x float> *%tmp2.i) {
0 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwimi
1
2 void %test(short %div.0.i.i.i.i, int %L_num.0.i.i.i.i, int %tmp1.i.i206.i.i, short* %P) {
3 %X = shl short %div.0.i.i.i.i, ubyte 1 ; [#uses=1]
4 %tmp28.i.i.i.i = shl int %L_num.0.i.i.i.i, ubyte 1 ; [#uses=2]
5 %tmp31.i.i.i.i = setlt int %tmp28.i.i.i.i, %tmp1.i.i206.i.i ; [#uses=2]
6
7 %tmp31.i.i.i.i = cast bool %tmp31.i.i.i.i to short ; [#uses=1]
8 %tmp371.i.i.i.i1 = or short %tmp31.i.i.i.i, %X ; [#uses=1]
9 %div.0.be.i.i.i.i = xor short %tmp371.i.i.i.i1, 1 ; [#uses=1]
10 store short %div.0.be.i.i.i.i, short* %P
11 ret void
12 }
13
0 ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
1 ; RUN: grep {srwi r3, r3, 31}
2
3 define i32 @test1(i32 %X) {
4 entry:
5 icmp slt i32 %X, 0 ; :0 [#uses=1]
6 zext i1 %0 to i32 ; :1 [#uses=1]
7 ret i32 %1
8 }
9
0 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep test:
1 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm
2
3 void %test(<4 x float> *%tmp2.i) {
4 %tmp2.i = load <4x float>* %tmp2.i
5 %xFloat0.48 = extractelement <4 x float> %tmp2.i, uint 0 ; [#uses=1]
6 %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, uint 0 ; <<4 x float>> [#uses=1]
7 %xFloat1.50 = extractelement <4 x float> %tmp2.i, uint 1 ; [#uses=1]
8 %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float %xFloat1.50, uint 1 ; <<4 x float>> [#uses=1]
9 %xFloat2.53 = extractelement <4 x float> %tmp2.i, uint 2 ; [#uses=1]
10 %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float %xFloat2.53, uint 2 ; <<4 x float>> [#uses=1]
11 %xFloat3.56 = extractelement <4 x float> %tmp2.i, uint 3 ; [#uses=1]
12 %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float %xFloat3.56, uint 3 ; <<4 x float>> [#uses=4]
13 store <4 x float> %inFloat3.58, <4x float>* %tmp2.i
14 ret void
15 }
0 ; RUN: llvm-as < %s | llc -march=x86 | grep {shrl.*31}
1
2 define i32 @test1(i32 %X) {
3 entry:
4 icmp slt i32 %X, 0 ; :0 [#uses=1]
5 zext i1 %0 to i32 ; :1 [#uses=1]
6 ret i32 %1
7 }
8