llvm.org GIT mirror llvm / 426286d
[mips] seq macro support This patch adds the seq macro. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris, seanbruno Differential Revision: https://reviews.llvm.org/D24607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287573 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
3 changed file(s) with 162 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
250250
251251 bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
252252 const MCSubtargetInfo *STI, bool IsLoad);
253
254 bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
255 const MCSubtargetInfo *STI);
256
257 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
258 const MCSubtargetInfo *STI);
253259
254260 bool reportParseError(Twine ErrorMsg);
255261 bool reportParseError(SMLoc Loc, Twine ErrorMsg);
22222228 Inst.getOpcode() == Mips::LDMacro)
22232229 ? MER_Fail
22242230 : MER_Success;
2231 case Mips::SEQMacro:
2232 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2233 case Mips::SEQIMacro:
2234 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
22252235 }
22262236 }
22272237
39113921 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
39123922 }
39133923
3924 return false;
3925 }
3926
3927 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3928 const MCSubtargetInfo *STI) {
3929
3930 warnIfNoMacro(IDLoc);
3931 MipsTargetStreamer &TOut = getTargetStreamer();
3932
3933 if (Inst.getOperand(1).getReg() != Mips::ZERO &&
3934 Inst.getOperand(2).getReg() != Mips::ZERO) {
3935 TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(),
3936 Inst.getOperand(1).getReg(), Inst.getOperand(2).getReg(),
3937 IDLoc, STI);
3938 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
3939 Inst.getOperand(0).getReg(), 1, IDLoc, STI);
3940 return false;
3941 }
3942
3943 unsigned Reg = 0;
3944 if (Inst.getOperand(1).getReg() == Mips::ZERO) {
3945 Reg = Inst.getOperand(2).getReg();
3946 } else {
3947 Reg = Inst.getOperand(1).getReg();
3948 }
3949 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), Reg, 1, IDLoc, STI);
3950 return false;
3951 }
3952
3953 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3954 const MCSubtargetInfo *STI) {
3955
3956 warnIfNoMacro(IDLoc);
3957 MipsTargetStreamer &TOut = getTargetStreamer();
3958
3959 unsigned Opc;
3960 int64_t Imm = Inst.getOperand(2).getImm();
3961 unsigned Reg = Inst.getOperand(1).getReg();
3962
3963 if (Imm == 0) {
3964 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
3965 Inst.getOperand(1).getReg(), 1, IDLoc, STI);
3966 return false;
3967 } else {
3968
3969 if (Reg == Mips::ZERO) {
3970 Warning(IDLoc, "comparison is always false");
3971 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
3972 Inst.getOperand(0).getReg(), Reg, Reg, IDLoc, STI);
3973 return false;
3974 }
3975
3976 if (Imm > -0x8000 && Imm < 0) {
3977 Imm = -Imm;
3978 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
3979 } else {
3980 Opc = Mips::XORi;
3981 }
3982 }
3983 if (!isUInt<16>(Imm)) {
3984 unsigned ATReg = getATReg(IDLoc);
3985 if (!ATReg)
3986 return true;
3987
3988 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
3989 Out, STI))
3990 return true;
3991
3992 TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(),
3993 Inst.getOperand(1).getReg(), ATReg, IDLoc, STI);
3994 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
3995 Inst.getOperand(0).getReg(), 1, IDLoc, STI);
3996 return false;
3997 }
3998
3999 TOut.emitRRI(Opc, Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(),
4000 Imm, IDLoc, STI);
4001 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
4002 Inst.getOperand(0).getReg(), 1, IDLoc, STI);
39144003 return false;
39154004 }
39164005
202202 AssemblerPredicate<"FeatureMips16">;
203203 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
204204 AssemblerPredicate<"FeatureCnMips">;
205 def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
206 AssemblerPredicate<"!FeatureCnMips">;
205207 def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;
206208 def RelocPIC : Predicate<"TM.isPositionIndependent()">;
207209 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
332334
333335 class ASE_CNMIPS {
334336 list InsnPredicates = [HasCnMips];
337 }
338
339 class NOT_ASE_CNMIPS {
340 list InsnPredicates = [NotCnMips];
335341 }
336342
337343 class ASE_MIPS64_CNMIPS {
22592265 def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
22602266 "abs\t$rd, $rs">;
22612267
2268 def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2269 (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2270 "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS;
2271
2272 def : MipsInstAlias<"seq $rd, $rs",
2273 (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
2274 NOT_ASE_CNMIPS;
2275
2276 def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2277 (ins GPR32Opnd:$rs, simm32_relaxed:$imm),
2278 "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS;
2279
2280 def : MipsInstAlias<"seq $rd, $imm",
2281 (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,
2282 NOT_ASE_CNMIPS;
22622283 //===----------------------------------------------------------------------===//
22632284 // Instruction aliases
22642285 //===----------------------------------------------------------------------===//
0 # RUN: llvm-mc -arch=mips -mcpu=mips1 < %s | FileCheck --check-prefixes=ALL,MIPS32 %s
1 # RUN: llvm-mc -arch=mips -mcpu=mips64 < %s | FileCheck --check-prefixes=ALL,MIPS64 %s
2
3 # ALL: .text
4 seq $2, $11, $0
5 # ALL: sltiu $2, $11, 1
6 seq $2, $0, $11
7 # ALL: sltiu $2, $11, 1
8 seq $2, $0, $0
9 # ALL: sltiu $2, $zero, 1
10 seq $2, $11, $12
11 # ALL: xor $2, $11, $12
12 # ALL: sltiu $2, $2, 1
13 seq $2, $11, 45
14 # ALL: xori $2, $11, 45
15 seq $2, $12, 0x76666
16 # ALL: lui $1, 7
17 # ALL: ori $1, $1, 26214
18 # ALL: xor $2, $12, $1
19 # ALL: sltiu $2, $2, 1
20 seq $2, $3
21 # ALL: xor $2, $2, $3
22 # ALL: sltiu $2, $2, 1
23 seq $2, 0x8888
24 # ALL: xori $2, $2, 34952
25 # ALL: sltiu $2, $2, 1
26 seq $2, $3, -1546
27 # MIPS32: addiu $2, $3, 1546
28 # MIPS64: daddiu $2, $3, 1546
29 # ALL: sltiu $2, $2, 1
30 seq $2, -7546
31 # MIPS32: addiu $2, $2, 7546
32 # MIPS64: daddiu $2, $2, 7546
33 # ALL: sltiu $2, $2, 1
34 seq $4, $5, -66666
35 # ALL: lui $1, 65534
36 # ALL: ori $1, $1, 64406
37 # ALL: xor $4, $5, $1
38 # ALL: sltiu $4, $4, 1
39 seq $4, $5, -2147483648
40 # ALL: lui $1, 32768
41 # ALL: xor $4, $5, $1
42 # ALL: sltiu $4, $4, 1
43 seq $4, -2147483648
44 # ALL: lui $1, 32768
45 # ALL: xor $4, $4, $1
46 # ALL: sltiu $4, $4, 1
47 seq $4, $5, 0
48 # ALL: sltiu $4, $5, 1
49 seq $4, $zero, 1
50 # MIPS32: move $4, $zero
51 # MIPS64: daddu $4, $zero, $zero