llvm.org GIT mirror llvm / 421397a
Remove duplicated DMB instructions ARM specific optimiztion, finding places in ARM machine code where 2 dmbs follow one another, and eliminating one of them. Patch by Reinoud Elhorst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205409 91177308-0d34-0410-b5e6-96231b3b80d8 Renato Golin 6 years ago
5 changed file(s) with 178 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
4141 FunctionPass *createARMConstantIslandPass();
4242 FunctionPass *createMLxExpansionPass();
4343 FunctionPass *createThumb2ITBlockPass();
44 FunctionPass *createARMOptimizeBarriersPass();
4445 FunctionPass *createThumb2SizeReductionPass();
4546
4647 /// \brief Creates an ARM-specific Target Transformation Info pass.
0 //===-- ARMOptimizeBarriersPass - two DMBs without a memory access in between,
1 //removed one -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===------------------------------------------------------------------------------------------===//
9
10 #define DEBUG_TYPE "double barriers"
11
12 #include "ARM.h"
13 #include "ARMMachineFunctionInfo.h"
14 #include "ARMInstrInfo.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 using namespace llvm;
18
19 STATISTIC(NumDMBsRemoved, "Number of DMBs removed");
20
21 namespace {
22 class ARMOptimizeBarriersPass : public MachineFunctionPass {
23 public:
24 static char ID;
25 ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
26
27 virtual bool runOnMachineFunction(MachineFunction &Fn);
28
29 virtual const char *getPassName() const {
30 return "optimise barriers pass";
31 }
32
33 private:
34 };
35 char ARMOptimizeBarriersPass::ID = 0;
36 }
37
38 // Returns whether the instruction can safely move past a DMB instruction
39 // The current implementation allows this iif MI does not have any possible
40 // memory access
41 static bool CanMovePastDMB(const MachineInstr *MI) {
42 return !(MI->mayLoad() ||
43 MI->mayStore() ||
44 MI->hasUnmodeledSideEffects() ||
45 MI->isCall() ||
46 MI->isReturn());
47 }
48
49 bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
50 // Vector to store the DMBs we will remove after the first iteration
51 std::vector ToRemove;
52 // DMBType is the Imm value of the first operand. It determines whether it's a
53 // DMB ish, dmb sy, dmb osh, etc
54 int64_t DMBType = -1;
55
56 // Find a dmb. If we can move it until the next dmb, tag the second one for
57 // removal
58 for (auto &MBB : MF) {
59 // Will be true when we have seen a DMB, and not seen any instruction since
60 // that cannot move past a DMB
61 bool IsRemovableNextDMB = false;
62 for (auto &MI : MBB) {
63 if (MI.getOpcode() == ARM::DMB) {
64 if (IsRemovableNextDMB) {
65 // If the Imm of this DMB is the same as that of the last DMB, we can
66 // tag this second DMB for removal
67 if (MI.getOperand(0).getImm() == DMBType) {
68 ToRemove.push_back(&MI);
69 } else {
70 // If it has a different DMBType, we cannot remove it, but will scan
71 // for the next DMB, recording this DMB's type as last seen DMB type
72 DMBType = MI.getOperand(0).getImm();
73 }
74 } else {
75 // After we see a DMB, a next one is removable
76 IsRemovableNextDMB = true;
77 DMBType = MI.getOperand(0).getImm();
78 }
79 } else if (!CanMovePastDMB(&MI)) {
80 // If we find an instruction unable to pass past a DMB, a next DMB is
81 // not removable
82 IsRemovableNextDMB = false;
83 }
84 }
85 }
86 // Remove the tagged DMB
87 for (auto MI : ToRemove) {
88 MI->eraseFromParent();
89 ++NumDMBsRemoved;
90 }
91
92 return NumDMBsRemoved > 0;
93 }
94
95 /// createARMOptimizeBarriersPass - Returns an instance of the remove double
96 /// barriers
97 /// pass.
98 FunctionPass *llvm::createARMOptimizeBarriersPass() {
99 return new ARMOptimizeBarriersPass();
100 }
295295 addPass(&UnpackMachineBundlesID);
296296 }
297297
298 addPass(createARMOptimizeBarriersPass());
298299 addPass(createARMConstantIslandPass());
299300
300301 return true;
3333 ARMMCInstLower.cpp
3434 ARMMachineFunctionInfo.cpp
3535 ARMRegisterInfo.cpp
36 ARMOptimizeBarriersPass.cpp
3637 ARMSelectionDAGInfo.cpp
3738 ARMSubtarget.cpp
3839 ARMTargetMachine.cpp
0 ; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s
1
2 @x1 = global i32 0, align 4
3 @x2 = global i32 0, align 4
4
5 define void @test() {
6 entry:
7 br label %for.body
8
9 for.body: ; preds = %for.body, %entry
10 %i.013 = phi i32 [ 1, %entry ], [ %inc6, %for.body ]
11 store atomic i32 %i.013, i32* @x1 seq_cst, align 4
12 store atomic i32 %i.013, i32* @x1 seq_cst, align 4
13 store atomic i32 %i.013, i32* @x2 seq_cst, align 4
14 %inc6 = add nsw i32 %i.013, 1
15 %exitcond = icmp eq i32 %inc6, 2
16 br i1 %exitcond, label %for.end, label %for.body
17
18 for.end: ; preds = %for.body
19 ret void
20
21 ; The for.body contains 3 seq_cst stores.
22 ; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
23 ; CHECK: %for.body
24 ; CHECK-NOT: str
25 ; CHECK: dmb
26 ; CHECK-NOT: dmb
27 ; CHECK: str
28
29 ; CHECK-NOT: str
30 ; CHECK: dmb
31 ; CHECK-NOT: dmb
32 ; CHECK: str
33
34 ; CHECK-NOT: str
35 ; CHECK: dmb
36 ; CHECK-NOT: dmb
37 ; CHECK: str
38
39 ; CHECK-NOT: str
40 ; CHECK: dmb
41 ; CHECK-NOT: dmb
42 ; CHECK-NOT: str
43 ; CHECK: %for.end
44 }
45
46 define void @test2() {
47 call void @llvm.arm.dmb(i32 11)
48 tail call void @test()
49 call void @llvm.arm.dmb(i32 11)
50 ret void
51 ; the call should prevent the two dmbs from collapsing
52 ; CHECK: test2:
53 ; CHECK: dmb
54 ; CHECK-NEXT: bl
55 ; CHECK-NEXT: dmb
56 }
57
58 define void @test3() {
59 call void @llvm.arm.dmb(i32 11)
60 call void @llvm.arm.dsb(i32 9)
61 call void @llvm.arm.dmb(i32 11)
62 ret void
63 ; the call should prevent the two dmbs from collapsing
64 ; CHECK: test3:
65 ; CHECK: dmb
66 ; CHECK-NEXT: dsb
67 ; CHECK-NEXT: dmb
68
69 }
70
71
72 declare void @llvm.arm.dmb(i32)
73 declare void @llvm.arm.dsb(i32)