llvm.org GIT mirror llvm / 420761a
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
31 changed file(s) with 294 addition(s) and 298 deletion(s). Raw diff Collapse all Expand all
257257
258258 const TargetRegisterClass *
259259 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
260 return ARM::GPRRegisterClass;
260 return &ARM::GPRRegClass;
261261 }
262262
263263 const TargetRegisterClass *
368368 };
369369
370370 // We only support even/odd hints for GPR and rGPR.
371 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
371 if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass)
372372 return RC->getRawAllocationOrder(MF);
373373
374374 if (HintType == ARMRI::RegPairEven) {
11091109 // Must be addrmode4/6.
11101110 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
11111111 else {
1112 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1112 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
11131113 if (!AFI->isThumbFunction())
11141114 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
11151115 Offset, Pred, PredReg, TII);
15401540 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
15411541 unsigned RegD = MI.getOperand(OpIdx).getReg();
15421542 unsigned Binary = 0;
1543 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1543 bool isSPVFP = ARM::SPRRegClass.contains(RegD);
15441544 RegD = getARMRegisterNumbering(RegD);
15451545 if (!isSPVFP)
15461546 Binary |= RegD << ARMII::RegRdShift;
15541554 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
15551555 unsigned RegN = MI.getOperand(OpIdx).getReg();
15561556 unsigned Binary = 0;
1557 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1557 bool isSPVFP = ARM::SPRRegClass.contains(RegN);
15581558 RegN = getARMRegisterNumbering(RegN);
15591559 if (!isSPVFP)
15601560 Binary |= RegN << ARMII::RegRnShift;
15681568 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
15691569 unsigned RegM = MI.getOperand(OpIdx).getReg();
15701570 unsigned Binary = 0;
1571 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1571 bool isSPVFP = ARM::SPRRegClass.contains(RegM);
15721572 RegM = getARMRegisterNumbering(RegM);
15731573 if (!isSPVFP)
15741574 Binary |= RegM;
909909 // put the alloca address into a register, set the base type back to
910910 // register and continue. This should almost never happen.
911911 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
912 const TargetRegisterClass *RC = isThumb2 ? ARM::tGPRRegisterClass
913 : ARM::GPRRegisterClass;
912 const TargetRegisterClass *RC = isThumb2 ?
913 (const TargetRegisterClass*)&ARM::tGPRRegClass :
914 (const TargetRegisterClass*)&ARM::GPRRegClass;
914915 unsigned ResultReg = createResultReg(RC);
915916 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
916917 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
10041005 useAM3 = true;
10051006 }
10061007 }
1007 RC = ARM::GPRRegisterClass;
1008 RC = &ARM::GPRRegClass;
10081009 break;
10091010 case MVT::i16:
10101011 if (isThumb2) {
10161017 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
10171018 useAM3 = true;
10181019 }
1019 RC = ARM::GPRRegisterClass;
1020 RC = &ARM::GPRRegClass;
10201021 break;
10211022 case MVT::i32:
10221023 if (isThumb2) {
10271028 } else {
10281029 Opc = ARM::LDRi12;
10291030 }
1030 RC = ARM::GPRRegisterClass;
1031 RC = &ARM::GPRRegClass;
10311032 break;
10321033 case MVT::f32:
10331034 if (!Subtarget->hasVFP2()) return false;
10361037 needVMOV = true;
10371038 VT = MVT::i32;
10381039 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1039 RC = ARM::GPRRegisterClass;
1040 RC = &ARM::GPRRegClass;
10401041 } else {
10411042 Opc = ARM::VLDRS;
10421043 RC = TLI.getRegClassFor(VT);
11051106 // This is mostly going to be Neon/vector support.
11061107 default: return false;
11071108 case MVT::i1: {
1108 unsigned Res = createResultReg(isThumb2 ? ARM::tGPRRegisterClass :
1109 ARM::GPRRegisterClass);
1109 unsigned Res = createResultReg(isThumb2 ?
1110 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1111 (const TargetRegisterClass*)&ARM::GPRRegClass);
11101112 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
11111113 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
11121114 TII.get(Opc), Res)
14901492 // Now set a register based on the comparison. Explicitly set the predicates
14911493 // here.
14921494 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1493 const TargetRegisterClass *RC = isThumb2 ? ARM::rGPRRegisterClass
1494 : ARM::GPRRegisterClass;
1495 const TargetRegisterClass *RC = isThumb2 ?
1496 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1497 (const TargetRegisterClass*)&ARM::GPRRegClass;
14951498 unsigned DestReg = createResultReg(RC);
14961499 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
14971500 unsigned ZeroReg = TargetMaterializeConstant(Zero);
15151518 unsigned Op = getRegForValue(V);
15161519 if (Op == 0) return false;
15171520
1518 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1521 unsigned Result = createResultReg(&ARM::DPRRegClass);
15191522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
15201523 TII.get(ARM::VCVTDS), Result)
15211524 .addReg(Op));
15341537 unsigned Op = getRegForValue(V);
15351538 if (Op == 0) return false;
15361539
1537 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1540 unsigned Result = createResultReg(&ARM::SPRRegClass);
15381541 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
15391542 TII.get(ARM::VCVTSD), Result)
15401543 .addReg(Op));
789789 // The writeback is only needed when emitting two vst1.64 instructions.
790790 if (NumAlignedDPRCS2Regs >= 6) {
791791 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
792 ARM::QQPRRegisterClass);
792 &ARM::QQPRRegClass);
793793 MBB.addLiveIn(SupReg);
794794 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
795795 ARM::R4)
807807 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
808808 if (NumAlignedDPRCS2Regs >= 4) {
809809 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
810 ARM::QQPRRegisterClass);
810 &ARM::QQPRRegClass);
811811 MBB.addLiveIn(SupReg);
812812 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
813813 .addReg(ARM::R4).addImm(16).addReg(NextReg)
819819 // 16-byte aligned vst1.64 with 2 d-regs.
820820 if (NumAlignedDPRCS2Regs >= 2) {
821821 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
822 ARM::QPRRegisterClass);
822 &ARM::QPRRegClass);
823823 MBB.addLiveIn(SupReg);
824824 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
825825 .addReg(ARM::R4).addImm(16).addReg(SupReg));
907907 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
908908 if (NumAlignedDPRCS2Regs >= 6) {
909909 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
910 ARM::QQPRRegisterClass);
910 &ARM::QQPRRegClass);
911911 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
912912 .addReg(ARM::R4, RegState::Define)
913913 .addReg(ARM::R4, RegState::Kill).addImm(16)
923923 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
924924 if (NumAlignedDPRCS2Regs >= 4) {
925925 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
926 ARM::QQPRRegisterClass);
926 &ARM::QQPRRegClass);
927927 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
928928 .addReg(ARM::R4).addImm(16)
929929 .addReg(SupReg, RegState::ImplicitDefine));
934934 // 16-byte aligned vld1.64 with 2 d-regs.
935935 if (NumAlignedDPRCS2Regs >= 2) {
936936 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
937 ARM::QPRRegisterClass);
937 &ARM::QPRRegClass);
938938 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
939939 .addReg(ARM::R4).addImm(16));
940940 NextReg += 2;
12431243 CanEliminateFrame = false;
12441244 }
12451245
1246 if (!ARM::GPRRegisterClass->contains(Reg))
1246 if (!ARM::GPRRegClass.contains(Reg))
12471247 continue;
12481248
12491249 if (Spilled) {
14031403 } else if (!AFI->isThumb1OnlyFunction()) {
14041404 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
14051405 // closest to SP or frame pointer.
1406 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
1406 const TargetRegisterClass *RC = &ARM::GPRRegClass;
14071407 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
14081408 RC->getAlignment(),
14091409 false));
152152 }
153153
154154 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::DPRRegisterClass);
155 addRegisterClass(VT, &ARM::DPRRegClass);
156156 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157157 }
158158
159159 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
160 addRegisterClass(VT, ARM::QPRRegisterClass);
160 addRegisterClass(VT, &ARM::QPRRegClass);
161161 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162162 }
163163
430430 }
431431
432432 if (Subtarget->isThumb1Only())
433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
433 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
434434 else
435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
435 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
436436 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
437437 !Subtarget->isThumb1Only()) {
438 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
438 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
439439 if (!Subtarget->isFPOnlySP())
440 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
440 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
441441
442442 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
443443 }
848848 // the cost is 1 for both f32 and f64.
849849 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
850850 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
851 RRC = ARM::DPRRegisterClass;
851 RRC = &ARM::DPRRegClass;
852852 // When NEON is used for SP, only half of the register file is available
853853 // because operations that define both SP and DP results will be constrained
854854 // to the VFP2 class (D0-D15). We currently model this constraint prior to
858858 break;
859859 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
860860 case MVT::v4f32: case MVT::v2f64:
861 RRC = ARM::DPRRegisterClass;
861 RRC = &ARM::DPRRegClass;
862862 Cost = 2;
863863 break;
864864 case MVT::v4i64:
865 RRC = ARM::DPRRegisterClass;
865 RRC = &ARM::DPRRegClass;
866866 Cost = 4;
867867 break;
868868 case MVT::v8i64:
869 RRC = ARM::DPRRegisterClass;
869 RRC = &ARM::DPRRegClass;
870870 Cost = 8;
871871 break;
872872 }
10261026 // load / store 4 to 8 consecutive D registers.
10271027 if (Subtarget->hasNEON()) {
10281028 if (VT == MVT::v4i64)
1029 return ARM::QQPRRegisterClass;
1030 else if (VT == MVT::v8i64)
1031 return ARM::QQQQPRRegisterClass;
1029 return &ARM::QQPRRegClass;
1030 if (VT == MVT::v8i64)
1031 return &ARM::QQQQPRRegClass;
10321032 }
10331033 return TargetLowering::getRegClassFor(VT);
10341034 }
24562456
24572457 const TargetRegisterClass *RC;
24582458 if (AFI->isThumb1OnlyFunction())
2459 RC = ARM::tGPRRegisterClass;
2459 RC = &ARM::tGPRRegClass;
24602460 else
2461 RC = ARM::GPRRegisterClass;
2461 RC = &ARM::GPRRegClass;
24622462
24632463 // Transform the arguments stored in physical registers into virtual ones.
24642464 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
25422542 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
25432543 const TargetRegisterClass *RC;
25442544 if (AFI->isThumb1OnlyFunction())
2545 RC = ARM::tGPRRegisterClass;
2545 RC = &ARM::tGPRRegClass;
25462546 else
2547 RC = ARM::GPRRegisterClass;
2547 RC = &ARM::GPRRegClass;
25482548
25492549 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
25502550 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
26262626 const TargetRegisterClass *RC;
26272627
26282628 if (RegVT == MVT::f32)
2629 RC = ARM::SPRRegisterClass;
2629 RC = &ARM::SPRRegClass;
26302630 else if (RegVT == MVT::f64)
2631 RC = ARM::DPRRegisterClass;
2631 RC = &ARM::DPRRegClass;
26322632 else if (RegVT == MVT::v2f64)
2633 RC = ARM::QPRRegisterClass;
2633 RC = &ARM::QPRRegClass;
26342634 else if (RegVT == MVT::i32)
2635 RC = (AFI->isThumb1OnlyFunction() ?
2636 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2635 RC = AFI->isThumb1OnlyFunction() ?
2636 (const TargetRegisterClass*)&ARM::tGPRRegClass :
2637 (const TargetRegisterClass*)&ARM::GPRRegClass;
26372638 else
26382639 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
26392640
52515252 bool isThumb2 = Subtarget->isThumb2();
52525253
52535254 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5254 unsigned scratch =
5255 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
5256 : ARM::GPRRegisterClass);
5255 unsigned scratch = MRI.createVirtualRegister(isThumb2 ?
5256 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5257 (const TargetRegisterClass*)&ARM::GPRRegClass);
52575258
52585259 if (isThumb2) {
5259 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5260 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
5261 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
5260 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5261 MRI.constrainRegClass(oldval, &ARM::rGPRRegClass);
5262 MRI.constrainRegClass(newval, &ARM::rGPRRegClass);
52625263 }
52635264
52645265 unsigned ldrOpc, strOpc;
53615362
53625363 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
53635364 if (isThumb2) {
5364 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5365 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5365 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5366 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
53665367 }
53675368
53685369 unsigned ldrOpc, strOpc;
53935394 BB->end());
53945395 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
53955396
5396 const TargetRegisterClass *TRC =
5397 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5397 const TargetRegisterClass *TRC = isThumb2 ?
5398 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5399 (const TargetRegisterClass*)&ARM::GPRRegClass;
53985400 unsigned scratch = MRI.createVirtualRegister(TRC);
53995401 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
54005402
54685470
54695471 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
54705472 if (isThumb2) {
5471 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5472 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5473 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5474 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
54735475 }
54745476
54755477 unsigned ldrOpc, strOpc, extendOpc;
55035505 BB->end());
55045506 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
55055507
5506 const TargetRegisterClass *TRC =
5507 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5508 const TargetRegisterClass *TRC = isThumb2 ?
5509 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5510 (const TargetRegisterClass*)&ARM::GPRRegClass;
55085511 unsigned scratch = MRI.createVirtualRegister(TRC);
55095512 unsigned scratch2 = MRI.createVirtualRegister(TRC);
55105513
55305533
55315534 // Sign extend the value, if necessary.
55325535 if (signExtend && extendOpc) {
5533 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5536 oldval = MRI.createVirtualRegister(&ARM::GPRRegClass);
55345537 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
55355538 .addReg(dest)
55365539 .addImm(0));
55855588
55865589 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
55875590 if (isThumb2) {
5588 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
5589 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
5590 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5591 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
5592 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
5593 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
55915594 }
55925595
55935596 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
56135616 BB->end());
56145617 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
56155618
5616 const TargetRegisterClass *TRC =
5617 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5619 const TargetRegisterClass *TRC = isThumb2 ?
5620 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5621 (const TargetRegisterClass*)&ARM::GPRRegClass;
56185622 unsigned storesuccess = MRI.createVirtualRegister(TRC);
56195623
56205624 // thisMBB:
57215725 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
57225726 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
57235727
5724 const TargetRegisterClass *TRC =
5725 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5728 const TargetRegisterClass *TRC = isThumb ?
5729 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5730 (const TargetRegisterClass*)&ARM::GPRRegClass;
57265731
57275732 // Grab constant pool and fixed stack memory operands.
57285733 MachineMemOperand *CPMMO =
58265831 MachineFrameInfo *MFI = MF->getFrameInfo();
58275832 int FI = MFI->getFunctionContextIndex();
58285833
5829 const TargetRegisterClass *TRC =
5830 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5834 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
5835 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5836 (const TargetRegisterClass*)&ARM::GPRRegClass;
58315837
58325838 // Get a mapping of the call site numbers to all of the landing pads they're
58335839 // associated with.
61756181 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
61766182 unsigned Reg = SavedRegs[i];
61776183 if (Subtarget->isThumb2() &&
6178 !ARM::tGPRRegisterClass->contains(Reg) &&
6179 !ARM::hGPRRegisterClass->contains(Reg))
6184 !ARM::tGPRRegClass.contains(Reg) &&
6185 !ARM::hGPRRegClass.contains(Reg))
61806186 continue;
6181 else if (Subtarget->isThumb1Only() &&
6182 !ARM::tGPRRegisterClass->contains(Reg))
6187 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
61836188 continue;
6184 else if (!Subtarget->isThumb() &&
6185 !ARM::GPRRegisterClass->contains(Reg))
6189 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
61866190 continue;
61876191 if (!DefRegs[Reg])
61886192 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
65166520 MachineRegisterInfo &MRI = Fn->getRegInfo();
65176521 // In Thumb mode S must not be specified if source register is the SP or
65186522 // PC and if destination register is the SP, so restrict register class
6519 unsigned NewMovDstReg = MRI.createVirtualRegister(
6520 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6521 unsigned NewRsbDstReg = MRI.createVirtualRegister(
6522 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6523 unsigned NewMovDstReg = MRI.createVirtualRegister(isThumb2 ?
6524 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6525 (const TargetRegisterClass*)&ARM::GPRRegClass);
6526 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
6527 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6528 (const TargetRegisterClass*)&ARM::GPRRegClass);
65236529
65246530 // Transfer the remainder of BB and its successor edges to sinkMBB.
65256531 SinkBB->splice(SinkBB->begin(), BB,
90299035 switch (Constraint[0]) {
90309036 case 'l': // Low regs or general regs.
90319037 if (Subtarget->isThumb())
9032 return RCPair(0U, ARM::tGPRRegisterClass);
9033 else
9034 return RCPair(0U, ARM::GPRRegisterClass);
9038 return RCPair(0U, &ARM::tGPRRegClass);
9039 return RCPair(0U, &ARM::GPRRegClass);
90359040 case 'h': // High regs or no regs.
90369041 if (Subtarget->isThumb())
9037 return RCPair(0U, ARM::hGPRRegisterClass);
9042 return RCPair(0U, &ARM::hGPRRegClass);
90389043 break;
90399044 case 'r':
9040 return RCPair(0U, ARM::GPRRegisterClass);
9045 return RCPair(0U, &ARM::GPRRegClass);
90419046 case 'w':
90429047 if (VT == MVT::f32)
9043 return RCPair(0U, ARM::SPRRegisterClass);
9048 return RCPair(0U, &ARM::SPRRegClass);
90449049 if (VT.getSizeInBits() == 64)
9045 return RCPair(0U, ARM::DPRRegisterClass);
9050 return RCPair(0U, &ARM::DPRRegClass);
90469051 if (VT.getSizeInBits() == 128)
9047 return RCPair(0U, ARM::QPRRegisterClass);
9052 return RCPair(0U, &ARM::QPRRegClass);
90489053 break;
90499054 case 'x':
90509055 if (VT == MVT::f32)
9051 return RCPair(0U, ARM::SPR_8RegisterClass);
9056 return RCPair(0U, &ARM::SPR_8RegClass);
90529057 if (VT.getSizeInBits() == 64)
9053 return RCPair(0U, ARM::DPR_8RegisterClass);
9058 return RCPair(0U, &ARM::DPR_8RegClass);
90549059 if (VT.getSizeInBits() == 128)
9055 return RCPair(0U, ARM::QPR_8RegisterClass);
9060 return RCPair(0U, &ARM::QPR_8RegClass);
90569061 break;
90579062 case 't':
90589063 if (VT == MVT::f32)
9059 return RCPair(0U, ARM::SPRRegisterClass);
9064 return RCPair(0U, &ARM::SPRRegClass);
90609065 break;
90619066 }
90629067 }
90639068 if (StringRef("{cc}").equals_lower(Constraint))
9064 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
9069 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
90659070
90669071 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
90679072 }
13251325 // First advance to the instruction just before the start of the chain.
13261326 AdvanceRS(MBB, MemOps);
13271327 // Find a scratch register.
1328 unsigned Scratch = RS->FindUnusedReg(ARM::GPRRegisterClass);
1328 unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass);
13291329 // Process the load / store instructions.
13301330 RS->forward(prior(MBBI));
13311331
5252 unsigned SrcReg, bool isKill, int FI,
5353 const TargetRegisterClass *RC,
5454 const TargetRegisterInfo *TRI) const {
55 assert((RC == ARM::tGPRRegisterClass ||
55 assert((RC == &ARM::tGPRRegClass ||
5656 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
5757 isARMLowRegister(SrcReg))) && "Unknown regclass!");
5858
59 if (RC == ARM::tGPRRegisterClass ||
59 if (RC == &ARM::tGPRRegClass ||
6060 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
6161 isARMLowRegister(SrcReg))) {
6262 DebugLoc DL;
8080 unsigned DestReg, int FI,
8181 const TargetRegisterClass *RC,
8282 const TargetRegisterInfo *TRI) const {
83 assert((RC == ARM::tGPRRegisterClass ||
83 assert((RC == &ARM::tGPRRegClass ||
8484 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
8585 isARMLowRegister(DestReg))) && "Unknown regclass!");
8686
87 if (RC == ARM::tGPRRegisterClass ||
87 if (RC == &ARM::tGPRRegClass ||
8888 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
8989 isARMLowRegister(DestReg))) {
9090 DebugLoc DL;
4848 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
4949 const {
5050 if (ARM::tGPRRegClass.hasSubClassEq(RC))
51 return ARM::tGPRRegisterClass;
51 return &ARM::tGPRRegClass;
5252 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
5353 }
5454
5555 const TargetRegisterClass *
5656 Thumb1RegisterInfo::getPointerRegClass(unsigned Kind) const {
57 return ARM::tGPRRegisterClass;
57 return &ARM::tGPRRegClass;
5858 }
5959
6060 /// emitLoadConstPool - Emits a load from constpool to materialize the
108108 unsigned LdReg = DestReg;
109109 if (DestReg == ARM::SP) {
110110 assert(BaseReg == ARM::SP && "Unexpected!");
111 LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
111 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
112112 }
113113
114114 if (NumBytes <= 255 && NumBytes >= 0)
692692 // register. The offset is already handled in the vreg value.
693693 MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
694694 } else if (MI.mayStore()) {
695 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
695 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
696696 bool UseRR = false;
697697
698698 if (Opcode == ARM::tSTRspi) {
125125 unsigned SrcReg, bool isKill, int FI,
126126 const TargetRegisterClass *RC,
127127 const TargetRegisterInfo *TRI) const {
128 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
129 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
130 RC == ARM::GPRnopcRegisterClass) {
128 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
129 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
130 RC == &ARM::GPRnopcRegClass) {
131131 DebugLoc DL;
132132 if (I != MBB.end()) DL = I->getDebugLoc();
133133
152152 unsigned DestReg, int FI,
153153 const TargetRegisterClass *RC,
154154 const TargetRegisterInfo *TRI) const {
155 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
156 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
157 RC == ARM::GPRnopcRegisterClass) {
155 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
156 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
157 RC == &ARM::GPRnopcRegClass) {
158158 DebugLoc DL;
159159 if (I != MBB.end()) DL = I->getDebugLoc();
160160
9999 setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
100100
101101 // Set up the SPU's register classes:
102 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
103 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
104 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
105 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
106 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
107 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
108 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
102 addRegisterClass(MVT::i8, &SPU::R8CRegClass);
103 addRegisterClass(MVT::i16, &SPU::R16CRegClass);
104 addRegisterClass(MVT::i32, &SPU::R32CRegClass);
105 addRegisterClass(MVT::i64, &SPU::R64CRegClass);
106 addRegisterClass(MVT::f32, &SPU::R32FPRegClass);
107 addRegisterClass(MVT::f64, &SPU::R64FPRegClass);
108 addRegisterClass(MVT::i128, &SPU::GPRCRegClass);
109109
110110 // SPU has no sign or zero extended loads for i1, i8, i16:
111111 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
396396
397397 // First set operation action for all vector types to expand. Then we
398398 // will selectively turn on ones that can be effectively codegen'd.
399 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
400 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
401 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
402 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
403 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
404 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
399 addRegisterClass(MVT::v16i8, &SPU::VECREGRegClass);
400 addRegisterClass(MVT::v8i16, &SPU::VECREGRegClass);
401 addRegisterClass(MVT::v4i32, &SPU::VECREGRegClass);
402 addRegisterClass(MVT::v2i64, &SPU::VECREGRegClass);
403 addRegisterClass(MVT::v4f32, &SPU::VECREGRegClass);
404 addRegisterClass(MVT::v2f64, &SPU::VECREGRegClass);
405405
406406 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
407407 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
31383138 case 'b': // R1-R31
31393139 case 'r': // R0-R31
31403140 if (VT == MVT::i64)
3141 return std::make_pair(0U, SPU::R64CRegisterClass);
3142 return std::make_pair(0U, SPU::R32CRegisterClass);
3141 return std::make_pair(0U, &SPU::R64CRegClass);
3142 return std::make_pair(0U, &SPU::R32CRegClass);
31433143 case 'f':
31443144 if (VT == MVT::f32)
3145 return std::make_pair(0U, SPU::R32FPRegisterClass);
3146 else if (VT == MVT::f64)
3147 return std::make_pair(0U, SPU::R64FPRegisterClass);
3145 return std::make_pair(0U, &SPU::R32FPRegClass);
3146 if (VT == MVT::f64)
3147 return std::make_pair(0U, &SPU::R64FPRegClass);
31483148 break;
31493149 case 'v':
3150 return std::make_pair(0U, SPU::GPRCRegisterClass);
3150 return std::make_pair(0U, &SPU::GPRCRegClass);
31513151 }
31523152 }
31533153
142142 const TargetRegisterInfo *TRI) const {
143143 unsigned opc;
144144 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
145 if (RC == SPU::GPRCRegisterClass)
145 if (RC == &SPU::GPRCRegClass)
146146 opc = isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128;
147 else if (RC == SPU::R64CRegisterClass)
147 else if (RC == &SPU::R64CRegClass)
148148 opc = isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64;
149 else if (RC == SPU::R64FPRegisterClass)
149 else if (RC == &SPU::R64FPRegClass)
150150 opc = isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64;
151 else if (RC == SPU::R32CRegisterClass)
151 else if (RC == &SPU::R32CRegClass)
152152 opc = isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32;
153 else if (RC == SPU::R32FPRegisterClass)
153 else if (RC == &SPU::R32FPRegClass)
154154 opc = isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32;
155 else if (RC == SPU::R16CRegisterClass)
155 else if (RC == &SPU::R16CRegClass)
156156 opc = isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16;
157 else if (RC == SPU::R8CRegisterClass)
157 else if (RC == &SPU::R8CRegClass)
158158 opc = isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8;
159 else if (RC == SPU::VECREGRegisterClass)
159 else if (RC == &SPU::VECREGRegClass)
160160 opc = isValidFrameIdx ? SPU::STQDv16i8 : SPU::STQXv16i8;
161161 else
162162 llvm_unreachable("Unknown regclass!");
175175 const TargetRegisterInfo *TRI) const {
176176 unsigned opc;
177177 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
178 if (RC == SPU::GPRCRegisterClass)
178 if (RC == &SPU::GPRCRegClass)
179179 opc = isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128;
180 else if (RC == SPU::R64CRegisterClass)
180 else if (RC == &SPU::R64CRegClass)
181181 opc = isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64;
182 else if (RC == SPU::R64FPRegisterClass)
182 else if (RC == &SPU::R64FPRegClass)
183183 opc = isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64;
184 else if (RC == SPU::R32CRegisterClass)
184 else if (RC == &SPU::R32CRegClass)
185185 opc = isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32;
186 else if (RC == SPU::R32FPRegisterClass)
186 else if (RC == &SPU::R32FPRegClass)
187187 opc = isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32;
188 else if (RC == SPU::R16CRegisterClass)
188 else if (RC == &SPU::R16CRegClass)
189189 opc = isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16;
190 else if (RC == SPU::R8CRegisterClass)
190 else if (RC == &SPU::R8CRegClass)
191191 opc = isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8;
192 else if (RC == SPU::VECREGRegisterClass)
192 else if (RC == &SPU::VECREGRegClass)
193193 opc = isValidFrameIdx ? SPU::LQDv16i8 : SPU::LQXv16i8;
194194 else
195195 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
622622 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
623623 MachineBasicBlock *MBB = MII->getParent();
624624 DebugLoc DL = MII->getDebugLoc();
625 unsigned Scratch = RS.scavengeRegister(Hexagon::IntRegsRegisterClass, MII, 0);
625 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
626626
627627 // First, set the LC0 with the trip count.
628628 if (MII->getOperand(1).isReg()) {
11291129 SDNode *Arg = N->getOperand(i).getNode();
11301130 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
11311131
1132 if (RC == Hexagon::IntRegsRegisterClass ||
1133 RC == Hexagon::DoubleRegsRegisterClass) {
1132 if (RC == &Hexagon::IntRegsRegClass ||
1133 RC == &Hexagon::DoubleRegsRegClass) {
11341134 Ops.push_back(SDValue(Arg, 0));
1135 } else if (RC == Hexagon::PredRegsRegisterClass) {
1135 } else if (RC == &Hexagon::PredRegsRegClass) {
11361136 // Do the transfer.
11371137 SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
11381138 SDValue(Arg, 0));
838838 EVT RegVT = VA.getLocVT();
839839 if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
840840 unsigned VReg =
841 RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass);
841 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
842842 RegInfo.addLiveIn(VA.getLocReg(), VReg);
843843 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
844844 } else if (RegVT == MVT::i64) {
845845 unsigned VReg =
846 RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass);
846 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
847847 RegInfo.addLiveIn(VA.getLocReg(), VReg);
848848 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
849849 } else {
10081008 TM(targetmachine) {
10091009
10101010 // Set up the register classes.
1011 addRegisterClass(MVT::i32, Hexagon::IntRegsRegisterClass);
1012 addRegisterClass(MVT::i64, Hexagon::DoubleRegsRegisterClass);
1013
1014 addRegisterClass(MVT::i1, Hexagon::PredRegsRegisterClass);
1011 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1012 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1013
1014 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
10151015
10161016 computeRegisterProperties();
10171017
14011401 case MVT::i32:
14021402 case MVT::i16:
14031403 case MVT::i8:
1404 return std::make_pair(0U, Hexagon::IntRegsRegisterClass);
1404 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
14051405 case MVT::i64:
1406 return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
1406 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
14071407 }
14081408 default:
14091409 llvm_unreachable("Unknown asm register class");
369369 MFI.getObjectSize(FI),
370370 Align);
371371
372 if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) {
372 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
373373 BuildMI(MBB, I, DL, get(Hexagon::STriw))
374374 .addFrameIndex(FI).addImm(0)
375375 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
376 } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) {
376 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
377377 BuildMI(MBB, I, DL, get(Hexagon::STrid))
378378 .addFrameIndex(FI).addImm(0)
379379 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
380 } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) {
380 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
381381 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
382382 .addFrameIndex(FI).addImm(0)
383383 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
415415 MFI.getObjectSize(FI),
416416 Align);
417417
418 if (RC == Hexagon::IntRegsRegisterClass) {
418 if (RC == &Hexagon::IntRegsRegClass) {
419419 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
420420 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
421 } else if (RC == Hexagon::DoubleRegsRegisterClass) {
421 } else if (RC == &Hexagon::DoubleRegsRegClass) {
422422 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
423423 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
424 } else if (RC == Hexagon::PredRegsRegisterClass) {
424 } else if (RC == &Hexagon::PredRegsRegClass) {
425425 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
426426 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
427427 } else {
451451
452452 MachineRegisterInfo &RegInfo = MF->getRegInfo();
453453 const TargetRegisterClass *TRC;
454 if (VT == MVT::i1) {
455 TRC = Hexagon::PredRegsRegisterClass;
456 } else if (VT == MVT::i32) {
457 TRC = Hexagon::IntRegsRegisterClass;
458 } else if (VT == MVT::i64) {
459 TRC = Hexagon::DoubleRegsRegisterClass;
460 } else {
454 if (VT == MVT::i1)
455 TRC = &Hexagon::PredRegsRegClass;
456 else if (VT == MVT::i32)
457 TRC = &Hexagon::IntRegsRegClass;
458 else if (VT == MVT::i64)
459 TRC = &Hexagon::DoubleRegsRegClass;
460 else
461461 llvm_unreachable("Cannot handle this register class");
462 }
463462
464463 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
465464 return NewReg;
13301329 MachineOperand MO = MI->getOperand(oper);
13311330 if (MO.isReg() && MO.isDef()) {
13321331 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1333 if (RC == Hexagon::PredRegsRegisterClass) {
1332 if (RC == &Hexagon::PredRegsRegClass) {
13341333 Pred.push_back(MO);
13351334 return true;
13361335 }
134134 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
135135 unsigned Reg = CSI[i].getReg();
136136 unsigned RegNum = getMBlazeRegisterNumbering(Reg);
137 if (MBlaze::GPRRegisterClass->contains(Reg))
137 if (MBlaze::GPRRegClass.contains(Reg))
138138 CPUBitmask |= (1 << RegNum);
139139 }
140140
6161 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
6262
6363 // Set up the register classes
64 addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
64 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass);
6565 if (Subtarget->hasFPU()) {
66 addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
66 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass);
6767 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
6868 }
6969
290290 loop->addSuccessor(finish);
291291 loop->addSuccessor(loop);
292292
293 unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
293 unsigned IAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
294294 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
295295 .addReg(MI->getOperand(2).getReg())
296296 .addImm(31);
297297
298 unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
298 unsigned IVAL = R.createVirtualRegister(&MBlaze::GPRRegClass);
299299 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
300300 .addReg(MI->getOperand(1).getReg())
301301 .addImm(0);
304304 .addReg(IAMT)
305305 .addMBB(finish);
306306
307 unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
308 unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
307 unsigned DST = R.createVirtualRegister(&MBlaze::GPRRegClass);
308 unsigned NDST = R.createVirtualRegister(&MBlaze::GPRRegClass);
309309 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
310310 .addReg(IVAL).addMBB(MBB)
311311 .addReg(NDST).addMBB(loop);
312312
313 unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
314 unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
313 unsigned SAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
314 unsigned NAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
315315 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
316316 .addReg(IAMT).addMBB(MBB)
317317 .addReg(NAMT).addMBB(loop);
499499 case MBlaze::LAN32: opcode = MBlaze::AND; break;
500500 }
501501
502 finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
502 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass);
503503 start->addSuccessor(exit);
504504 start->addSuccessor(start);
505505
509509
510510 if (MI->getOpcode() == MBlaze::LAN32) {
511511 unsigned tmp = finalReg;
512 finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
512 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass);
513513 BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg)
514514 .addReg(tmp)
515515 .addImm(-1);
527527 final->addSuccessor(exit);
528528 final->addSuccessor(start);
529529
530 unsigned CMP = R.createVirtualRegister(MBlaze::GPRRegisterClass);
530 unsigned CMP = R.createVirtualRegister(&MBlaze::GPRRegClass);
531531 BuildMI(start, dl, TII->get(MBlaze::CMP), CMP)
532532 .addReg(MI->getOperand(0).getReg())
533533 .addReg(MI->getOperand(2).getReg());
542542 }
543543 }
544544
545 unsigned CHK = R.createVirtualRegister(MBlaze::GPRRegisterClass);
545 unsigned CHK = R.createVirtualRegister(&MBlaze::GPRRegClass);
546546 BuildMI(final, dl, TII->get(MBlaze::SWX))
547547 .addReg(finalReg)
548548 .addReg(MI->getOperand(1).getReg())
898898 const TargetRegisterClass *RC;
899899
900900 if (RegVT == MVT::i32)
901 RC = MBlaze::GPRRegisterClass;
901 RC = &MBlaze::GPRRegClass;
902902 else if (RegVT == MVT::f32)
903 RC = MBlaze::GPRRegisterClass;
903 RC = &MBlaze::GPRRegClass;
904904 else
905905 llvm_unreachable("RegVT not supported by LowerFormalArguments");
906906
963963 StackPtr = DAG.getRegister(StackReg, getPointerTy());
964964
965965 // The last register argument that must be saved is MBlaze::R10
966 const TargetRegisterClass *RC = MBlaze::GPRRegisterClass;
966 const TargetRegisterClass *RC = &MBlaze::GPRRegClass;
967967
968968 unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5);
969969 unsigned Start = getMBlazeRegisterNumbering(ArgRegEnd+1);
11231123 if (Constraint.size() == 1) {
11241124 switch (Constraint[0]) {
11251125 case 'r':
1126 return std::make_pair(0U, MBlaze::GPRRegisterClass);
1126 return std::make_pair(0U, &MBlaze::GPRRegClass);
11271127 // TODO: These can't possibly be right, but match what was in
11281128 // getRegClassForInlineAsmConstraint.
11291129 case 'd':
11301130 case 'y':
11311131 case 'f':
11321132 if (VT == MVT::f32)
1133 return std::make_pair(0U, MBlaze::GPRRegisterClass);
1133 return std::make_pair(0U, &MBlaze::GPRRegClass);
11341134 }
11351135 }
11361136 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
286286 MachineRegisterInfo &RegInfo = MF->getRegInfo();
287287 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
288288
289 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::GPRRegisterClass);
289 GlobalBaseReg = RegInfo.createVirtualRegister(&MBlaze::GPRRegClass);
290290 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
291291 GlobalBaseReg).addReg(MBlaze::R20);
292292 RegInfo.addLiveIn(MBlaze::R20);
6363 TD = getTargetData();
6464
6565 // Set up the register classes.
66 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
67 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
66 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
67 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
6868
6969 // Compute derived properties from the register classes
7070 computeRegisterProperties();
225225 default: break;
226226 case 'r': // GENERAL_REGS
227227 if (VT == MVT::i8)
228 return std::make_pair(0U, MSP430::GR8RegisterClass);
229
230 return std::make_pair(0U, MSP430::GR16RegisterClass);
228 return std::make_pair(0U, &MSP430::GR8RegClass);
229
230 return std::make_pair(0U, &MSP430::GR16RegClass);
231231 }
232232 }
233233
329329 llvm_unreachable(0);
330330 }
331331 case MVT::i16:
332 unsigned VReg =
333 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
332 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
334333 RegInfo.addLiveIn(VA.getLocReg(), VReg);
335334 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
336335
10231022 default: llvm_unreachable("Invalid shift opcode!");
10241023 case MSP430::Shl8:
10251024 Opc = MSP430::SHL8r1;
1026 RC = MSP430::GR8RegisterClass;
1025 RC = &MSP430::GR8RegClass;
10271026 break;
10281027 case MSP430::Shl16:
10291028 Opc = MSP430::SHL16r1;
1030 RC = MSP430::GR16RegisterClass;
1029 RC = &MSP430::GR16RegClass;
10311030 break;
10321031 case MSP430::Sra8:
10331032 Opc = MSP430::SAR8r1;
1034 RC = MSP430::GR8RegisterClass;
1033 RC = &MSP430::GR8RegClass;
10351034 break;
10361035 case MSP430::Sra16:
10371036 Opc = MSP430::SAR16r1;
1038 RC = MSP430::GR16RegisterClass;
1037 RC = &MSP430::GR16RegClass;
10391038 break;
10401039 case MSP430::Srl8:
10411040 Opc = MSP430::SAR8r1c;
1042 RC = MSP430::GR8RegisterClass;
1041 RC = &MSP430::GR8RegClass;
10431042 break;
10441043 case MSP430::Srl16:
10451044 Opc = MSP430::SAR16r1c;
1046 RC = MSP430::GR16RegisterClass;
1045 RC = &MSP430::GR16RegClass;
10471046 break;
10481047 }
10491048
10711070 LoopBB->addSuccessor(RemBB);
10721071 LoopBB->addSuccessor(LoopBB);
10731072
1074 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1075 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1073 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1074 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
10761075 unsigned ShiftReg = RI.createVirtualRegister(RC);
10771076 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
10781077 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
196196 const MachineFrameInfo *MFI = MF->getFrameInfo();
197197 const std::vector &CSI = MFI->getCalleeSavedInfo();
198198 // size of stack area to which FP callee-saved regs are saved.
199 unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
200 unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
201 unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
199 unsigned CPURegSize = Mips::CPURegsRegClass.getSize();
200 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
201 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
202202 bool HasAFGR64Reg = false;
203203 unsigned CSFPRegsSize = 0;
204204 unsigned i, e = CSI.size();
206206 // Set FPU Bitmask.
207207 for (i = 0; i != e; ++i) {
208208 unsigned Reg = CSI[i].getReg();
209 if (Mips::CPURegsRegisterClass->contains(Reg))
209 if (Mips::CPURegsRegClass.contains(Reg))
210210 break;
211211
212212 unsigned RegNum = getMipsRegisterNumbering(Reg);
213 if (Mips::AFGR64RegisterClass->contains(Reg)) {
213 if (Mips::AFGR64RegClass.contains(Reg)) {
214214 FPUBitmask |= (3 << RegNum);
215215 CSFPRegsSize += AFGR64RegSize;
216216 HasAFGR64Reg = true;
216216
217217 // If Reg is a double precision register, emit two cfa_offsets,
218218 // one for each of the paired single precision registers.
219 if (Mips::AFGR64RegisterClass->contains(Reg)) {
219 if (Mips::AFGR64RegClass.contains(Reg)) {
220220 const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg);
221221 MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
222222 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
228228
229229 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
230230 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
231 }
232 else {
231 } else {
233232 // Reg is either in CPURegs or FGR32.
234233 DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
235234 SrcML = MachineLocation(Reg);
133133 else {
134134 const TargetRegisterClass *RC;
135135 RC = Subtarget.isABI_N64() ?
136 Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
136 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
137 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
137138
138139 V0 = RegInfo.createVirtualRegister(RC);
139140 V1 = RegInfo.createVirtualRegister(RC);
9595 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
9696
9797 // Set up the register classes
98 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
98 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
9999
100100 if (HasMips64)
101 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
101 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
102102
103103 if (!TM.Options.UseSoftFloat) {
104 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
104 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
105105
106106 // When dealing with single precision only, use libcalls
107107 if (!Subtarget->isSingleFloat()) {
108108 if (HasMips64)
109 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
109 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110110 else
111 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
111 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
112112 }
113113 }
114114
26652665 break;
26662666
26672667 unsigned SrcReg = O32IntRegs[CurWord];
2668 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
2668 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
26692669 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
26702670 DAG.getConstant(i * 4, MVT::i32));
26712671 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
27022702 // Copy arg registers.
27032703 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
27042704 ++Reg, ++I) {
2705 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass);
2705 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
27062706 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
27072707 DAG.getConstant(I * 8, PtrTy));
27082708 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
27782778 const TargetRegisterClass *RC;
27792779
27802780 if (RegVT == MVT::i32)
2781 RC = Mips::CPURegsRegisterClass;
2781 RC = &Mips::CPURegsRegClass;
27822782 else if (RegVT == MVT::i64)
2783 RC = Mips::CPU64RegsRegisterClass;
2783 RC = &Mips::CPU64RegsRegClass;
27842784 else if (RegVT == MVT::f32)
2785 RC = Mips::FGR32RegisterClass;
2785 RC = &Mips::FGR32RegClass;
27862786 else if (RegVT == MVT::f64)
2787 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass;
2787 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
27882788 else
27892789 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
27902790
28582858 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
28592859 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
28602860 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
2861 const TargetRegisterClass *RC
2862 = IsO32 ? Mips::CPURegsRegisterClass : Mips::CPU64RegsRegisterClass;
2861 const TargetRegisterClass *RC = IsO32 ?
2862 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
2863 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
28632864 unsigned RegSize = RC->getSize();
28642865 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
28652866
30483049 case 'y': // Same as 'r'. Exists for compatibility.
30493050 case 'r':
30503051 if (VT == MVT::i32)
3051 return std::make_pair(0U, Mips::CPURegsRegisterClass);
3052 return std::make_pair(0U, &Mips::CPURegsRegClass);
30523053 assert(VT == MVT::i64 && "Unexpected type.");
3053 return std::make_pair(0U, Mips::CPU64RegsRegisterClass);
3054 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
30543055 case 'f':
30553056 if (VT == MVT::f32)
3056 return std::make_pair(0U, Mips::FGR32RegisterClass);
3057 return std::make_pair(0U, &Mips::FGR32RegClass);
30573058 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
30583059 if (Subtarget->isFP64bit())
3059 return std::make_pair(0U, Mips::FGR64RegisterClass);
3060 else
3061 return std::make_pair(0U, Mips::AFGR64RegisterClass);
3060 return std::make_pair(0U, &Mips::FGR64RegClass);
3061 return std::make_pair(0U, &Mips::AFGR64RegClass);
30623062 }
30633063 }
30643064 }
188188
189189 unsigned Opc = 0;
190190
191 if (RC == Mips::CPURegsRegisterClass)
191 if (RC == &Mips::CPURegsRegClass)
192192 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
193 else if (RC == Mips::CPU64RegsRegisterClass)
193 else if (RC == &Mips::CPU64RegsRegClass)
194194 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
195 else if (RC == Mips::FGR32RegisterClass)
195 else if (RC == &Mips::FGR32RegClass)
196196 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
197 else if (RC == Mips::AFGR64RegisterClass)
197 else if (RC == &Mips::AFGR64RegClass)
198198 Opc = Mips::SDC1;
199 else if (RC == Mips::FGR64RegisterClass)
199 else if (RC == &Mips::FGR64RegClass)
200200 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
201201
202202 assert(Opc && "Register class not handled!");
215215 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
216216 unsigned Opc = 0;
217217
218 if (RC == Mips::CPURegsRegisterClass)
218 if (RC == &Mips::CPURegsRegClass)
219219 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
220 else if (RC == Mips::CPU64RegsRegisterClass)
220 else if (RC == &Mips::CPU64RegsRegClass)
221221 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
222 else if (RC == Mips::FGR32RegisterClass)
222 else if (RC == &Mips::FGR32RegClass)
223223 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
224 else if (RC == Mips::AFGR64RegisterClass)
224 else if (RC == &Mips::AFGR64RegClass)
225225 Opc = Mips::LDC1;
226 else if (RC == Mips::FGR64RegisterClass)
226 else if (RC == &Mips::FGR64RegClass)
227227 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
228228
229229 assert(Opc && "Register class not handled!");
3939 if (FixGlobalBaseReg) // $gp is the global base register.
4040 return GlobalBaseReg = ST.isABI_N64() ? Mips::GP_64 : Mips::GP;
4141
42 const TargetRegisterClass *RC;
43 RC = ST.isABI_N64() ?
44 Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
42 const TargetRegisterClass *RC = ST.isABI_N64() ?
43 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
44 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
4545
4646 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
4747 }
9393 };
9494
9595 BitVector Reserved(getNumRegs());
96 typedef TargetRegisterClass::iterator RegIter;
96 typedef TargetRegisterClass::const_iterator RegIter;
9797
9898 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
9999 Reserved.set(ReservedCPURegs[I]);
103103 Reserved.set(ReservedCPU64Regs[I]);
104104
105105 // Reserve all registers in AFGR64.
106 for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
107 Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
106 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
107 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
108108 Reserved.set(*Reg);
109 }
110 else {
109 } else {
111110 // Reserve all registers in CPU64Regs & FGR64.
112 for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
113 Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
111 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
112 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
114113 Reserved.set(*Reg);
115114
116 for (RegIter Reg = Mips::FGR64RegisterClass->begin();
117 Reg != Mips::FGR64RegisterClass->end(); ++Reg)
115 for (RegIter Reg = Mips::FGR64RegClass.begin(),
116 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
118117 Reserved.set(*Reg);
119118 }
120119
3535 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
3636 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
3737 // Set up the register classes.
38 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
39 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
40 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
41 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
42 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
43 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
38 addRegisterClass(MVT::i1, &PTX::RegPredRegClass);
39 addRegisterClass(MVT::i16, &PTX::RegI16RegClass);
40 addRegisterClass(MVT::i32, &PTX::RegI32RegClass);
41 addRegisterClass(MVT::i64, &PTX::RegI64RegClass);
42 addRegisterClass(MVT::f32, &PTX::RegF32RegClass);
43 addRegisterClass(MVT::f64, &PTX::RegF64RegClass);
4444
4545 setBooleanContents(ZeroOrOneBooleanContent);
4646 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
327327 }
328328 } else {
329329 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
330 EVT RegVT = Outs[i].VT;
330 EVT RegVT = Outs[i].VT;
331331 const TargetRegisterClass* TRC;
332 unsigned RegType;
332 unsigned RegType;
333333
334334 // Determine which register class we need
335335 if (RegVT == MVT::i1) {
336 TRC = PTX::RegPredRegisterClass;
336 TRC = &PTX::RegPredRegClass;
337337 RegType = PTXRegisterType::Pred;
338 }
339 else if (RegVT == MVT::i16) {
340 TRC = PTX::RegI16RegisterClass;
338 } else if (RegVT == MVT::i16) {
339 TRC = &PTX::RegI16RegClass;
341340 RegType = PTXRegisterType::B16;
342 }
343 else if (RegVT == MVT::i32) {
344 TRC = PTX::RegI32RegisterClass;
341 } else if (RegVT == MVT::i32) {
342 TRC = &PTX::RegI32RegClass;
345343 RegType = PTXRegisterType::B32;
346 }
347 else if (RegVT == MVT::i64) {
348 TRC = PTX::RegI64RegisterClass;
344 } else if (RegVT == MVT::i64) {
345 TRC = &PTX::RegI64RegClass;
349346 RegType = PTXRegisterType::B64;
350 }
351 else if (RegVT == MVT::f32) {
352 TRC = PTX::RegF32RegisterClass;
347 } else if (RegVT == MVT::f32) {
348 TRC = &PTX::RegF32RegClass;
353349 RegType = PTXRegisterType::F32;
354 }
355 else if (RegVT == MVT::f64) {
356 TRC = PTX::RegF64RegisterClass;
350 } else if (RegVT == MVT::f64) {
351 TRC = &PTX::RegF64RegClass;
357352 RegType = PTXRegisterType::F64;
358 }
359 else {
353 } else {
360354 llvm_unreachable("Unknown parameter type");
361355 }
362356
5858 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
5959 const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
6060 unsigned RegType;
61 if (TRC == PTX::RegPredRegisterClass)
61 if (TRC == &PTX::RegPredRegClass)
6262 RegType = PTXRegisterType::Pred;
63 else if (TRC == PTX::RegI16RegisterClass)
63 else if (TRC == &PTX::RegI16RegClass)
6464 RegType = PTXRegisterType::B16;
65 else if (TRC == PTX::RegI32RegisterClass)
65 else if (TRC == &PTX::RegI32RegClass)
6666 RegType = PTXRegisterType::B32;
67 else if (TRC == PTX::RegI64RegisterClass)
67 else if (TRC == &PTX::RegI64RegClass)
6868 RegType = PTXRegisterType::B64;
69 else if (TRC == PTX::RegF32RegisterClass)
69 else if (TRC == &PTX::RegF32RegClass)
7070 RegType = PTXRegisterType::F32;
71 else if (TRC == PTX::RegF64RegisterClass)
71 else if (TRC == &PTX::RegF64RegClass)
7272 RegType = PTXRegisterType::F64;
7373 else
7474 llvm_unreachable("Unkown register class.");
340340 MachineFrameInfo *MFI = MF.getFrameInfo();
341341 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
342342 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
343 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
343 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
344344 XCoreFunctionInfo *XFI = MF.getInfo();
345345 if (LRUsed) {
346346 MF.getRegInfo().setPhysRegUnused(XCore::LR);
6565 Subtarget(*XTM.getSubtargetImpl()) {
6666
6767 // Set up the register classes.
68 addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
68 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
6969
7070 // Compute derived properties from the register classes
7171 computeRegisterProperties();
11201120 llvm_unreachable(0);
11211121 }
11221122 case MVT::i32:
1123 unsigned VReg = RegInfo.createVirtualRegister(
1124 XCore::GRRegsRegisterClass);
1123 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
11251124 RegInfo.addLiveIn(VA.getLocReg(), VReg);
11261125 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
11271126 }
11711170 offset -= StackSlotSize;
11721171 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
11731172 // Move argument from phys reg -> virt reg
1174 unsigned VReg = RegInfo.createVirtualRegister(
1175 XCore::GRRegsRegisterClass);
1173 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
11761174 RegInfo.addLiveIn(ArgRegs[i], VReg);
11771175 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
11781176 // Move argument from virt reg -> stack
16101608 switch (Constraint[0]) {
16111609 default : break;
16121610 case 'r':
1613 return std::make_pair(0U, XCore::GRRegsRegisterClass);
1611 return std::make_pair(0U, &XCore::GRRegsRegClass);
16141612 }
16151613 }
16161614 // Use the default implementation in TargetLowering to convert the register
204204 unsigned Reg = MI.getOperand(0).getReg();
205205 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
206206
207 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
208 "Unexpected register operand");
207 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
209208
210209 MachineBasicBlock &MBB = *MI.getParent();
211210
216215 if (!RS)
217216 report_fatal_error("eliminateFrameIndex Frame size too big: " +
218217 Twine(Offset));
219 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
218 unsigned ScratchReg = RS->scavengeRegister(&XCore::GRRegsRegClass, II,
220219 SPAdj);
221220 loadConstant(MBB, II, ScratchReg, Offset, dl);
222221 switch (MI.getOpcode()) {