llvm.org GIT mirror llvm / 41fae9f
AMDGPU/GlobalISel: RegBankSelect for basic int ops git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327843 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
5 changed file(s) with 205 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
5454 };
5555
5656 setAction({G_ADD, S32}, Legal);
57 setAction({G_SUB, S32}, Legal);
5758 setAction({G_MUL, S32}, Legal);
5859 setAction({G_AND, S32}, Legal);
5960 setAction({G_OR, S32}, Legal);
301301 switch (MI.getOpcode()) {
302302 default:
303303 return getInvalidInstructionMapping();
304 case AMDGPU::G_ADD:
305 case AMDGPU::G_SUB:
306 case AMDGPU::G_MUL:
304307 case AMDGPU::G_AND:
305308 case AMDGPU::G_OR:
306309 case AMDGPU::G_XOR:
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2
3 ---
4 name: add_s32_ss
5 legalized: true
6
7 body: |
8 bb.0:
9 liveins: $sgpr0, $sgpr1
10 ; CHECK-LABEL: name: add_s32_ss
11 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
12 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
13 ; CHECK: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY]], [[COPY1]]
14 %0:_(s32) = COPY $sgpr0
15 %1:_(s32) = COPY $sgpr1
16 %2:_(s32) = G_ADD %0, %1
17 ...
18
19 ---
20 name: add_s32_sv
21 legalized: true
22
23 body: |
24 bb.0:
25 liveins: $sgpr0, $vgpr0
26 ; CHECK-LABEL: name: add_s32_sv
27 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
28 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
29 ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY1]]
30 %0:_(s32) = COPY $sgpr0
31 %1:_(s32) = COPY $vgpr0
32 %2:_(s32) = G_ADD %0, %1
33 ...
34
35 ---
36 name: add_s32_vs
37 legalized: true
38
39 body: |
40 bb.0:
41 liveins: $sgpr0, $vgpr0
42 ; CHECK-LABEL: name: add_s32_vs
43 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
44 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
45 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
46 ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY2]]
47 %0:_(s32) = COPY $vgpr0
48 %1:_(s32) = COPY $sgpr0
49 %2:_(s32) = G_ADD %0, %1
50 ...
51
52 ---
53 name: add_s32_vv
54 legalized: true
55
56 body: |
57 bb.0:
58 liveins: $vgpr0, $vgpr1
59 ; CHECK-LABEL: name: add_s32_vv
60 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
61 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
62 ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY1]]
63 %0:_(s32) = COPY $vgpr0
64 %1:_(s32) = COPY $vgpr1
65 %2:_(s32) = G_ADD %0, %1
66 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2
3 ---
4 name: mul_s32_ss
5 legalized: true
6
7 body: |
8 bb.0:
9 liveins: $sgpr0, $sgpr1
10 ; CHECK-LABEL: name: mul_s32_ss
11 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
12 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
13 ; CHECK: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]
14 %0:_(s32) = COPY $sgpr0
15 %1:_(s32) = COPY $sgpr1
16 %2:_(s32) = G_MUL %0, %1
17 ...
18
19 ---
20 name: mul_s32_sv
21 legalized: true
22
23 body: |
24 bb.0:
25 liveins: $sgpr0, $vgpr0
26 ; CHECK-LABEL: name: mul_s32_sv
27 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
28 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
29 ; CHECK: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[COPY]], [[COPY1]]
30 %0:_(s32) = COPY $sgpr0
31 %1:_(s32) = COPY $vgpr0
32 %2:_(s32) = G_MUL %0, %1
33 ...
34
35 ---
36 name: mul_s32_vs
37 legalized: true
38
39 body: |
40 bb.0:
41 liveins: $sgpr0, $vgpr0
42 ; CHECK-LABEL: name: mul_s32_vs
43 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
44 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
45 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
46 ; CHECK: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[COPY]], [[COPY2]]
47 %0:_(s32) = COPY $vgpr0
48 %1:_(s32) = COPY $sgpr0
49 %2:_(s32) = G_MUL %0, %1
50 ...
51
52 ---
53 name: mul_s32_vv
54 legalized: true
55
56 body: |
57 bb.0:
58 liveins: $vgpr0, $vgpr1
59 ; CHECK-LABEL: name: mul_s32_vv
60 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
61 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
62 ; CHECK: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[COPY]], [[COPY1]]
63 %0:_(s32) = COPY $vgpr0
64 %1:_(s32) = COPY $vgpr1
65 %2:_(s32) = G_MUL %0, %1
66 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2
3 ---
4 name: sub_s32_ss
5 legalized: true
6
7 body: |
8 bb.0:
9 liveins: $sgpr0, $sgpr1
10 ; CHECK-LABEL: name: sub_s32_ss
11 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
12 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
13 ; CHECK: [[SUB:%[0-9]+]]:sgpr(s32) = G_SUB [[COPY]], [[COPY1]]
14 %0:_(s32) = COPY $sgpr0
15 %1:_(s32) = COPY $sgpr1
16 %2:_(s32) = G_SUB %0, %1
17 ...
18
19 ---
20 name: sub_s32_sv
21 legalized: true
22
23 body: |
24 bb.0:
25 liveins: $sgpr0, $vgpr0
26 ; CHECK-LABEL: name: sub_s32_sv
27 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
28 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
29 ; CHECK: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[COPY]], [[COPY1]]
30 %0:_(s32) = COPY $sgpr0
31 %1:_(s32) = COPY $vgpr0
32 %2:_(s32) = G_SUB %0, %1
33 ...
34
35 ---
36 name: sub_s32_vs
37 legalized: true
38
39 body: |
40 bb.0:
41 liveins: $sgpr0, $vgpr0
42 ; CHECK-LABEL: name: sub_s32_vs
43 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
44 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
45 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
46 ; CHECK: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[COPY]], [[COPY2]]
47 %0:_(s32) = COPY $vgpr0
48 %1:_(s32) = COPY $sgpr0
49 %2:_(s32) = G_SUB %0, %1
50 ...
51
52 ---
53 name: sub_s32_vv
54 legalized: true
55
56 body: |
57 bb.0:
58 liveins: $vgpr0, $vgpr1
59 ; CHECK-LABEL: name: sub_s32_vv
60 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
61 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
62 ; CHECK: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[COPY]], [[COPY1]]
63 %0:_(s32) = COPY $vgpr0
64 %1:_(s32) = COPY $vgpr1
65 %2:_(s32) = G_SUB %0, %1
66 ...