llvm.org GIT mirror llvm / 41f9733
Virtualize TargetInstrInfo::getRegClass() AMDGPU target needs to override getRegClass() used during instruction selection. We now may have either 32 or 64 bit conditional registers used in the same instructions. For that purpose special SReg_1 register class is created which is dynamically resolved to either SReg_64 or SGPR_32 depending on the subtarget attributes. Differential Revision: https://reviews.llvm.org/D63205 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363931 91177308-0d34-0410-b5e6-96231b3b80d8 Stanislav Mekhanoshin 25 days ago
1 changed file(s) with 1 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
8080
8181 /// Given a machine instruction descriptor, returns the register
8282 /// class constraint for OpNum, or NULL.
83 virtual
8384 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
8485 const TargetRegisterInfo *TRI,
8586 const MachineFunction &MF) const;