llvm.org GIT mirror llvm / 418eb3d
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
16 changed file(s) with 270 addition(s) and 275 deletion(s). Raw diff Collapse all Expand all
136136 }
137137 }
138138
139 static void PrintRegName(raw_ostream &O, StringRef RegName) {
140 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
141 O << (char)toupper(RegName[i]);
142 }
143
144139 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
145140 raw_ostream &O) {
146141 const MCOperand &Op = MI->getOperand(OpNo);
147142 if (Op.isReg()) {
148 PrintRegName(O, getRegisterName(Op.getReg()));
143 printRegName(O, Op.getReg());
149144 } else if (Op.isImm()) {
150145 O << Op.getImm();
151146 } else {
4040 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4141
4242 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
43 O << "OPAQUE PTR ";
43 O << "opaque ptr ";
4444 printMemReference(MI, OpNo, O);
4545 }
4646
4747 void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
48 O << "BYTE PTR ";
48 O << "byte ptr ";
4949 printMemReference(MI, OpNo, O);
5050 }
5151 void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
52 O << "WORD PTR ";
52 O << "word ptr ";
5353 printMemReference(MI, OpNo, O);
5454 }
5555 void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
56 O << "DWORD PTR ";
56 O << "dword ptr ";
5757 printMemReference(MI, OpNo, O);
5858 }
5959 void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
60 O << "QWORD PTR ";
60 O << "qword ptr ";
6161 printMemReference(MI, OpNo, O);
6262 }
6363 void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
64 O << "XMMWORD PTR ";
64 O << "xmmword ptr ";
6565 printMemReference(MI, OpNo, O);
6666 }
6767 void printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
68 O << "YMMWORD PTR ";
68 O << "ymmword ptr ";
6969 printMemReference(MI, OpNo, O);
7070 }
7171 void printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
72 O << "ZMMWORD PTR ";
72 O << "zmmword ptr ";
7373 printMemReference(MI, OpNo, O);
7474 }
7575 void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
76 O << "DWORD PTR ";
76 O << "dword ptr ";
7777 printMemReference(MI, OpNo, O);
7878 }
7979 void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
80 O << "QWORD PTR ";
80 O << "qword ptr ";
8181 printMemReference(MI, OpNo, O);
8282 }
8383 void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
84 O << "XWORD PTR ";
84 O << "xword ptr ";
8585 printMemReference(MI, OpNo, O);
8686 }
8787 void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
88 O << "XMMWORD PTR ";
88 O << "xmmword ptr ";
8989 printMemReference(MI, OpNo, O);
9090 }
9191 void printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
92 O << "YMMWORD PTR ";
92 O << "ymmword ptr ";
9393 printMemReference(MI, OpNo, O);
9494 }
9595 void printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 O << "ZMMWORD PTR ";
96 O << "zmmword ptr ";
9797 printMemReference(MI, OpNo, O);
9898 }
9999 };
10401040 } // Defs = [EFLAGS]
10411041
10421042 def NAME#8i8 : BinOpAI
1043 "{$src, %al|AL, $src}">;
1043 "{$src, %al|al, $src}">;
10441044 def NAME#16i16 : BinOpAI
1045 "{$src, %ax|AX, $src}">;
1045 "{$src, %ax|ax, $src}">;
10461046 def NAME#32i32 : BinOpAI
1047 "{$src, %eax|EAX, $src}">;
1047 "{$src, %eax|eax, $src}">;
10481048 def NAME#64i32 : BinOpAI
1049 "{$src, %rax|RAX, $src}">;
1049 "{$src, %rax|rax, $src}">;
10501050 }
10511051
10521052 /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is
11111111 } // Uses = [EFLAGS], Defs = [EFLAGS]
11121112
11131113 def NAME#8i8 : BinOpAI_FF
1114 "{$src, %al|AL, $src}">;
1114 "{$src, %al|al, $src}">;
11151115 def NAME#16i16 : BinOpAI_FF
1116 "{$src, %ax|AX, $src}">;
1116 "{$src, %ax|ax, $src}">;
11171117 def NAME#32i32 : BinOpAI_FF
1118 "{$src, %eax|EAX, $src}">;
1118 "{$src, %eax|eax, $src}">;
11191119 def NAME#64i32 : BinOpAI_FF
1120 "{$src, %rax|RAX, $src}">;
1120 "{$src, %rax|rax, $src}">;
11211121 }
11221122
11231123 /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
11781178 } // Defs = [EFLAGS]
11791179
11801180 def NAME#8i8 : BinOpAI
1181 "{$src, %al|AL, $src}">;
1181 "{$src, %al|al, $src}">;
11821182 def NAME#16i16 : BinOpAI
1183 "{$src, %ax|AX, $src}">;
1183 "{$src, %ax|ax, $src}">;
11841184 def NAME#32i32 : BinOpAI
1185 "{$src, %eax|EAX, $src}">;
1185 "{$src, %eax|eax, $src}">;
11861186 def NAME#64i32 : BinOpAI
1187 "{$src, %rax|RAX, $src}">;
1187 "{$src, %rax|rax, $src}">;
11881188 }
11891189
11901190
12521252 } // Defs = [EFLAGS]
12531253
12541254 def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
1255 "{$src, %al|AL, $src}">;
1255 "{$src, %al|al, $src}">;
12561256 def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
1257 "{$src, %ax|AX, $src}">;
1257 "{$src, %ax|ax, $src}">;
12581258 def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
1259 "{$src, %eax|EAX, $src}">;
1259 "{$src, %eax|eax, $src}">;
12601260 def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
1261 "{$src, %rax|RAX, $src}">;
1261 "{$src, %rax|rax, $src}">;
12621262 } // isCompare
12631263
12641264 //===----------------------------------------------------------------------===//
228228 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
229229 // we have to put some 'r's in and take them out of weird places.
230230 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
231 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, ST(0)}">;
231 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, st(0)}">;
232232 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
233233 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
234 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, ST(0)}">;
234 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
235235 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
236236 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
237 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, ST(0)}">;
237 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
238238 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
239239 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
240 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, ST(0)}">;
240 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, st(0)}">;
241241 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
242242 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
243 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, ST(0)}">;
243 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
244244 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
245245 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
246 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, ST(0)}">;
246 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
247247 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
248248
249249 def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
336336 let Predicates = [HasCMov] in {
337337 // These are not factored because there's no clean way to pass DA/DB.
338338 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
339 "fcmovb\t{$op, %st(0)|ST(0), $op}">, DA;
339 "fcmovb\t{$op, %st(0)|st(0), $op}">, DA;
340340 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
341 "fcmovbe\t{$op, %st(0)|ST(0), $op}">, DA;
341 "fcmovbe\t{$op, %st(0)|st(0), $op}">, DA;
342342 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
343 "fcmove\t{$op, %st(0)|ST(0), $op}">, DA;
343 "fcmove\t{$op, %st(0)|st(0), $op}">, DA;
344344 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
345 "fcmovu\t{$op, %st(0)|ST(0), $op}">, DA;
345 "fcmovu\t{$op, %st(0)|st(0), $op}">, DA;
346346 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
347 "fcmovnb\t{$op, %st(0)|ST(0), $op}">, DB;
347 "fcmovnb\t{$op, %st(0)|st(0), $op}">, DB;
348348 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
349 "fcmovnbe\t{$op, %st(0)|ST(0), $op}">, DB;
349 "fcmovnbe\t{$op, %st(0)|st(0), $op}">, DB;
350350 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
351 "fcmovne\t{$op, %st(0)|ST(0), $op}">, DB;
351 "fcmovne\t{$op, %st(0)|st(0), $op}">, DB;
352352 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
353 "fcmovnu\t{$op, %st(0)|ST(0), $op}">, DB;
353 "fcmovnu\t{$op, %st(0)|st(0), $op}">, DB;
354354 } // Predicates = [HasCMov]
355355
356356 // Floating point loads & stores.
577577 let SchedRW = [WriteALU] in {
578578 let Defs = [AX], Uses = [FPSW] in
579579 def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags
580 (outs), (ins), "fnstsw\t{%ax|AX}",
580 (outs), (ins), "fnstsw\t{%ax|ax}",
581581 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>, DF;
582582
583583 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
10751075 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
10761076 let SchedRW = [WriteALU] in {
10771077 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1078 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
1078 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
10791079 Requires<[In32BitMode]>;
10801080 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1081 "mov{w}\t{$src, %ax|AX, $src}", [], IIC_MOV_MEM>, OpSize,
1081 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
10821082 Requires<[In32BitMode]>;
10831083 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1084 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1084 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
10851085 Requires<[In32BitMode]>;
10861086 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1087 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1087 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
10881088 Requires<[In32BitMode]>;
10891089 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1090 "mov{w}\t{%ax, $dst|$dst, AX}", [], IIC_MOV_MEM>, OpSize,
1090 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
10911091 Requires<[In32BitMode]>;
10921092 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1093 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1093 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
10941094 Requires<[In32BitMode]>;
10951095 }
10961096
10971097 // These forms all have full 64-bit absolute addresses in their instructions
10981098 // and use the movabs mnemonic to indicate this specific form.
10991099 def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset64:$src),
1100 "movabs{b}\t{$src, %al|AL, $src}", []>,
1100 "movabs{b}\t{$src, %al|al, $src}", []>,
11011101 Requires<[In64BitMode]>;
11021102 def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
1103 "movabs{w}\t{$src, %ax|AX, $src}", []>, OpSize,
1103 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
11041104 Requires<[In64BitMode]>;
11051105 def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
1106 "movabs{l}\t{$src, %eax|AEX, $src}", []>,
1106 "movabs{l}\t{$src, %eax|eax, $src}", []>,
11071107 Requires<[In64BitMode]>;
11081108 def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
1109 "movabs{q}\t{$src, %rax|RAX, $src}", []>,
1109 "movabs{q}\t{$src, %rax|rax, $src}", []>,
11101110 Requires<[In64BitMode]>;
11111111
11121112 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset64:$dst), (ins),
1113 "movabs{b}\t{%al, $dst|$dst, AL}", []>,
1113 "movabs{b}\t{%al, $dst|$dst, al}", []>,
11141114 Requires<[In64BitMode]>;
11151115 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
1116 "movabs{w}\t{%ax, $dst|$dst, AX}", []>, OpSize,
1116 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
11171117 Requires<[In64BitMode]>;
11181118 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
1119 "movabs{l}\t{%eax, $dst|$dst, EAX}", []>,
1119 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
11201120 Requires<[In64BitMode]>;
11211121 def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
1122 "movabs{q}\t{%rax, $dst|$dst, RAX}", []>,
1122 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
11231123 Requires<[In64BitMode]>;
11241124
11251125 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
14531453
14541454 // Swap between EAX and other registers.
14551455 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1456 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1456 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
14571457 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1458 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1458 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
14591459 Requires<[In32BitMode]>;
14601460 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
14611461 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
14621462 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1463 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1463 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
14641464 Requires<[In64BitMode]>;
14651465 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1466 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1466 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
14671467 } // SchedRW
14681468
14691469 let SchedRW = [WriteALU] in {
20322032 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
20332033
20342034 // div and idiv aliases for explicit A register.
2035 def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8r GR8 :$src)>;
2036 def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16r GR16:$src)>;
2037 def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32r GR32:$src)>;
2038 def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64r GR64:$src)>;
2039 def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8m i8mem :$src)>;
2040 def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16m i16mem:$src)>;
2041 def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32m i32mem:$src)>;
2042 def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64m i64mem:$src)>;
2043 def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8r GR8 :$src)>;
2044 def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16r GR16:$src)>;
2045 def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32r GR32:$src)>;
2046 def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64r GR64:$src)>;
2047 def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8m i8mem :$src)>;
2048 def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16m i16mem:$src)>;
2049 def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32m i32mem:$src)>;
2050 def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64m i64mem:$src)>;
2035 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2036 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2037 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2038 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2039 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2040 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2041 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2042 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2043 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2044 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2045 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2046 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2047 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2048 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2049 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2050 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
20512051
20522052
20532053
20742074 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
20752075 // gas.
20762076 multiclass FpUnaryAlias {
2077 def : InstAliasST(0), $op}"),
2077 def : InstAliasst(0), $op}"),
20782078 (Inst RST:$op), EmitAlias>;
2079 def : InstAliasST(0), ST(0)}"),
2079 def : InstAliasst(0), st(0)}"),
20802080 (Inst ST0), EmitAlias>;
20812081 }
20822082
21012101 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
21022102 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
21032103 // solely because gas supports it.
2104 def : InstAlias<"faddp\t{%st(0), $op|$op, ST(0)}", (ADD_FPrST0 RST:$op), 0>;
2105 def : InstAlias<"fmulp\t{%st(0), $op|$op, ST(0)}", (MUL_FPrST0 RST:$op)>;
2106 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, ST(0)}", (SUBR_FPrST0 RST:$op)>;
2107 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, ST(0)}", (SUB_FPrST0 RST:$op)>;
2108 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, ST(0)}", (DIVR_FPrST0 RST:$op)>;
2109 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, ST(0)}", (DIV_FPrST0 RST:$op)>;
2104 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2105 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2106 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2107 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2108 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2109 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
21102110
21112111 // We accept "fnstsw %eax" even though it only writes %ax.
2112 def : InstAlias<"fnstsw\t{%eax|EAX}", (FNSTSW16r)>;
2113 def : InstAlias<"fnstsw\t{%al|AL}" , (FNSTSW16r)>;
2112 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2113 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
21142114 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
21152115
21162116 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
21292129 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
21302130
21312131 // inb %dx -> inb %al, %dx
2132 def : InstAlias<"inb\t{%dx|DX}", (IN8rr), 0>;
2133 def : InstAlias<"inw\t{%dx|DX}", (IN16rr), 0>;
2134 def : InstAlias<"inl\t{%dx|DX}", (IN32rr), 0>;
2132 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2133 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2134 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
21352135 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
21362136 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
21372137 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
21832183 // Note: No GR32->GR64 movzx form.
21842184
21852185 // outb %dx -> outb %al, %dx
2186 def : InstAlias<"outb\t{%dx|DX}", (OUT8rr), 0>;
2187 def : InstAlias<"outw\t{%dx|DX}", (OUT16rr), 0>;
2188 def : InstAlias<"outl\t{%dx|DX}", (OUT32rr), 0>;
2186 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2187 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2188 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
21892189 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
21902190 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
21912191 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
22512251 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
22522252
22532253 // xchg: We accept "xchgX , %eax" and "xchgX %eax, " as synonyms.
2254 def : InstAlias<"xchg{w}\t{%ax, $src|$src, AX}", (XCHG16ar GR16:$src)>;
2255 def : InstAlias<"xchg{l}\t{%eax, $src|$src, EAX}", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2256 def : InstAlias<"xchg{l}\t{%eax, $src|$src, EAX}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2257 def : InstAlias<"xchg{q}\t{%rax, $src|$src, RAX}", (XCHG64ar GR64:$src)>;
2254 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2255 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2256 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2257 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;
54765476 TB, Requires<[HasSSE3]>;
54775477 } // SchedRW
54785478
5479 def : InstAlias<"mwait\t{%eax, %ecx|ECX, EAX}", (MWAITrr)>, Requires<[In32BitMode]>;
5480 def : InstAlias<"mwait\t{%rax, %rcx|RCX, RAX}", (MWAITrr)>, Requires<[In64BitMode]>;
5481
5482 def : InstAlias<"monitor\t{%eax, %ecx, %edx|EDX, ECX, EAX}", (MONITORrrr)>,
5479 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5480 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5481
5482 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
54835483 Requires<[In32BitMode]>;
5484 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|RDX, RCX, RAX}", (MONITORrrr)>,
5484 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
54855485 Requires<[In64BitMode]>;
54865486
54875487 //===----------------------------------------------------------------------===//
70157015 int_x86_sse41_pblendvb>;
70167016
70177017 // Aliases with the implicit xmm0 argument
7018 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
7018 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
70197019 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7020 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
7020 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
70217021 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7022 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
7022 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
70237023 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7024 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
7024 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
70257025 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7026 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
7026 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
70277027 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7028 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, XMM0}",
7028 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
70297029 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
70307030
70317031 let Predicates = [UseSSE41] in {
2525
2626 // 0F 01 DE
2727 let Uses = [EAX] in
28 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|EAX}", []>, TB;
28 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
2929
3030 // 0F 01 D8
3131 let Uses = [EAX] in
3232 def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
33 "vmrun\t{%eax|EAX}", []>, TB, Requires<[In32BitMode]>;
33 "vmrun\t{%eax|eax}", []>, TB, Requires<[In32BitMode]>;
3434 let Uses = [RAX] in
3535 def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
36 "vmrun\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
36 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
3737
3838 // 0F 01 DA
3939 let Uses = [EAX] in
4040 def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
41 "vmload\t{%eax|EAX}", []>, TB, Requires<[In32BitMode]>;
41 "vmload\t{%eax|eax}", []>, TB, Requires<[In32BitMode]>;
4242 let Uses = [RAX] in
4343 def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
44 "vmload\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
44 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
4545
4646 // 0F 01 DB
4747 let Uses = [EAX] in
4848 def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
49 "vmsave\t{%eax|EAX}", []>, TB, Requires<[In32BitMode]>;
49 "vmsave\t{%eax|eax}", []>, TB, Requires<[In32BitMode]>;
5050 let Uses = [RAX] in
5151 def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins),
52 "vmsave\t{%rax|RAX}", []>, TB, Requires<[In64BitMode]>;
52 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
5353
5454 // 0F 01 DF
5555 let Uses = [EAX, ECX] in
5656 def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins),
57 "invlpga\t{%ecx, %eax|EAX, ECX}", []>, TB, Requires<[In32BitMode]>;
57 "invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[In32BitMode]>;
5858 let Uses = [RAX, ECX] in
5959 def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins),
60 "invlpga\t{%ecx, %rax|RAX, ECX}", []>, TB, Requires<[In64BitMode]>;
60 "invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
6161
1717 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
1818 let Uses = [CL] in {
1919 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
20 "shl{b}\t{%cl, $dst|$dst, CL}",
20 "shl{b}\t{%cl, $dst|$dst, cl}",
2121 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
2222 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
23 "shl{w}\t{%cl, $dst|$dst, CL}",
23 "shl{w}\t{%cl, $dst|$dst, cl}",
2424 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
2525 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
26 "shl{l}\t{%cl, $dst|$dst, CL}",
26 "shl{l}\t{%cl, $dst|$dst, cl}",
2727 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
2828 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
29 "shl{q}\t{%cl, $dst|$dst, CL}",
29 "shl{q}\t{%cl, $dst|$dst, cl}",
3030 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
3131 } // Uses = [CL]
3232
6969 // using CL?
7070 let Uses = [CL] in {
7171 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
72 "shl{b}\t{%cl, $dst|$dst, CL}",
72 "shl{b}\t{%cl, $dst|$dst, cl}",
7373 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
7474 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
75 "shl{w}\t{%cl, $dst|$dst, CL}",
75 "shl{w}\t{%cl, $dst|$dst, cl}",
7676 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
7777 OpSize;
7878 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
79 "shl{l}\t{%cl, $dst|$dst, CL}",
79 "shl{l}\t{%cl, $dst|$dst, cl}",
8080 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
8181 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
82 "shl{q}\t{%cl, $dst|$dst, CL}",
82 "shl{q}\t{%cl, $dst|$dst, cl}",
8383 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
8484 }
8585 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
123123 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
124124 let Uses = [CL] in {
125125 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
126 "shr{b}\t{%cl, $dst|$dst, CL}",
126 "shr{b}\t{%cl, $dst|$dst, cl}",
127127 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
128128 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
129 "shr{w}\t{%cl, $dst|$dst, CL}",
129 "shr{w}\t{%cl, $dst|$dst, cl}",
130130 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
131131 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
132 "shr{l}\t{%cl, $dst|$dst, CL}",
132 "shr{l}\t{%cl, $dst|$dst, cl}",
133133 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
134134 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
135 "shr{q}\t{%cl, $dst|$dst, CL}",
135 "shr{q}\t{%cl, $dst|$dst, cl}",
136136 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
137137 }
138138
170170 let SchedRW = [WriteShiftLd, WriteRMW] in {
171171 let Uses = [CL] in {
172172 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
173 "shr{b}\t{%cl, $dst|$dst, CL}",
173 "shr{b}\t{%cl, $dst|$dst, cl}",
174174 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
175175 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
176 "shr{w}\t{%cl, $dst|$dst, CL}",
176 "shr{w}\t{%cl, $dst|$dst, cl}",
177177 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
178178 OpSize;
179179 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
180 "shr{l}\t{%cl, $dst|$dst, CL}",
180 "shr{l}\t{%cl, $dst|$dst, cl}",
181181 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
182182 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
183 "shr{q}\t{%cl, $dst|$dst, CL}",
183 "shr{q}\t{%cl, $dst|$dst, cl}",
184184 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
185185 }
186186 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
223223 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
224224 let Uses = [CL] in {
225225 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
226 "sar{b}\t{%cl, $dst|$dst, CL}",
226 "sar{b}\t{%cl, $dst|$dst, cl}",
227227 [(set GR8:$dst, (sra GR8:$src1, CL))],
228228 IIC_SR>;
229229 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
230 "sar{w}\t{%cl, $dst|$dst, CL}",
230 "sar{w}\t{%cl, $dst|$dst, cl}",
231231 [(set GR16:$dst, (sra GR16:$src1, CL))],
232232 IIC_SR>, OpSize;
233233 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
234 "sar{l}\t{%cl, $dst|$dst, CL}",
234 "sar{l}\t{%cl, $dst|$dst, cl}",
235235 [(set GR32:$dst, (sra GR32:$src1, CL))],
236236 IIC_SR>;
237237 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
238 "sar{q}\t{%cl, $dst|$dst, CL}",
238 "sar{q}\t{%cl, $dst|$dst, cl}",
239239 [(set GR64:$dst, (sra GR64:$src1, CL))],
240240 IIC_SR>;
241241 }
282282 let SchedRW = [WriteShiftLd, WriteRMW] in {
283283 let Uses = [CL] in {
284284 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
285 "sar{b}\t{%cl, $dst|$dst, CL}",
285 "sar{b}\t{%cl, $dst|$dst, cl}",
286286 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
287287 IIC_SR>;
288288 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
289 "sar{w}\t{%cl, $dst|$dst, CL}",
289 "sar{w}\t{%cl, $dst|$dst, cl}",
290290 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
291291 IIC_SR>, OpSize;
292292 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
293 "sar{l}\t{%cl, $dst|$dst, CL}",
293 "sar{l}\t{%cl, $dst|$dst, cl}",
294294 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
295295 IIC_SR>;
296296 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
297 "sar{q}\t{%cl, $dst|$dst, CL}",
297 "sar{q}\t{%cl, $dst|$dst, cl}",
298298 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
299299 IIC_SR>;
300300 }
348348 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
349349 let Uses = [CL] in
350350 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
351 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
351 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
352352
353353 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
354354 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
356356 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
357357 let Uses = [CL] in
358358 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
359 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
359 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
360360
361361 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
362362 "rcl{l}\t$dst", [], IIC_SR>;
364364 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
365365 let Uses = [CL] in
366366 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
367 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
367 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
368368
369369
370370 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
373373 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
374374 let Uses = [CL] in
375375 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
376 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
376 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
377377
378378
379379 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
382382 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
383383 let Uses = [CL] in
384384 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
385 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
385 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
386386
387387 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
388388 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
390390 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
391391 let Uses = [CL] in
392392 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
393 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
393 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
394394
395395 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
396396 "rcr{l}\t$dst", [], IIC_SR>;
398398 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
399399 let Uses = [CL] in
400400 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
401 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
401 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
402402
403403 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
404404 "rcr{q}\t$dst", [], IIC_SR>;
406406 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
407407 let Uses = [CL] in
408408 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
409 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
409 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
410410
411411 } // Constraints = "$src = $dst"
412412
447447
448448 let Uses = [CL] in {
449449 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
450 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
450 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
451451 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
452 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
452 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
453453 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
454 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
454 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
455455 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
456 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
456 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
457457
458458 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
459 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
459 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
460460 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
461 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
461 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
462462 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
463 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
463 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
464464 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
465 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
465 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
466466 }
467467 } // SchedRW
468468 } // hasSideEffects = 0
471471 // FIXME: provide shorter instructions when imm8 == 1
472472 let Uses = [CL] in {
473473 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
474 "rol{b}\t{%cl, $dst|$dst, CL}",
474 "rol{b}\t{%cl, $dst|$dst, cl}",
475475 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
476476 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
477 "rol{w}\t{%cl, $dst|$dst, CL}",
477 "rol{w}\t{%cl, $dst|$dst, cl}",
478478 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
479479 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
480 "rol{l}\t{%cl, $dst|$dst, CL}",
480 "rol{l}\t{%cl, $dst|$dst, cl}",
481481 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
482482 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
483 "rol{q}\t{%cl, $dst|$dst, CL}",
483 "rol{q}\t{%cl, $dst|$dst, cl}",
484484 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
485485 }
486486
524524 let SchedRW = [WriteShiftLd, WriteRMW] in {
525525 let Uses = [CL] in {
526526 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
527 "rol{b}\t{%cl, $dst|$dst, CL}",
527 "rol{b}\t{%cl, $dst|$dst, cl}",
528528 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
529529 IIC_SR>;
530530 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
531 "rol{w}\t{%cl, $dst|$dst, CL}",
531 "rol{w}\t{%cl, $dst|$dst, cl}",
532532 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
533533 IIC_SR>, OpSize;
534534 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
535 "rol{l}\t{%cl, $dst|$dst, CL}",
535 "rol{l}\t{%cl, $dst|$dst, cl}",
536536 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
537537 IIC_SR>;
538538 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
539 "rol{q}\t{%cl, $dst|$dst, CL}",
539 "rol{q}\t{%cl, $dst|$dst, cl}",
540540 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
541541 IIC_SR>;
542542 }
581581 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
582582 let Uses = [CL] in {
583583 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
584 "ror{b}\t{%cl, $dst|$dst, CL}",
584 "ror{b}\t{%cl, $dst|$dst, cl}",
585585 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
586586 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
587 "ror{w}\t{%cl, $dst|$dst, CL}",
587 "ror{w}\t{%cl, $dst|$dst, cl}",
588588 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
589589 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
590 "ror{l}\t{%cl, $dst|$dst, CL}",
590 "ror{l}\t{%cl, $dst|$dst, cl}",
591591 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
592592 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
593 "ror{q}\t{%cl, $dst|$dst, CL}",
593 "ror{q}\t{%cl, $dst|$dst, cl}",
594594 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
595595 }
596596
634634 let SchedRW = [WriteShiftLd, WriteRMW] in {
635635 let Uses = [CL] in {
636636 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
637 "ror{b}\t{%cl, $dst|$dst, CL}",
637 "ror{b}\t{%cl, $dst|$dst, cl}",
638638 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
639639 IIC_SR>;
640640 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
641 "ror{w}\t{%cl, $dst|$dst, CL}",
641 "ror{w}\t{%cl, $dst|$dst, cl}",
642642 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
643643 IIC_SR>, OpSize;
644644 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
645 "ror{l}\t{%cl, $dst|$dst, CL}",
645 "ror{l}\t{%cl, $dst|$dst, cl}",
646646 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
647647 IIC_SR>;
648648 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
649 "ror{q}\t{%cl, $dst|$dst, CL}",
649 "ror{q}\t{%cl, $dst|$dst, cl}",
650650 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
651651 IIC_SR>;
652652 }
698698 let Uses = [CL] in {
699699 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
700700 (ins GR16:$src1, GR16:$src2),
701 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
701 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
702702 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
703703 IIC_SHD16_REG_CL>,
704704 TB, OpSize;
705705 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
706706 (ins GR16:$src1, GR16:$src2),
707 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
707 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
708708 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
709709 IIC_SHD16_REG_CL>,
710710 TB, OpSize;
711711 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
712712 (ins GR32:$src1, GR32:$src2),
713 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
713 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
714714 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
715715 IIC_SHD32_REG_CL>, TB;
716716 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
717717 (ins GR32:$src1, GR32:$src2),
718 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
718 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
719719 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
720720 IIC_SHD32_REG_CL>, TB;
721721 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
722722 (ins GR64:$src1, GR64:$src2),
723 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
723 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
724724 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
725725 IIC_SHD64_REG_CL>,
726726 TB;
727727 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
728728 (ins GR64:$src1, GR64:$src2),
729 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
729 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
730730 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
731731 IIC_SHD64_REG_CL>,
732732 TB;
781781 let SchedRW = [WriteShiftLd, WriteRMW] in {
782782 let Uses = [CL] in {
783783 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
784 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
784 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
785785 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
786786 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
787787 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
788 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
788 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
789789 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
790790 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
791791
792792 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
793 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
793 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
794794 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
795795 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
796796 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
797 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
797 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
798798 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
799799 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
800800
801801 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
802 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
802 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
803803 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
804804 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
805805 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
806 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
806 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
807807 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
808808 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
809809 }
7676 let SchedRW = [WriteSystem] in {
7777 let Defs = [AL], Uses = [DX] in
7878 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
79 "in{b}\t{%dx, %al|AL, DX}", [], IIC_IN_RR>;
79 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
8080 let Defs = [AX], Uses = [DX] in
8181 def IN16rr : I<0xED, RawFrm, (outs), (ins),
82 "in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize;
82 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
8383 let Defs = [EAX], Uses = [DX] in
8484 def IN32rr : I<0xED, RawFrm, (outs), (ins),
85 "in{l}\t{%dx, %eax|EAX, DX}", [], IIC_IN_RR>;
85 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>;
8686
8787 let Defs = [AL] in
8888 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
89 "in{b}\t{$port, %al|AL, $port}", [], IIC_IN_RI>;
89 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
9090 let Defs = [AX] in
9191 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
92 "in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize;
92 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
9393 let Defs = [EAX] in
9494 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
95 "in{l}\t{$port, %eax|EAX, $port}", [], IIC_IN_RI>;
95 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>;
9696
9797 let Uses = [DX, AL] in
9898 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
99 "out{b}\t{%al, %dx|DX, AL}", [], IIC_OUT_RR>;
99 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
100100 let Uses = [DX, AX] in
101101 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
102 "out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize;
102 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
103103 let Uses = [DX, EAX] in
104104 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
105 "out{l}\t{%eax, %dx|DX, EAX}", [], IIC_OUT_RR>;
105 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>;
106106
107107 let Uses = [AL] in
108108 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
109 "out{b}\t{%al, $port|$port, AL}", [], IIC_OUT_IR>;
109 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
110110 let Uses = [AX] in
111111 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
112 "out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize;
112 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
113113 let Uses = [EAX] in
114114 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
115 "out{l}\t{%eax, $port|$port, EAX}", [], IIC_OUT_IR>;
115 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>;
116116
117117 def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
118118 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
247247 "ltr{w}\t$src", [], IIC_LTR>, TB;
248248
249249 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
250 "push{w}\t{%cs|CS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
250 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
251251 OpSize;
252252 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
253 "push{l}\t{%cs|CS}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
253 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
254254 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
255 "push{w}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
255 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
256256 OpSize;
257257 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
258 "push{l}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
258 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
259259 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
260 "push{w}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
260 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
261261 OpSize;
262262 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
263 "push{l}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
263 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
264264 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
265 "push{w}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
265 "push{w}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
266266 OpSize;
267267 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
268 "push{l}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
268 "push{l}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
269269
270270 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
271 "push{w}\t{%fs|FS}", [], IIC_PUSH_SR>, OpSize, TB;
271 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
272272 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
273 "push{l}\t{%fs|FS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
273 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
274274 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
275 "push{w}\t{%gs|GS}", [], IIC_PUSH_SR>, OpSize, TB;
275 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
276276 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
277 "push{l}\t{%gs|GS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
277 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
278278
279279 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
280 "push{q}\t{%fs|FS}", [], IIC_PUSH_SR>, TB;
280 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB;
281281 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
282 "push{q}\t{%gs|GS}", [], IIC_PUSH_SR>, TB;
282 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB;
283283
284284 // No "pop cs" instruction.
285285 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
286 "pop{w}\t{%ss|SS}", [], IIC_POP_SR_SS>,
286 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
287287 OpSize, Requires<[In32BitMode]>;
288288 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
289 "pop{l}\t{%ss|SS}", [], IIC_POP_SR_SS>,
289 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
290290 Requires<[In32BitMode]>;
291291
292292 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
293 "pop{w}\t{%ds|DS}", [], IIC_POP_SR>,
293 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
294294 OpSize, Requires<[In32BitMode]>;
295295 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
296 "pop{l}\t{%ds|DS}", [], IIC_POP_SR>,
296 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
297297 Requires<[In32BitMode]>;
298298
299299 def POPES16 : I<0x07, RawFrm, (outs), (ins),
300 "pop{w}\t{%es|ES}", [], IIC_POP_SR>,
300 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
301301 OpSize, Requires<[In32BitMode]>;
302302 def POPES32 : I<0x07, RawFrm, (outs), (ins),
303 "pop{l}\t{%es|ES}", [], IIC_POP_SR>,
303 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
304304 Requires<[In32BitMode]>;
305305
306306 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
307 "pop{w}\t{%fs|FS}", [], IIC_POP_SR>, OpSize, TB;
307 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
308308 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
309 "pop{l}\t{%fs|FS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
309 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
310310 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
311 "pop{q}\t{%fs|FS}", [], IIC_POP_SR>, TB;
311 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB;
312312
313313 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
314 "pop{w}\t{%gs|GS}", [], IIC_POP_SR>, OpSize, TB;
314 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
315315 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
316 "pop{l}\t{%gs|GS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
316 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
317317 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
318 "pop{q}\t{%gs|GS}", [], IIC_POP_SR>, TB;
318 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB;
319319
320320
321321 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
0 ; RUN: llc < %s -mcpu=generic -march=x86 -x86-asm-syntax=intel | FileCheck %s
1 ; CHECK: add ESP, 8
1 ; CHECK: add esp, 8
22
33 target triple = "i686-pc-linux-gnu"
44
44
55 define i64 @caller() {
66 %X = call x86_fastcallcc i64 @callee( i64 4294967299 ) ; [#uses=1]
7 ; CHECK: mov{{.*}}EDX, 1
7 ; CHECK: mov{{.*}}edx, 1
88 ret i64 %X
99 }
1010
1111 define x86_fastcallcc i64 @caller2(i64 inreg %X) {
1212 ret i64 %X
13 ; CHECK: mov{{.*}}EAX, ECX
13 ; CHECK: mov{{.*}}eax, ecx
1414 }
1515
1616 declare x86_thiscallcc i64 @callee2(i32)
1717
1818 define i64 @caller3() {
1919 %X = call x86_thiscallcc i64 @callee2( i32 3 )
20 ; CHECK: mov{{.*}}ECX, 3
20 ; CHECK: mov{{.*}}ecx, 3
2121 ret i64 %X
2222 }
2323
2424 define x86_thiscallcc i32 @caller4(i32 %X) {
2525 ret i32 %X
26 ; CHECK: mov{{.*}}EAX, ECX
26 ; CHECK: mov{{.*}}eax, ecx
2727 }
2828
66 ret double %tmp.1
77 }
88 ; CHECK-LABEL: foo_add:
9 ; CHECK: fadd DWORD PTR
9 ; CHECK: fadd dword ptr
1010
1111 define double @foo_mul(double %P) {
1212 %tmp.1 = fmul double %P, 1.230000e+02 ; [#uses=1]
1313 ret double %tmp.1
1414 }
1515 ; CHECK-LABEL: foo_mul:
16 ; CHECK: fmul DWORD PTR
16 ; CHECK: fmul dword ptr
1717
1818 define double @foo_sub(double %P) {
1919 %tmp.1 = fsub double %P, 1.230000e+02 ; [#uses=1]
2020 ret double %tmp.1
2121 }
2222 ; CHECK-LABEL: foo_sub:
23 ; CHECK: fadd DWORD PTR
23 ; CHECK: fadd dword ptr
2424
2525 define double @foo_subr(double %P) {
2626 %tmp.1 = fsub double 1.230000e+02, %P ; [#uses=1]
2727 ret double %tmp.1
2828 }
2929 ; CHECK-LABEL: foo_subr:
30 ; CHECK: fsub QWORD PTR
30 ; CHECK: fsub qword ptr
3131
3232 define double @foo_div(double %P) {
3333 %tmp.1 = fdiv double %P, 1.230000e+02 ; [#uses=1]
3434 ret double %tmp.1
3535 }
3636 ; CHECK-LABEL: foo_div:
37 ; CHECK: fdiv DWORD PTR
37 ; CHECK: fdiv dword ptr
3838
3939 define double @foo_divr(double %P) {
4040 %tmp.1 = fdiv double 1.230000e+02, %P ; [#uses=1]
4141 ret double %tmp.1
4242 }
4343 ; CHECK-LABEL: foo_divr:
44 ; CHECK: fdiv QWORD PTR
44 ; CHECK: fdiv qword ptr
4545
66 ; The above computation of %tmp4 should match a single lea, without using
77 ; actual add instructions.
88 ; CHECK-NOT: add
9 ; CHECK: lea {{[A-Z]+}}, DWORD PTR [{{[A-Z]+}} + 4*{{[A-Z]+}} - 5]
9 ; CHECK: lea {{[a-z]+}}, dword ptr [{{[a-z]+}} + 4*{{[a-z]+}} - 5]
1010
1111 ret i32 %tmp4
1212 }
0 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
1 ; RUN: grep "shld.*CL"
1 ; RUN: grep "shld.*cl"
22 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
3 ; RUN: not grep "mov CL, BL"
3 ; RUN: not grep "mov cl, bl"
44
55 ; PR687
66
1616 store i64 %tmp2676.us.us, i64* %tmp2666
1717 ret i32 0
1818
19 ; INTEL: and {{E..}}, DWORD PTR [360]
20 ; INTEL: and DWORD PTR [356], {{E..}}
21 ; FIXME: mov DWORD PTR [360], {{E..}}
22 ; The above line comes out as 'mov 360, EAX', but when the register is ECX it works?
19 ; INTEL: and {{e..}}, dword ptr [360]
20 ; INTEL: and dword ptr [356], {{e..}}
21 ; FIXME: mov dword ptr [360], {{e..}}
22 ; The above line comes out as 'mov 360, eax', but when the register is ecx it works?
2323
2424 ; ATT: andl 360, %{{e..}}
2525 ; ATT: andl %{{e..}}, 356
1111 # CHECK: movsq
1212 0x48 0xa5
1313
14 # CHECK: pop FS
14 # CHECK: pop fs
1515 0x0f 0xa1
1616
17 # CHECK: pop GS
17 # CHECK: pop gs
1818 0x0f 0xa9
1919
20 # CHECK: in AL, DX
20 # CHECK: in al, dx
2121 0xec
2222
2323 # CHECK: nop
2424 0x90
2525
26 # CHECK: xchg EAX, R8D
26 # CHECK: xchg eax, r8d
2727 0x41 0x90
2828
29 # CHECK: xchg RAX, R8
29 # CHECK: xchg rax, r8
3030 0x49 0x90
3131
32 # CHECK: add AL, 0
32 # CHECK: add al, 0
3333 0x04 0x00
3434
35 # CHECK: add AX, 0
35 # CHECK: add ax, 0
3636 0x66 0x05 0x00 0x00
3737
38 # CHECK: add EAX, 0
38 # CHECK: add eax, 0
3939 0x05 0x00 0x00 0x00 0x00
4040
41 # CHECK: add RAX, 0
41 # CHECK: add rax, 0
4242 0x48 0x05 0x00 0x00 0x00 0x00
4343
44 # CHECK: adc AL, 0
44 # CHECK: adc al, 0
4545 0x14 0x00
4646
47 # CHECK: adc AX, 0
47 # CHECK: adc ax, 0
4848 0x66 0x15 0x00 0x00
4949
50 # CHECK: adc EAX, 0
50 # CHECK: adc eax, 0
5151 0x15 0x00 0x00 0x00 0x00
5252
53 # CHECK: adc RAX, 0
53 # CHECK: adc rax, 0
5454 0x48 0x15 0x00 0x00 0x00 0x00
5555
56 # CHECK: cmp AL, 0
56 # CHECK: cmp al, 0
5757 0x3c 0x00
5858
59 # CHECK: cmp AX, 0
59 # CHECK: cmp ax, 0
6060 0x66 0x3d 0x00 0x00
6161
62 # CHECK: cmp EAX, 0
62 # CHECK: cmp eax, 0
6363 0x3d 0x00 0x00 0x00 0x00
6464
65 # CHECK: cmp RAX, 0
65 # CHECK: cmp rax, 0
6666 0x48 0x3d 0x00 0x00 0x00 0x00
6767
68 # CHECK: test AL, 0
68 # CHECK: test al, 0
6969 0xa8 0x00
7070
71 # CHECK: test AX, 0
71 # CHECK: test ax, 0
7272 0x66 0xa9 0x00 0x00
7373
74 # CHECK: test EAX, 0
74 # CHECK: test eax, 0
7575 0xa9 0x00 0x00 0x00 0x00
7676
77 # CHECK: test RAX, 0
77 # CHECK: test rax, 0
7878 0x48 0xa9 0x00 0x00 0x00 0x00
7979
8080 # CHECK: sysret
104104 # CHECK: retf
105105 0x66 0xcb
106106
107 # CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0
107 # CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0
108108 0xc4 0xe2 0xfd 0x91 0x14 0x4f
109109
110 # CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
110 # CHECK: vpgatherdd xmm10, dword ptr [r15 + 2*xmm9], xmm8
111111 0xc4 0x02 0x39 0x90 0x14 0x4f
112112
113 # CHECK: xsave64 OPAQUE PTR [RAX]
113 # CHECK: xsave64 opaque ptr [rax]
114114 0x48 0x0f 0xae 0x20
115115
116 # CHECK: xrstor64 OPAQUE PTR [RAX]
116 # CHECK: xrstor64 opaque ptr [rax]
117117 0x48 0x0f 0xae 0x28
118118
119 # CHECK: xsaveopt64 OPAQUE PTR [RAX]
119 # CHECK: xsaveopt64 opaque ptr [rax]
120120 0x48 0x0f 0xae 0x30