llvm.org GIT mirror llvm / 41474ba
Add a sanity-check to tablegen to catch the case where isSimpleLoad is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
8 changed file(s) with 25 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
413413 const TargetInstrDesc &TID = I->getDesc();
414414 if (TID.isCall())
415415 Time += 10;
416 else if (TID.isSimpleLoad() || TID.mayStore())
416 else if (TID.mayLoad() || TID.mayStore())
417417 Time += 2;
418418 else
419419 ++Time;
833833 assert(Offset && "This code isn't needed if offset already handled!");
834834
835835 if (isThumb) {
836 if (Desc.isSimpleLoad()) {
836 if (Desc.mayLoad()) {
837837 // Use the destination register to materialize sp + offset.
838838 unsigned TmpReg = MI.getOperand(0).getReg();
839839 bool UseRR = false;
569569
570570
571571 //load address, rellocated gpdist form
572 let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
572 let OutOperandList = (ops GPRC:$RA),
573 InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM),
574 mayLoad = 1 in {
573575 def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
574576 def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
575577 }
588590 def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>;
589591 def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>;
590592 }
591 let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
593 let OutOperandList = (ops GPRC:$RA),
594 InOperandList = (ops s64imm:$DISP, GPRC:$RB),
595 mayLoad = 1 in {
592596 def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>;
593597 def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>;
594598 }
7171
7272 const TargetInstrDesc &TID = TII.get(Opcode);
7373
74 isLoad = TID.isSimpleLoad();
74 isLoad = TID.mayLoad();
7575 isStore = TID.mayStore();
7676
7777 unsigned TSFlags = TID.TSFlags;
486486 PPC970_DGroup_Cracked;
487487
488488 // Update forms.
489 let mayLoad = 1 in
489490 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
490491 ptr_rc:$rA),
491492 "lhau $rD, $disp($rA)", LdStGeneral,
519520
520521
521522 // Update forms.
523 let mayLoad = 1 in {
522524 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
523525 "lbzu $rD, $addr", LdStGeneral,
524526 []>, RegConstraint<"$addr.reg = $ea_result">,
532534 []>, RegConstraint<"$addr.reg = $ea_result">,
533535 NoEncode<"$ea_result">;
534536 }
537 }
535538
536539
537540 // Full 8-byte loads.
543546 "ldx $rD, $src", LdStLD,
544547 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
545548
549 let mayLoad = 1 in
546550 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
547551 "ldu $rD, $addr", LdStLD,
548552 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
682682
683683
684684 // Unindexed (r+i) Loads with Update (preinc).
685 let mayLoad = 1 in {
685686 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
686687 "lbzu $rD, $addr", LdStGeneral,
687688 []>, RegConstraint<"$addr.reg = $ea_result">,
711712 "lfd $rD, $addr", LdStLFD,
712713 []>, RegConstraint<"$addr.reg = $ea_result">,
713714 NoEncode<"$ea_result">;
715 }
714716 }
715717
716718 // Indexed (r+r) Loads.
17581758 MayLoad = true;
17591759 }
17601760
1761 // Sanity-check the isSimpleLoad flag.
1762 if (Inst.isSimpleLoad) {
1763 if (!MayLoad)
1764 fprintf(stderr,
1765 "Warning: mayLoad flag not set or inferred for instruction '%s'"
1766 " which has isSimpleLoad set.\n",
1767 Inst.TheDef->getName().c_str());
1768 }
1769
17611770 if (Inst.neverHasSideEffects) {
17621771 if (HadPattern)
17631772 fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "
10961096
10971097 // Generate MemOperandSDNodes nodes for each memory accesses covered by
10981098 // this pattern.
1099 if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
1099 if (II.mayLoad | II.mayStore) {
11001100 std::vector::const_iterator mi, mie;
11011101 for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
11021102 std::string LSIName = "LSI_" + *mi;