llvm.org GIT mirror llvm / 40b75b2
[ARM GlobalISel] Import MOVi32imm into GlobalISel Make it possible for TableGen to produce code for selecting MOVi32imm. This allows reasonably recent ARM targets to select a lot more constants than before. We achieve this by adding GISelPredicateCode to arm_i32imm. It's impossible to use the exact same code for both DAGISel and GlobalISel, since one uses "Subtarget->" and the other "STI." to refer to the subtarget. Moreover, in GlobalISel we don't have ready access to the MachineFunction, so we need to add a bit of code for obtaining it from the instruction that we're selecting. This is also the reason why it needs to remain a PatLeaf instead of the more specific IntImmLeaf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351056 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 1 year, 8 months ago
2 changed file(s) with 35 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
721721 if (Subtarget->useMovt(*MF))
722722 return true;
723723 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
724 }]>;
724 }]> {
725 // Ideally this would be an IntImmLeaf, but then we wouldn't have access to
726 // the MachineFunction.
727 let GISelPredicateCode = [{
728 const auto &MF = *MI.getParent()->getParent();
729 if (STI.useMovt(MF))
730 return true;
731
732 const auto &MO = MI.getOperand(1);
733 if (!MO.isCImm())
734 return false;
735 return ARM_AM::isSOImmTwoPartVal(MO.getCImm()->getZExtValue());
736 }];
737 }
725738
726739 /// imm0_1 predicate - Immediate in the range [0,1].
727740 def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; }
6363 define void @test_stores() #0 { ret void }
6464
6565 define void @test_gep() { ret void }
66
67 define void @test_MOVi32imm() #3 { ret void }
68
6669 define void @test_constant_imm() { ret void }
6770 define void @test_constant_cimm() { ret void }
71
6872 define void @test_pointer_constant_unconstrained() { ret void }
6973 define void @test_pointer_constant_constrained() { ret void }
7074
14801484 BX_RET 14, $noreg, implicit $r0
14811485 ...
14821486 ---
1487 name: test_MOVi32imm
1488 # CHECK-LABEL: name: test_MOVi32imm
1489 legalized: true
1490 regBankSelected: true
1491 selected: false
1492 # CHECK: selected: true
1493 registers:
1494 - { id: 0, class: gprb }
1495 body: |
1496 bb.0:
1497 %0(s32) = G_CONSTANT 65537
1498 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi32imm 65537
1499
1500 $r0 = COPY %0(s32)
1501 BX_RET 14, $noreg, implicit $r0
1502 ...
1503 ---
14831504 name: test_constant_imm
14841505 # CHECK-LABEL: name: test_constant_imm
14851506 legalized: true