llvm.org GIT mirror llvm / 4071301
[ARM] MVE patterns for VMVN, VORR and VBIC This add simple Q register forms of bitwise not instructions. Differential Revision: https://reviews.llvm.org/D63983 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365214 91177308-0d34-0410-b5e6-96231b3b80d8 David Green 4 months ago
2 changed file(s) with 118 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
15291529 let Inst{0} = 0b0;
15301530 }
15311531
1532 let Predicates = [HasMVEInt] in {
1533 def : Pat<(v16i8 (vnotq (v16i8 MQPR:$val1))),
1534 (v16i8 (MVE_VMVN (v16i8 MQPR:$val1)))>;
1535 def : Pat<(v8i16 (vnotq (v8i16 MQPR:$val1))),
1536 (v8i16 (MVE_VMVN (v8i16 MQPR:$val1)))>;
1537 def : Pat<(v4i32 (vnotq (v4i32 MQPR:$val1))),
1538 (v4i32 (MVE_VMVN (v4i32 MQPR:$val1)))>;
1539 }
1540
15321541 class MVE_bit_ops bit_21_20, bit bit_28>
15331542 : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
15341543 iname, "", "$Qd, $Qn, $Qm", ""> {
15871596 (v8i16 (MVE_VEOR (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
15881597 def : Pat<(v4i32 (xor (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
15891598 (v4i32 (MVE_VEOR (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
1599
1600 def : Pat<(v16i8 (and (v16i8 MQPR:$val1), (vnotq MQPR:$val2))),
1601 (v16i8 (MVE_VBIC (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
1602 def : Pat<(v8i16 (and (v8i16 MQPR:$val1), (vnotq MQPR:$val2))),
1603 (v8i16 (MVE_VBIC (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
1604 def : Pat<(v4i32 (and (v4i32 MQPR:$val1), (vnotq MQPR:$val2))),
1605 (v4i32 (MVE_VBIC (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
1606
1607 def : Pat<(v16i8 (or (v16i8 MQPR:$val1), (vnotq (v16i8 MQPR:$val2)))),
1608 (v16i8 (MVE_VORN (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
1609 def : Pat<(v8i16 (or (v8i16 MQPR:$val1), (vnotq MQPR:$val2))),
1610 (v8i16 (MVE_VORN (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
1611 def : Pat<(v4i32 (or (v4i32 MQPR:$val1), (vnotq MQPR:$val2))),
1612 (v4i32 (MVE_VORN (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
15901613 }
15911614
15921615 class MVE_bit_cmode cmode, dag inOps>
9292 ret <4 x i32> %0
9393 }
9494
95 define arm_aapcs_vfpcc <16 x i8> @v_mvn_i8(<16 x i8> %src) {
96 ; CHECK-LABEL: v_mvn_i8:
97 ; CHECK: @ %bb.0: @ %entry
98 ; CHECK-NEXT: vmvn q0, q0
99 ; CHECK-NEXT: bx lr
100 entry:
101 %0 = xor <16 x i8> %src,
102 ret <16 x i8> %0
103 }
104
105 define arm_aapcs_vfpcc <8 x i16> @v_mvn_i16(<8 x i16> %src) {
106 ; CHECK-LABEL: v_mvn_i16:
107 ; CHECK: @ %bb.0: @ %entry
108 ; CHECK-NEXT: vmvn q0, q0
109 ; CHECK-NEXT: bx lr
110 entry:
111 %0 = xor <8 x i16> %src,
112 ret <8 x i16> %0
113 }
114
115 define arm_aapcs_vfpcc <4 x i32> @v_mvn_i32(<4 x i32> %src) {
116 ; CHECK-LABEL: v_mvn_i32:
117 ; CHECK: @ %bb.0: @ %entry
118 ; CHECK-NEXT: vmvn q0, q0
119 ; CHECK-NEXT: bx lr
120 entry:
121 %0 = xor <4 x i32> %src,
122 ret <4 x i32> %0
123 }
124
125 define arm_aapcs_vfpcc <16 x i8> @v_bic_i8(<16 x i8> %src1, <16 x i8> %src2) {
126 ; CHECK-LABEL: v_bic_i8:
127 ; CHECK: @ %bb.0: @ %entry
128 ; CHECK-NEXT: vbic q0, q1, q0
129 ; CHECK-NEXT: bx lr
130 entry:
131 %0 = xor <16 x i8> %src1,
132 %1 = and <16 x i8> %src2, %0
133 ret <16 x i8> %1
134 }
135
136 define arm_aapcs_vfpcc <8 x i16> @v_bic_i16(<8 x i16> %src1, <8 x i16> %src2) {
137 ; CHECK-LABEL: v_bic_i16:
138 ; CHECK: @ %bb.0: @ %entry
139 ; CHECK-NEXT: vbic q0, q1, q0
140 ; CHECK-NEXT: bx lr
141 entry:
142 %0 = xor <8 x i16> %src1,
143 %1 = and <8 x i16> %src2, %0
144 ret <8 x i16> %1
145 }
146
147 define arm_aapcs_vfpcc <4 x i32> @v_bic_i32(<4 x i32> %src1, <4 x i32> %src2) {
148 ; CHECK-LABEL: v_bic_i32:
149 ; CHECK: @ %bb.0: @ %entry
150 ; CHECK-NEXT: vbic q0, q1, q0
151 ; CHECK-NEXT: bx lr
152 entry:
153 %0 = xor <4 x i32> %src1,
154 %1 = and <4 x i32> %src2, %0
155 ret <4 x i32> %1
156 }
157
158 define arm_aapcs_vfpcc <16 x i8> @v_or_i8(<16 x i8> %src1, <16 x i8> %src2) {
159 ; CHECK-LABEL: v_or_i8:
160 ; CHECK: @ %bb.0: @ %entry
161 ; CHECK-NEXT: vorn q0, q1, q0
162 ; CHECK-NEXT: bx lr
163 entry:
164 %0 = xor <16 x i8> %src1,
165 %1 = or <16 x i8> %src2, %0
166 ret <16 x i8> %1
167 }
168
169 define arm_aapcs_vfpcc <8 x i16> @v_or_i16(<8 x i16> %src1, <8 x i16> %src2) {
170 ; CHECK-LABEL: v_or_i16:
171 ; CHECK: @ %bb.0: @ %entry
172 ; CHECK-NEXT: vorn q0, q1, q0
173 ; CHECK-NEXT: bx lr
174 entry:
175 %0 = xor <8 x i16> %src1,
176 %1 = or <8 x i16> %src2, %0
177 ret <8 x i16> %1
178 }
179
180 define arm_aapcs_vfpcc <4 x i32> @v_or_i32(<4 x i32> %src1, <4 x i32> %src2) {
181 ; CHECK-LABEL: v_or_i32:
182 ; CHECK: @ %bb.0: @ %entry
183 ; CHECK-NEXT: vorn q0, q1, q0
184 ; CHECK-NEXT: bx lr
185 entry:
186 %0 = xor <4 x i32> %src1,
187 %1 = or <4 x i32> %src2, %0
188 ret <4 x i32> %1
189 }