llvm.org GIT mirror llvm / 403e4a4
Rename. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34011 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
1 changed file(s) with 7 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
370370 BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx);
371371 }
372372
373 /// emitThumbRegPlusConstPool - Emits a series of instructions to materialize
374 /// a destreg = basereg + immediate in Thumb code. Load the immediate from a
373 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
374 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
375 /// in a register using mov / mvn sequences or load the immediate from a
375376 /// constpool entry.
376377 static
377 void emitThumbRegPlusConstPool(MachineBasicBlock &MBB,
378 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
378379 MachineBasicBlock::iterator &MBBI,
379380 unsigned DestReg, unsigned BaseReg,
380381 int NumBytes, bool CanChangeCC,
470471 if (NumMIs > Threshold) {
471472 // This will expand into too many instructions. Load the immediate from a
472473 // constpool entry.
473 emitThumbRegPlusConstPool(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
474 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
474475 return;
475476 }
476477
794795 bool UseRR = false;
795796 if (Opcode == ARM::tRestore) {
796797 if (FrameReg == ARM::SP)
797 emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,Offset,false,TII);
798 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
798799 else {
799800 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
800801 UseRR = true;
827828 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
828829 if (Opcode == ARM::tSpill) {
829830 if (FrameReg == ARM::SP)
830 emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,Offset,false,TII);
831 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
831832 else {
832833 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
833834 UseRR = true;