llvm.org GIT mirror llvm / 4009e89
[Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test to make sure it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238947 91177308-0d34-0410-b5e6-96231b3b80d8 Colin LeMahieu 5 years ago
6 changed file(s) with 457 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
8989 ELF_RELOC(R_HEX_TPREL_32_6_X, 83)
9090 ELF_RELOC(R_HEX_TPREL_16_X, 84)
9191 ELF_RELOC(R_HEX_TPREL_11_X, 85)
92 ELF_RELOC(R_HEX_LD_PLT_B22_PCREL, 86)
93 ELF_RELOC(R_HEX_LD_GOT_LO16, 87)
94 ELF_RELOC(R_HEX_LD_GOT_HI16, 88)
95 ELF_RELOC(R_HEX_LD_GOT_32, 89)
96 ELF_RELOC(R_HEX_LD_GOT_16, 90)
97 ELF_RELOC(R_HEX_LD_GOT_32_6_X, 91)
98 ELF_RELOC(R_HEX_LD_GOT_16_X, 92)
99 ELF_RELOC(R_HEX_LD_GOT_11_X, 93)
1414 #include "llvm/MC/MCAsmBackend.h"
1515 #include "llvm/MC/MCAssembler.h"
1616 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCFixupKindInfo.h"
18 #include "llvm/Support/TargetRegistry.h"
1719
1820 using namespace llvm;
1921 using namespace Hexagon;
2123 namespace {
2224
2325 class HexagonAsmBackend : public MCAsmBackend {
26 uint8_t OSABI;
27 StringRef CPU;
2428 mutable uint64_t relaxedCnt;
2529 std::unique_ptr MCII;
2630 std::unique_ptr RelaxTarget;
2731 public:
28 HexagonAsmBackend(Target const & /*T*/) :
29 MCII (createHexagonMCInstrInfo()), RelaxTarget(new MCInst *){}
30
31 unsigned getNumFixupKinds() const override { return 0; }
32 HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) :
33 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *){}
34
35 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
36 return createHexagonELFObjectWriter(OS, OSABI, CPU);
37 }
38
39 unsigned getNumFixupKinds() const override {
40 return Hexagon::NumTargetFixupKinds;
41 }
42
43 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
44 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
45 // This table *must* be in same the order of fixup_* kinds in
46 // HexagonFixupKinds.h.
47 //
48 // namei offset bits flags
49 {"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
50 {"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
51 {"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
52 {"fixup_Hexagon_LO16", 0, 32, 0},
53 {"fixup_Hexagon_HI16", 0, 32, 0},
54 {"fixup_Hexagon_32", 0, 32, 0},
55 {"fixup_Hexagon_16", 0, 32, 0},
56 {"fixup_Hexagon_8", 0, 32, 0},
57 {"fixup_Hexagon_GPREL16_0", 0, 32, 0},
58 {"fixup_Hexagon_GPREL16_1", 0, 32, 0},
59 {"fixup_Hexagon_GPREL16_2", 0, 32, 0},
60 {"fixup_Hexagon_GPREL16_3", 0, 32, 0},
61 {"fixup_Hexagon_HL16", 0, 32, 0},
62 {"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
63 {"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
64 {"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_Hexagon_32_6_X", 0, 32, 0},
66 {"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
67 {"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
68 {"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
69 {"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_Hexagon_16_X", 0, 32, 0},
72 {"fixup_Hexagon_12_X", 0, 32, 0},
73 {"fixup_Hexagon_11_X", 0, 32, 0},
74 {"fixup_Hexagon_10_X", 0, 32, 0},
75 {"fixup_Hexagon_9_X", 0, 32, 0},
76 {"fixup_Hexagon_8_X", 0, 32, 0},
77 {"fixup_Hexagon_7_X", 0, 32, 0},
78 {"fixup_Hexagon_6_X", 0, 32, 0},
79 {"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
80 {"fixup_Hexagon_COPY", 0, 32, 0},
81 {"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
82 {"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
83 {"fixup_Hexagon_RELATIVE", 0, 32, 0},
84 {"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
85 {"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
86 {"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
87 {"fixup_Hexagon_GOTREL_32", 0, 32, 0},
88 {"fixup_Hexagon_GOT_LO16", 0, 32, 0},
89 {"fixup_Hexagon_GOT_HI16", 0, 32, 0},
90 {"fixup_Hexagon_GOT_32", 0, 32, 0},
91 {"fixup_Hexagon_GOT_16", 0, 32, 0},
92 {"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
93 {"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
94 {"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
95 {"fixup_Hexagon_DTPREL_32", 0, 32, 0},
96 {"fixup_Hexagon_DTPREL_16", 0, 32, 0},
97 {"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
98 {"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
99 {"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
100 {"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
101 {"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
102 {"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
103 {"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
104 {"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
105 {"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
106 {"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
107 {"fixup_Hexagon_IE_LO16", 0, 32, 0},
108 {"fixup_Hexagon_IE_HI16", 0, 32, 0},
109 {"fixup_Hexagon_IE_32", 0, 32, 0},
110 {"fixup_Hexagon_IE_16", 0, 32, 0},
111 {"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
112 {"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
113 {"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
114 {"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
115 {"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
116 {"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
117 {"fixup_Hexagon_TPREL_32", 0, 32, 0},
118 {"fixup_Hexagon_TPREL_16", 0, 32, 0},
119 {"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
120 {"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
121 {"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
122 {"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
123 {"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
124 {"fixup_Hexagon_GOT_16_X", 0, 32, 0},
125 {"fixup_Hexagon_GOT_11_X", 0, 32, 0},
126 {"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
127 {"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
128 {"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
129 {"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
130 {"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
131 {"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
132 {"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
133 {"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
134 {"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
135 {"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
136 {"fixup_Hexagon_IE_16_X", 0, 32, 0},
137 {"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
138 {"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
139 {"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
140 {"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
141 {"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
142 {"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
143
144 if (Kind < FirstTargetFixupKind) {
145 return MCAsmBackend::getFixupKindInfo(Kind);
146 }
147
148 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
149 "Invalid kind!");
150 return Infos[Kind - FirstTargetFixupKind];
151 }
32152
33153 void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
34154 unsigned /*DataSize*/, uint64_t /*Value*/,
163283 };
164284 } // end anonymous namespace
165285
166 namespace {
167 class ELFHexagonAsmBackend : public HexagonAsmBackend {
168 uint8_t OSABI;
169
170 public:
171 ELFHexagonAsmBackend(Target const &T, uint8_t OSABI)
172 : HexagonAsmBackend(T), OSABI(OSABI) {}
173
174 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
175 StringRef CPU("HexagonV4");
176 return createHexagonELFObjectWriter(OS, OSABI, CPU);
177 }
178 };
179 } // end anonymous namespace
180
181286 namespace llvm {
182287 MCAsmBackend *createHexagonAsmBackend(Target const &T,
183288 MCRegisterInfo const & /*MRI*/,
184 StringRef TT, StringRef /*CPU*/) {
289 StringRef TT, StringRef CPU) {
185290 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
186 return new ELFHexagonAsmBackend(T, OSABI);
291 return new HexagonAsmBackend(T, OSABI, CPU);
187292 }
188293 }
77 //===----------------------------------------------------------------------===//
88
99 #include "Hexagon.h"
10 #include "MCTargetDesc/HexagonFixupKinds.h"
1011 #include "llvm/MC/MCAssembler.h"
1112 #include "llvm/MC/MCELFObjectWriter.h"
1213 #include "llvm/Support/Debug.h"
3940 unsigned HexagonELFObjectWriter::GetRelocType(MCValue const &/*Target*/,
4041 MCFixup const &Fixup,
4142 bool IsPCRel) const {
43 // determine the type of the relocation
4244 unsigned Type = (unsigned)ELF::R_HEX_NONE;
43 llvm::MCFixupKind Kind = Fixup.getKind();
45 unsigned Kind = (unsigned)Fixup.getKind();
4446
4547 switch (Kind) {
46 default:
47 DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
48 llvm_unreachable("Unimplemented Fixup kind!");
49 break;
50 case FK_Data_4:
51 Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
52 break;
48 default:
49 DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
50 llvm_unreachable("Unimplemented Fixup kind!");
51 break;
52 case FK_Data_4:
53 Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
54 break;
55 case FK_PCRel_4:
56 Type = ELF::R_HEX_32_PCREL;
57 break;
58 case FK_Data_2:
59 Type = ELF::R_HEX_16;
60 break;
61 case FK_Data_1:
62 Type = ELF::R_HEX_8;
63 break;
64 case fixup_Hexagon_B22_PCREL:
65 Type = ELF::R_HEX_B22_PCREL;
66 break;
67 case fixup_Hexagon_B15_PCREL:
68 Type = ELF::R_HEX_B15_PCREL;
69 break;
70 case fixup_Hexagon_B7_PCREL:
71 Type = ELF::R_HEX_B7_PCREL;
72 break;
73 case fixup_Hexagon_LO16:
74 Type = ELF::R_HEX_LO16;
75 break;
76 case fixup_Hexagon_HI16:
77 Type = ELF::R_HEX_HI16;
78 break;
79 case fixup_Hexagon_32:
80 Type = ELF::R_HEX_32;
81 break;
82 case fixup_Hexagon_16:
83 Type = ELF::R_HEX_16;
84 break;
85 case fixup_Hexagon_8:
86 Type = ELF::R_HEX_8;
87 break;
88 case fixup_Hexagon_GPREL16_0:
89 Type = ELF::R_HEX_GPREL16_0;
90 break;
91 case fixup_Hexagon_GPREL16_1:
92 Type = ELF::R_HEX_GPREL16_1;
93 break;
94 case fixup_Hexagon_GPREL16_2:
95 Type = ELF::R_HEX_GPREL16_2;
96 break;
97 case fixup_Hexagon_GPREL16_3:
98 Type = ELF::R_HEX_GPREL16_3;
99 break;
100 case fixup_Hexagon_HL16:
101 Type = ELF::R_HEX_HL16;
102 break;
103 case fixup_Hexagon_B13_PCREL:
104 Type = ELF::R_HEX_B13_PCREL;
105 break;
106 case fixup_Hexagon_B9_PCREL:
107 Type = ELF::R_HEX_B9_PCREL;
108 break;
109 case fixup_Hexagon_B32_PCREL_X:
110 Type = ELF::R_HEX_B32_PCREL_X;
111 break;
112 case fixup_Hexagon_32_6_X:
113 Type = ELF::R_HEX_32_6_X;
114 break;
115 case fixup_Hexagon_B22_PCREL_X:
116 Type = ELF::R_HEX_B22_PCREL_X;
117 break;
118 case fixup_Hexagon_B15_PCREL_X:
119 Type = ELF::R_HEX_B15_PCREL_X;
120 break;
121 case fixup_Hexagon_B13_PCREL_X:
122 Type = ELF::R_HEX_B13_PCREL_X;
123 break;
124 case fixup_Hexagon_B9_PCREL_X:
125 Type = ELF::R_HEX_B9_PCREL_X;
126 break;
127 case fixup_Hexagon_B7_PCREL_X:
128 Type = ELF::R_HEX_B7_PCREL_X;
129 break;
130 case fixup_Hexagon_16_X:
131 Type = ELF::R_HEX_16_X;
132 break;
133 case fixup_Hexagon_12_X:
134 Type = ELF::R_HEX_12_X;
135 break;
136 case fixup_Hexagon_11_X:
137 Type = ELF::R_HEX_11_X;
138 break;
139 case fixup_Hexagon_10_X:
140 Type = ELF::R_HEX_10_X;
141 break;
142 case fixup_Hexagon_9_X:
143 Type = ELF::R_HEX_9_X;
144 break;
145 case fixup_Hexagon_8_X:
146 Type = ELF::R_HEX_8_X;
147 break;
148 case fixup_Hexagon_7_X:
149 Type = ELF::R_HEX_7_X;
150 break;
151 case fixup_Hexagon_6_X:
152 Type = ELF::R_HEX_6_X;
153 break;
154 case fixup_Hexagon_32_PCREL:
155 Type = ELF::R_HEX_32_PCREL;
156 break;
157 case fixup_Hexagon_COPY:
158 Type = ELF::R_HEX_COPY;
159 break;
160 case fixup_Hexagon_GLOB_DAT:
161 Type = ELF::R_HEX_GLOB_DAT;
162 break;
163 case fixup_Hexagon_JMP_SLOT:
164 Type = ELF::R_HEX_JMP_SLOT;
165 break;
166 case fixup_Hexagon_RELATIVE:
167 Type = ELF::R_HEX_RELATIVE;
168 break;
169 case fixup_Hexagon_PLT_B22_PCREL:
170 Type = ELF::R_HEX_PLT_B22_PCREL;
171 break;
172 case fixup_Hexagon_GOTREL_LO16:
173 Type = ELF::R_HEX_GOTREL_LO16;
174 break;
175 case fixup_Hexagon_GOTREL_HI16:
176 Type = ELF::R_HEX_GOTREL_HI16;
177 break;
178 case fixup_Hexagon_GOTREL_32:
179 Type = ELF::R_HEX_GOTREL_32;
180 break;
181 case fixup_Hexagon_GOT_LO16:
182 Type = ELF::R_HEX_GOT_LO16;
183 break;
184 case fixup_Hexagon_GOT_HI16:
185 Type = ELF::R_HEX_GOT_HI16;
186 break;
187 case fixup_Hexagon_GOT_32:
188 Type = ELF::R_HEX_GOT_32;
189 break;
190 case fixup_Hexagon_GOT_16:
191 Type = ELF::R_HEX_GOT_16;
192 break;
193 case fixup_Hexagon_DTPMOD_32:
194 Type = ELF::R_HEX_DTPMOD_32;
195 break;
196 case fixup_Hexagon_DTPREL_LO16:
197 Type = ELF::R_HEX_DTPREL_LO16;
198 break;
199 case fixup_Hexagon_DTPREL_HI16:
200 Type = ELF::R_HEX_DTPREL_HI16;
201 break;
202 case fixup_Hexagon_DTPREL_32:
203 Type = ELF::R_HEX_DTPREL_32;
204 break;
205 case fixup_Hexagon_DTPREL_16:
206 Type = ELF::R_HEX_DTPREL_16;
207 break;
208 case fixup_Hexagon_GD_PLT_B22_PCREL:
209 Type = ELF::R_HEX_GD_PLT_B22_PCREL;
210 break;
211 case fixup_Hexagon_LD_PLT_B22_PCREL:
212 Type = ELF::R_HEX_LD_PLT_B22_PCREL;
213 break;
214 case fixup_Hexagon_GD_GOT_LO16:
215 Type = ELF::R_HEX_GD_GOT_LO16;
216 break;
217 case fixup_Hexagon_GD_GOT_HI16:
218 Type = ELF::R_HEX_GD_GOT_HI16;
219 break;
220 case fixup_Hexagon_GD_GOT_32:
221 Type = ELF::R_HEX_GD_GOT_32;
222 break;
223 case fixup_Hexagon_GD_GOT_16:
224 Type = ELF::R_HEX_GD_GOT_16;
225 break;
226 case fixup_Hexagon_LD_GOT_LO16:
227 Type = ELF::R_HEX_LD_GOT_LO16;
228 break;
229 case fixup_Hexagon_LD_GOT_HI16:
230 Type = ELF::R_HEX_LD_GOT_HI16;
231 break;
232 case fixup_Hexagon_LD_GOT_32:
233 Type = ELF::R_HEX_LD_GOT_32;
234 break;
235 case fixup_Hexagon_LD_GOT_16:
236 Type = ELF::R_HEX_LD_GOT_16;
237 break;
238 case fixup_Hexagon_IE_LO16:
239 Type = ELF::R_HEX_IE_LO16;
240 break;
241 case fixup_Hexagon_IE_HI16:
242 Type = ELF::R_HEX_IE_HI16;
243 break;
244 case fixup_Hexagon_IE_32:
245 Type = ELF::R_HEX_IE_32;
246 break;
247 case fixup_Hexagon_IE_GOT_LO16:
248 Type = ELF::R_HEX_IE_GOT_LO16;
249 break;
250 case fixup_Hexagon_IE_GOT_HI16:
251 Type = ELF::R_HEX_IE_GOT_HI16;
252 break;
253 case fixup_Hexagon_IE_GOT_32:
254 Type = ELF::R_HEX_IE_GOT_32;
255 break;
256 case fixup_Hexagon_IE_GOT_16:
257 Type = ELF::R_HEX_IE_GOT_16;
258 break;
259 case fixup_Hexagon_TPREL_LO16:
260 Type = ELF::R_HEX_TPREL_LO16;
261 break;
262 case fixup_Hexagon_TPREL_HI16:
263 Type = ELF::R_HEX_TPREL_HI16;
264 break;
265 case fixup_Hexagon_TPREL_32:
266 Type = ELF::R_HEX_TPREL_32;
267 break;
268 case fixup_Hexagon_TPREL_16:
269 Type = ELF::R_HEX_TPREL_16;
270 break;
271 case fixup_Hexagon_6_PCREL_X:
272 Type = ELF::R_HEX_6_PCREL_X;
273 break;
274 case fixup_Hexagon_GOTREL_32_6_X:
275 Type = ELF::R_HEX_GOTREL_32_6_X;
276 break;
277 case fixup_Hexagon_GOTREL_16_X:
278 Type = ELF::R_HEX_GOTREL_16_X;
279 break;
280 case fixup_Hexagon_GOTREL_11_X:
281 Type = ELF::R_HEX_GOTREL_11_X;
282 break;
283 case fixup_Hexagon_GOT_32_6_X:
284 Type = ELF::R_HEX_GOT_32_6_X;
285 break;
286 case fixup_Hexagon_GOT_16_X:
287 Type = ELF::R_HEX_GOT_16_X;
288 break;
289 case fixup_Hexagon_GOT_11_X:
290 Type = ELF::R_HEX_GOT_11_X;
291 break;
292 case fixup_Hexagon_DTPREL_32_6_X:
293 Type = ELF::R_HEX_DTPREL_32_6_X;
294 break;
295 case fixup_Hexagon_DTPREL_16_X:
296 Type = ELF::R_HEX_DTPREL_16_X;
297 break;
298 case fixup_Hexagon_DTPREL_11_X:
299 Type = ELF::R_HEX_DTPREL_11_X;
300 break;
301 case fixup_Hexagon_GD_GOT_32_6_X:
302 Type = ELF::R_HEX_GD_GOT_32_6_X;
303 break;
304 case fixup_Hexagon_GD_GOT_16_X:
305 Type = ELF::R_HEX_GD_GOT_16_X;
306 break;
307 case fixup_Hexagon_GD_GOT_11_X:
308 Type = ELF::R_HEX_GD_GOT_11_X;
309 break;
310 case fixup_Hexagon_LD_GOT_32_6_X:
311 Type = ELF::R_HEX_LD_GOT_32_6_X;
312 break;
313 case fixup_Hexagon_LD_GOT_16_X:
314 Type = ELF::R_HEX_LD_GOT_16_X;
315 break;
316 case fixup_Hexagon_LD_GOT_11_X:
317 Type = ELF::R_HEX_LD_GOT_11_X;
318 break;
319 case fixup_Hexagon_IE_32_6_X:
320 Type = ELF::R_HEX_IE_32_6_X;
321 break;
322 case fixup_Hexagon_IE_16_X:
323 Type = ELF::R_HEX_IE_16_X;
324 break;
325 case fixup_Hexagon_IE_GOT_32_6_X:
326 Type = ELF::R_HEX_IE_GOT_32_6_X;
327 break;
328 case fixup_Hexagon_IE_GOT_16_X:
329 Type = ELF::R_HEX_IE_GOT_16_X;
330 break;
331 case fixup_Hexagon_IE_GOT_11_X:
332 Type = ELF::R_HEX_IE_GOT_11_X;
333 break;
334 case fixup_Hexagon_TPREL_32_6_X:
335 Type = ELF::R_HEX_TPREL_32_6_X;
336 break;
337 case fixup_Hexagon_TPREL_16_X:
338 Type = ELF::R_HEX_TPREL_16_X;
339 break;
340 case fixup_Hexagon_TPREL_11_X:
341 Type = ELF::R_HEX_TPREL_11_X;
342 break;
53343 }
54344 return Type;
55345 }
111111 TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
112112 createHexagonMCCodeEmitter);
113113
114 // Register the asm backend
115 TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
116 createHexagonAsmBackend);
117
114118 // Register the MC Inst Printer
115119 TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
116120 createHexagonMCInstPrinter);
0 ; RUN: llc -march=hexagon -filetype=obj < %s | llvm-readobj -file-headers | FileCheck %s
1
2 ; CHECK: OS/ABI: SystemV (0x0)
3 define void @foo() {
4 ret void
5 }
6
0 ; RUN: llc -march=hexagon -filetype=obj < %s | llvm-objdump -d -r - | FileCheck %s
1
2 declare void @bar()
3
4 define void @foo() {
5 call void @bar()
6 ret void
7 }
8
9
10 ; CHECK: { allocframe(#0) }
11 ; CHECK: { call 0 }
12 ; CHECK: 00000004: R_HEX_B22_PCREL
13 ; CHECK: { dealloc_return }