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Merging r262728: ------------------------------------------------------------------------ r262728 | thomas.stellard | 2016-03-04 10:02:01 -0800 (Fri, 04 Mar 2016) | 19 lines AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserter Summary: This allows us to use virtual registers when we need extra registers for inserting spill instructions in SIRegisterInfo:eliminateFrameIndex(). Once all the frame indices have been eliminated, the PrologEpilogueInserter does an extra pass over the program to replace all virtual registers with physical ones. This allows us to make more efficient use of our emergency spill slots, so we only need to create one. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17591 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271721 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
2 changed file(s) with 16 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
179179
180180 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
181181 return Fn.getFrameInfo()->hasStackObjects();
182 }
183
184 bool
185 SIRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
186 return MF.getFrameInfo()->hasStackObjects();
182187 }
183188
184189 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
221226 unsigned Value,
222227 unsigned ScratchRsrcReg,
223228 unsigned ScratchOffset,
224 int64_t Offset,
225 RegScavenger *RS) const {
229 int64_t Offset) const {
226230
227231 MachineBasicBlock *MBB = MI->getParent();
228 const MachineFunction *MF = MI->getParent()->getParent();
232 MachineFunction *MF = MI->getParent()->getParent();
233 MachineRegisterInfo &MRI = MF->getRegInfo();
229234 const SIInstrInfo *TII =
230235 static_cast(MF->getSubtarget().getInstrInfo());
231236 LLVMContext &Ctx = MF->getFunction()->getContext();
240245 unsigned Size = NumSubRegs * 4;
241246
242247 if (!isUInt<12>(Offset + Size)) {
243 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
248 SOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
244249 if (SOffset == AMDGPU::NoRegister) {
245250 RanOutOfSGPRs = true;
246251 SOffset = AMDGPU::SGPR0;
282287 int SPAdj, unsigned FIOperandNum,
283288 RegScavenger *RS) const {
284289 MachineFunction *MF = MI->getParent()->getParent();
290 MachineRegisterInfo &MRI = MF->getRegInfo();
285291 MachineBasicBlock *MBB = MI->getParent();
286292 SIMachineFunctionInfo *MFI = MF->getInfo();
287293 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
374380 TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
375381 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
376382 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
377 FrameInfo->getObjectOffset(Index), RS);
383 FrameInfo->getObjectOffset(Index));
378384 MI->eraseFromParent();
379385 break;
380386 case AMDGPU::SI_SPILL_V32_RESTORE:
387393 TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
388394 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
389395 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
390 FrameInfo->getObjectOffset(Index), RS);
396 FrameInfo->getObjectOffset(Index));
391397 MI->eraseFromParent();
392398 break;
393399 }
396402 int64_t Offset = FrameInfo->getObjectOffset(Index);
397403 FIOp.ChangeToImmediate(Offset);
398404 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
399 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
405 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
400406 BuildMI(*MBB, MI, MI->getDebugLoc(),
401407 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
402408 .addImm(Offset);
4747 unsigned Idx) const override;
4848
4949 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
50
51 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
5052
5153 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
5254 unsigned FIOperandNum,
161163 void buildScratchLoadStore(MachineBasicBlock::iterator MI,
162164 unsigned LoadStoreOp, unsigned Value,
163165 unsigned ScratchRsrcReg, unsigned ScratchOffset,
164 int64_t Offset, RegScavenger *RS) const;
166 int64_t Offset) const;
165167 };
166168
167169 } // End namespace llvm