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[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591 Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308740 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
14 changed file(s) with 117996 addition(s) and 115158 deletion(s). Raw diff Collapse all Expand all
173173 bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
174174 SDValue &Clamp) const;
175175
176 bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;
177 bool SelectVOP3OpSel0(SDValue In, SDValue &Src, SDValue &SrcMods,
178 SDValue &Clamp) const;
179
180 bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
181 bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
182 SDValue &Clamp) const;
183
176184 void SelectADD_SUB_I64(SDNode *N);
177185 void SelectUADDO_USUBO(SDNode *N);
178186 void SelectDIV_SCALE(SDNode *N);
18631871 return SelectVOP3PMods(In, Src, SrcMods);
18641872 }
18651873
1874 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src,
1875 SDValue &SrcMods) const {
1876 Src = In;
1877 // FIXME: Handle op_sel
1878 SrcMods = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1879 return true;
1880 }
1881
1882 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel0(SDValue In, SDValue &Src,
1883 SDValue &SrcMods,
1884 SDValue &Clamp) const {
1885 SDLoc SL(In);
1886
1887 // FIXME: Handle clamp
1888 Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
1889
1890 return SelectVOP3OpSel(In, Src, SrcMods);
1891 }
1892
1893 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src,
1894 SDValue &SrcMods) const {
1895 // FIXME: Handle op_sel
1896 return SelectVOP3Mods(In, Src, SrcMods);
1897 }
1898
1899 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods0(SDValue In, SDValue &Src,
1900 SDValue &SrcMods,
1901 SDValue &Clamp) const {
1902 SDLoc SL(In);
1903
1904 // FIXME: Handle clamp
1905 Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
1906
1907 return SelectVOP3OpSelMods(In, Src, SrcMods);
1908 }
1909
18661910 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
18671911 const AMDGPUTargetLowering& Lowering =
18681912 *static_cast(getTargetLowering());
10591059
10601060 void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
10611061 OptionalImmIndexMap &OptionalIdx);
1062 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
10621063 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
10631064 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
10641065
26872688
26882689 // FIXME: How to verify the number of elements matches the number of src
26892690 // operands?
2690 for (int I = 0; I < 3; ++I) {
2691 for (int I = 0; I < 4; ++I) {
26912692 if (I != 0) {
26922693 if (getLexer().is(AsmToken::RBrac))
26932694 break;
40874088 return MatchOperand_NoMatch;
40884089 }
40894090
4091 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands) {
4092 cvtVOP3P(Inst, Operands);
4093
4094 int Opc = Inst.getOpcode();
4095
4096 int SrcNum;
4097 const int Ops[] = { AMDGPU::OpName::src0,
4098 AMDGPU::OpName::src1,
4099 AMDGPU::OpName::src2 };
4100 for (SrcNum = 0;
4101 SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1;
4102 ++SrcNum);
4103 assert(SrcNum > 0);
4104
4105 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
4106 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
4107
4108 if ((OpSel & (1 << SrcNum)) != 0) {
4109 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
4110 uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
4111 Inst.getOperand(ModIdx).setImm(ModVal | SISrcMods::DST_OP_SEL);
4112 }
4113 }
4114
40904115 static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
40914116 // 1. This operand is input modifiers
40924117 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
41714196 int Opc = Inst.getOpcode();
41724197
41734198 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
4174 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1);
4199
4200 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
4201 if (OpSelHiIdx != -1) {
4202 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1);
4203 }
41754204
41764205 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);
41774206 if (NegLoIdx != -1) {
41874216 AMDGPU::OpName::src2_modifiers };
41884217
41894218 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
4190 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
41914219
41924220 unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
4193 unsigned OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();
4221 unsigned OpSelHi = 0;
41944222 unsigned NegLo = 0;
41954223 unsigned NegHi = 0;
4224
4225 if (OpSelHiIdx != -1) {
4226 OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();
4227 }
41964228
41974229 if (NegLoIdx != -1) {
41984230 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);
802802 }
803803 }
804804
805 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod) {
805 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
806 bool HasDstSel) {
806807 int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
807808
808809 for (int I = 0; I < NumOps; ++I) {
810811 return false;
811812 }
812813
814 if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
815 return false;
816
813817 return true;
814818 }
815819
816 static void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
817 raw_ostream &O) {
820 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
821 StringRef Name,
822 unsigned Mod,
823 raw_ostream &O) {
818824 unsigned Opc = MI->getOpcode();
819825 int NumOps = 0;
820826 int Ops[3];
829835 Ops[NumOps++] = MI->getOperand(Idx).getImm();
830836 }
831837
832 if (allOpsDefaultValue(Ops, NumOps, Mod))
838 const bool HasDstSel =
839 NumOps > 0 &&
840 Mod == SISrcMods::OP_SEL_0 &&
841 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
842
843 if (allOpsDefaultValue(Ops, NumOps, Mod, HasDstSel))
833844 return;
834845
835846 O << Name;
838849 O << ',';
839850
840851 O << !!(Ops[I] & Mod);
852 }
853
854 if (HasDstSel) {
855 O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
841856 }
842857
843858 O << ']';
126126 const MCSubtargetInfo &STI, raw_ostream &O);
127127 void printSDWADstUnused(const MCInst *MI, unsigned OpNo,
128128 const MCSubtargetInfo &STI, raw_ostream &O);
129 void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
130 raw_ostream &O);
129131 void printOpSel(const MCInst *MI, unsigned OpNo,
130132 const MCSubtargetInfo &STI, raw_ostream &O);
131133 void printOpSelHi(const MCInst *MI, unsigned OpNo,
6666 SCALAR_STORE = UINT64_C(1) << 39,
6767 FIXED_SIZE = UINT64_C(1) << 40,
6868 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
69 HasFPClamp = UINT64_C(1) << 42
69 HasFPClamp = UINT64_C(1) << 42,
70 VOP3_OPSEL = UINT64_C(1) << 43
7071 };
7172
7273 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
136137 SEXT = 1 << 0, // Integer sign-extend modifier
137138 NEG_HI = ABS, // Floating-point negate high packed component modifier.
138139 OP_SEL_0 = 1 << 2,
139 OP_SEL_1 = 1 << 3
140 OP_SEL_1 = 1 << 3,
141 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
140142 };
141143 }
142144
8282 // the clamp modifier has floating point semantics.
8383 field bit FPClamp = 0;
8484
85 // This bit indicates that this is a VOP3 opcode which supports op_sel
86 // modifier (gfx9 only).
87 field bit VOP3_OPSEL = 0;
88
8589 // These need to be kept in sync with the enum in SIInstrFlags.
8690 let TSFlags{0} = SALU;
8791 let TSFlags{1} = VALU;
126130 let TSFlags{40} = FixedSize;
127131 let TSFlags{41} = VOPAsmPrefer32Bit;
128132 let TSFlags{42} = FPClamp;
133 let TSFlags{43} = VOP3_OPSEL;
129134
130135 let SchedRW = [Write32Bit];
131136
658658 def Int32InputMods : IntInputMods;
659659 def Int64InputMods : IntInputMods;
660660
661 class OpSelModsMatchClass : AsmOperandClass {
662 let Name = "OpSelMods";
663 let ParserMethod = "parseRegOrImm";
664 let PredicateMethod = "isRegOrImm";
665 }
666
667 def IntOpSelModsMatchClass : OpSelModsMatchClass;
668 def IntOpSelMods : InputMods;
669
661670 def FPRegSDWAInputModsMatchClass : AsmOperandClass {
662671 let Name = "SDWARegWithFPInputMods";
663672 let ParserMethod = "parseRegWithFPInputMods";
749758 def VOP3PMods : ComplexPattern;
750759 def VOP3PMods0 : ComplexPattern;
751760
761 def VOP3OpSel : ComplexPattern;
762 def VOP3OpSel0 : ComplexPattern;
763
764 def VOP3OpSelMods : ComplexPattern;
765 def VOP3OpSelMods0 : ComplexPattern;
752766
753767 //===----------------------------------------------------------------------===//
754768 // SI assembler operands
770784 int NEG_HI = ABS;
771785 int OP_SEL_0 = 4;
772786 int OP_SEL_1 = 8;
787 int DST_OP_SEL = 8;
773788 }
774789
775790 def DSTCLAMP {
10171032 ),
10181033 Int32InputMods)
10191034 );
1035 }
1036
1037 class getOpSelMod {
1038 Operand ret = !if(!eq(VT.Value, f16.Value), FP16InputMods, IntOpSelMods);
10201039 }
10211040
10221041 // Return type of input modifiers operand specified input operand for DPP
11321151 );
11331152 }
11341153
1154 class getInsVOP3OpSel
1155 RegisterOperand Src1RC,
1156 RegisterOperand Src2RC,
1157 int NumSrcArgs,
1158 bit HasClamp,
1159 Operand Src0Mod,
1160 Operand Src1Mod,
1161 Operand Src2Mod> {
1162 dag ret = !if (!eq(NumSrcArgs, 2),
1163 !if (HasClamp,
1164 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1165 Src1Mod:$src1_modifiers, Src1RC:$src1,
1166 clampmod:$clamp,
1167 op_sel:$op_sel),
1168 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1169 Src1Mod:$src1_modifiers, Src1RC:$src1,
1170 op_sel:$op_sel)),
1171 // else NumSrcArgs == 3
1172 !if (HasClamp,
1173 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1174 Src1Mod:$src1_modifiers, Src1RC:$src1,
1175 Src2Mod:$src2_modifiers, Src2RC:$src2,
1176 clampmod:$clamp,
1177 op_sel:$op_sel),
1178 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1179 Src1Mod:$src1_modifiers, Src1RC:$src1,
1180 Src2Mod:$src2_modifiers, Src2RC:$src2,
1181 op_sel:$op_sel))
1182 );
1183 }
1184
11351185 class getInsDPP
11361186 bit HasModifiers, Operand Src0Mod, Operand Src1Mod> {
11371187
12781328 string ret = dst#", "#src0#src1#src2#"$op_sel$op_sel_hi"#mods#clamp;
12791329 }
12801330
1331 class getAsmVOP3OpSel
1332 bit HasClamp,
1333 bit Src0HasMods,
1334 bit Src1HasMods,
1335 bit Src2HasMods> {
1336 string dst = " $vdst";
1337
1338 string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1339 string isrc1 = !if(!eq(NumSrcArgs, 1), "",
1340 !if(!eq(NumSrcArgs, 2), " $src1",
1341 " $src1,"));
1342 string isrc2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1343
1344 string fsrc0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1345 string fsrc1 = !if(!eq(NumSrcArgs, 1), "",
1346 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1347 " $src1_modifiers,"));
1348 string fsrc2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1349
1350 string src0 = !if(Src0HasMods, fsrc0, isrc0);
1351 string src1 = !if(Src1HasMods, fsrc1, isrc1);
1352 string src2 = !if(Src2HasMods, fsrc2, isrc2);
1353
1354 string clamp = !if(HasClamp, "$clamp", "");
1355
1356 string ret = dst#", "#src0#src1#src2#"$op_sel"#clamp;
1357 }
1358
12811359 class getAsmDPP {
12821360 string dst = !if(HasDst,
12831361 !if(!eq(DstVT.Size, 1),
14611539 field dag InsVOP3P = getInsVOP3P
14621540 NumSrcArgs, HasClamp,
14631541 Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
1464
1542 field dag InsVOP3OpSel = getInsVOP3OpSel
1543 NumSrcArgs,
1544 HasClamp,
1545 getOpSelMod.ret,
1546 getOpSelMod.ret,
1547 getOpSelMod.ret>.ret;
14651548 field dag InsDPP = getInsDPP
14661549 HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
14671550 field dag InsSDWA = getInsSDWA
14721555 field string Asm32 = getAsm32.ret;
14731556 field string Asm64 = getAsm64.ret;
14741557 field string AsmVOP3P = getAsmVOP3P.ret;
1558 field string AsmVOP3OpSel = getAsmVOP3OpSel
1559 HasClamp,
1560 HasSrc0FloatMods,
1561 HasSrc1FloatMods,
1562 HasSrc2FloatMods>.ret;
14751563 field string AsmDPP = getAsmDPP.ret;
14761564 field string AsmSDWA = getAsmSDWA.ret;
14771565 field string AsmSDWA9 = getAsmSDWA9.ret;
14931581
14941582 def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
14951583 def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
1584
1585 def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
14961586
14971587 def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
14981588 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
12871287 (med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
12881288 >;
12891289
1290 class FP16Med3Pat
1291 Instruction med3Inst> : Pat<
1292 (fmaxnum (fminnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
1293 (VOP3Mods_nnan vt:$src1, i32:$src1_mods)),
1294 (fminnum_oneuse (fmaxnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
1295 (VOP3Mods_nnan vt:$src1, i32:$src1_mods)),
1296 (vt (VOP3Mods_nnan vt:$src2, i32:$src2_mods)))),
1297 (med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE)
1298 >;
1299
1300 class Int16Med3Pat
1301 SDPatternOperator max,
1302 SDPatternOperator max_oneuse,
1303 SDPatternOperator min_oneuse,
1304 ValueType vt = i32> : Pat<
1305 (max (min_oneuse vt:$src0, vt:$src1),
1306 (min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)),
1307 (med3Inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE)
1308 >;
1309
12901310 def : FPMed3Pat;
12911311
12921312 let Predicates = [isGFX9] in {
1293 def : FPMed3Pat;
1294 def : IntMed3Pat;
1295 def : IntMed3Pat16>;
1313 def : FP16Med3Pat16>;
1314 def : Int16Med3Pat;
1315 def : Int16Med3Pat;
12961316 } // End Predicates = [isGFX9]
12971317
12981318 //============================================================================//
5252 ret1));
5353 }
5454
55 class getVOP3OpSelPat {
56 list ret3 = [(set P.DstVT:$vdst,
57 (node (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
58 (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
59 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
60 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
61
62 list ret2 = [(set P.DstVT:$vdst,
63 (node !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
64 (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
65 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
66
67 list ret1 = [(set P.DstVT:$vdst,
68 (node (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
69
70 list ret = !if(!eq(P.NumSrcArgs, 3), ret3,
71 !if(!eq(P.NumSrcArgs, 2), ret2,
72 ret1));
73 }
74
75 class getVOP3OpSelModPat {
76 list ret3 = [(set P.DstVT:$vdst,
77 (node (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
78 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
79 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
80 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
81
82 list ret2 = [(set P.DstVT:$vdst,
83 (node !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
84 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
85 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
86
87 list ret1 = [(set P.DstVT:$vdst,
88 (node (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
89
90 list ret = !if(!eq(P.NumSrcArgs, 3), ret3,
91 !if(!eq(P.NumSrcArgs, 2), ret2,
92 ret1));
93 }
94
5595 class getVOP3Pat {
5696 list ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
5797 list ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
66106 !if(P.HasModifiers, getVOP3ModPat.ret, getVOP3Pat.ret),
67107 VOP3Only>;
68108
109 class VOP3OpSelInst :
110 VOP3_Pseudo
111 !if(isFloatType.ret,
112 getVOP3OpSelModPat.ret,
113 getVOP3OpSelPat.ret),
114 1, 0, 1> {
115
116 let AsmMatchConverter = "cvtVOP3OpSel";
117 }
118
69119 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
70120 // only VOP instruction that implicitly reads VCC.
71121 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
90140 // FIXME: Hack to stop printing _e64
91141 let Outs64 = (outs DstRC.RegClass:$vdst);
92142 let Asm64 = " " # P.Asm64;
143 }
144
145 class VOP3OpSel_Profile : VOP3_Profile

{

146 let HasClamp = 1;
147 let HasOpSel = 1;
93148 }
94149
95150 class VOP3b_Profile : VOPProfile<[vt, vt, vt, vt]> {
302357 } // End Predicates = [Has16BitInsts]
303358
304359 let SubtargetPredicate = isGFX9 in {
305 def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile>;
360 def V_PACK_B32_F16 : VOP3OpSelInst <"v_pack_b32_f16", VOP3OpSel_Profile>;
306361 def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile>;
307362 def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile>;
308363 def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile>;
312367
313368 def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile>;
314369
315 def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile, AMDGPUfmed3>;
316 def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile, AMDGPUsmed3>;
317 def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile, AMDGPUumed3>;
318
319 def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile, AMDGPUfmin3>;
320 def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile, AMDGPUsmin3>;
321 def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile, AMDGPUumin3>;
322
323 def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile, AMDGPUfmax3>;
324 def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile, AMDGPUsmax3>;
325 def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile, AMDGPUumax3>;
370 def V_MED3_F16 : VOP3OpSelInst <"v_med3_f16", VOP3OpSel_Profile, AMDGPUfmed3>;
371 def V_MED3_I16 : VOP3OpSelInst <"v_med3_i16", VOP3OpSel_Profile, AMDGPUsmed3>;
372 def V_MED3_U16 : VOP3OpSelInst <"v_med3_u16", VOP3OpSel_Profile, AMDGPUumed3>;
373
374 def V_MIN3_F16 : VOP3OpSelInst <"v_min3_f16", VOP3OpSel_Profile, AMDGPUfmin3>;
375 def V_MIN3_I16 : VOP3OpSelInst <"v_min3_i16", VOP3OpSel_Profile, AMDGPUsmin3>;
376 def V_MIN3_U16 : VOP3OpSelInst <"v_min3_u16", VOP3OpSel_Profile, AMDGPUumin3>;
377
378 def V_MAX3_F16 : VOP3OpSelInst <"v_max3_f16", VOP3OpSel_Profile, AMDGPUfmax3>;
379 def V_MAX3_I16 : VOP3OpSelInst <"v_max3_i16", VOP3OpSel_Profile, AMDGPUsmax3>;
380 def V_MAX3_U16 : VOP3OpSelInst <"v_max3_u16", VOP3OpSel_Profile, AMDGPUumax3>;
381
382 def V_ADD_I16 : VOP3OpSelInst <"v_add_i16", VOP3OpSel_Profile>;
383 def V_SUB_I16 : VOP3OpSelInst <"v_sub_i16", VOP3OpSel_Profile>;
384
385 def V_MAD_U32_U16 : VOP3OpSelInst <"v_mad_u32_u16", VOP3OpSel_Profile>;
386 def V_MAD_I32_I16 : VOP3OpSelInst <"v_mad_i32_i16", VOP3OpSel_Profile>;
387
388 def V_CVT_PKNORM_I16_F16 : VOP3OpSelInst <"v_cvt_pknorm_i16_f16", VOP3OpSel_Profile>;
389 def V_CVT_PKNORM_U16_F16 : VOP3OpSelInst <"v_cvt_pknorm_u16_f16", VOP3OpSel_Profile>;
326390 } // End SubtargetPredicate = isGFX9
327391
328392
442506 VOP3be_vi (NAME).Pfl>;
443507 }
444508
509 multiclass VOP3OpSel_Real_gfx9 op> {
510 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
511 VOP3OpSel_gfx9 (NAME).Pfl>;
512 }
513
445514 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
446515
447516 defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
526595 defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
527596 defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
528597 defm V_OR3_B32 : VOP3_Real_vi <0x202>;
529 defm V_PACK_B32_F16 : VOP3_Real_vi <0x2a0>;
598 defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
530599
531600 defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
532601
533 defm V_MIN3_F16 : VOP3_Real_vi <0x1f4>;
534 defm V_MIN3_I16 : VOP3_Real_vi <0x1f5>;
535 defm V_MIN3_U16 : VOP3_Real_vi <0x1f6>;
536
537 defm V_MAX3_F16 : VOP3_Real_vi <0x1f7>;
538 defm V_MAX3_I16 : VOP3_Real_vi <0x1f8>;
539 defm V_MAX3_U16 : VOP3_Real_vi <0x1f9>;
540
541 defm V_MED3_F16 : VOP3_Real_vi <0x1fa>;
542 defm V_MED3_I16 : VOP3_Real_vi <0x1fb>;
543 defm V_MED3_U16 : VOP3_Real_vi <0x1fc>;
602 defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
603 defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
604 defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
605
606 defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
607 defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
608 defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
609
610 defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
611 defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
612 defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
613
614 defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>;
615 defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>;
616
617 defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
618 defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
619
620 defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
621 defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
6464 }
6565
6666 class VOP3_Pseudo pattern = [],
67 bit VOP3Only = 0, bit isVOP3P = 0> :
68 InstSI ,
67 bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> :
68 InstSI
69 !if(isVop3OpSel,
70 P.InsVOP3OpSel,
71 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)),
72 "",
73 pattern>,
6974 VOP ,
7075 SIMCInstr,
7176 MnemonicAlias {
7378 let isPseudo = 1;
7479 let isCodeGenOnly = 1;
7580 let UseNamedOperandTable = 1;
81 let VOP3_OPSEL = isVop3OpSel;
7682
7783 string Mnemonic = opName;
78 string AsmOperands = !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64);
84 string AsmOperands = !if(isVop3OpSel,
85 P.AsmVOP3OpSel,
86 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
7987
8088 let Size = 8;
8189 let mayLoad = 0;
145153 VOP3_Real;
146154
147155 class VOP3a : Enc64 {
148 bits<2> src0_modifiers;
156 bits<4> src0_modifiers;
149157 bits<9> src0;
150 bits<2> src1_modifiers;
158 bits<3> src1_modifiers;
151159 bits<9> src1;
152 bits<2> src2_modifiers;
160 bits<3> src2_modifiers;
153161 bits<9> src2;
154162 bits<1> clamp;
155163 bits<2> omod;
186194 class VOP3e_vi op, VOPProfile P> : VOP3a_vi {
187195 bits<8> vdst;
188196 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
197 }
198
199 class VOP3OpSel_gfx9 op, VOPProfile P> : VOP3e_vi {
200 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
201 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
202 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
203 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
189204 }
190205
191206 class VOP3be : Enc64 {
3828538285 v_xad_u32 v5, v1, v2, -4.0
3828638286 // CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xde,0x03]
3828738287
38288 v_lshl_add_u32 v5, v1, v2, v3
38289 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x04]
38290
38291 v_lshl_add_u32 v255, v1, v2, v3
38292 // CHECK: [0xff,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x04]
38293
38294 v_lshl_add_u32 v5, v255, v2, v3
38295 // CHECK: [0x05,0x00,0xfd,0xd1,0xff,0x05,0x0e,0x04]
38296
38297 v_lshl_add_u32 v5, s1, v2, v3
38298 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x04,0x0e,0x04]
38299
38300 v_lshl_add_u32 v5, s101, v2, v3
38301 // CHECK: [0x05,0x00,0xfd,0xd1,0x65,0x04,0x0e,0x04]
38302
38303 v_lshl_add_u32 v5, flat_scratch_lo, v2, v3
38304 // CHECK: [0x05,0x00,0xfd,0xd1,0x66,0x04,0x0e,0x04]
38305
38306 v_lshl_add_u32 v5, flat_scratch_hi, v2, v3
38307 // CHECK: [0x05,0x00,0xfd,0xd1,0x67,0x04,0x0e,0x04]
38308
38309 v_lshl_add_u32 v5, vcc_lo, v2, v3
38310 // CHECK: [0x05,0x00,0xfd,0xd1,0x6a,0x04,0x0e,0x04]
38311
38312 v_lshl_add_u32 v5, vcc_hi, v2, v3
38313 // CHECK: [0x05,0x00,0xfd,0xd1,0x6b,0x04,0x0e,0x04]
38314
38315 v_lshl_add_u32 v5, m0, v2, v3
38316 // CHECK: [0x05,0x00,0xfd,0xd1,0x7c,0x04,0x0e,0x04]
38317
38318 v_lshl_add_u32 v5, exec_lo, v2, v3
38319 // CHECK: [0x05,0x00,0xfd,0xd1,0x7e,0x04,0x0e,0x04]
38320
38321 v_lshl_add_u32 v5, exec_hi, v2, v3
38322 // CHECK: [0x05,0x00,0xfd,0xd1,0x7f,0x04,0x0e,0x04]
38323
38324 v_lshl_add_u32 v5, 0, v2, v3
38325 // CHECK: [0x05,0x00,0xfd,0xd1,0x80,0x04,0x0e,0x04]
38326
38327 v_lshl_add_u32 v5, -1, v2, v3
38328 // CHECK: [0x05,0x00,0xfd,0xd1,0xc1,0x04,0x0e,0x04]
38329
38330 v_lshl_add_u32 v5, 0.5, v2, v3
38331 // CHECK: [0x05,0x00,0xfd,0xd1,0xf0,0x04,0x0e,0x04]
38332
38333 v_lshl_add_u32 v5, -4.0, v2, v3
38334 // CHECK: [0x05,0x00,0xfd,0xd1,0xf7,0x04,0x0e,0x04]
38335
38336 v_lshl_add_u32 v5, v1, v255, v3
38337 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xff,0x0f,0x04]
38338
38339 v_lshl_add_u32 v5, v1, s2, v3
38340 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0c,0x04]
38341
38342 v_lshl_add_u32 v5, v1, s101, v3
38343 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcb,0x0c,0x04]
38344
38345 v_lshl_add_u32 v5, v1, flat_scratch_lo, v3
38346 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcd,0x0c,0x04]
38347
38348 v_lshl_add_u32 v5, v1, flat_scratch_hi, v3
38349 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcf,0x0c,0x04]
38350
38351 v_lshl_add_u32 v5, v1, vcc_lo, v3
38352 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xd5,0x0c,0x04]
38353
38354 v_lshl_add_u32 v5, v1, vcc_hi, v3
38355 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xd7,0x0c,0x04]
38356
38357 v_lshl_add_u32 v5, v1, m0, v3
38358 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xf9,0x0c,0x04]
38359
38360 v_lshl_add_u32 v5, v1, exec_lo, v3
38361 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xfd,0x0c,0x04]
38362
38363 v_lshl_add_u32 v5, v1, exec_hi, v3
38364 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xff,0x0c,0x04]
38365
38366 v_lshl_add_u32 v5, v1, 0, v3
38367 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x01,0x0d,0x04]
38368
38369 v_lshl_add_u32 v5, v1, -1, v3
38370 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x83,0x0d,0x04]
38371
38372 v_lshl_add_u32 v5, v1, 0.5, v3
38373 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xe1,0x0d,0x04]
38374
38375 v_lshl_add_u32 v5, v1, -4.0, v3
38376 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xef,0x0d,0x04]
38377
38378 v_lshl_add_u32 v5, v1, v2, v255
38379 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfe,0x07]
38380
38381 v_lshl_add_u32 v5, v1, v2, s3
38382 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x00]
38383
38384 v_lshl_add_u32 v5, v1, v2, s101
38385 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x96,0x01]
38386
38387 v_lshl_add_u32 v5, v1, v2, flat_scratch_lo
38388 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x9a,0x01]
38389
38390 v_lshl_add_u32 v5, v1, v2, flat_scratch_hi
38391 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x9e,0x01]
38392
38393 v_lshl_add_u32 v5, v1, v2, vcc_lo
38394 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xaa,0x01]
38395
38396 v_lshl_add_u32 v5, v1, v2, vcc_hi
38397 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xae,0x01]
38398
38399 v_lshl_add_u32 v5, v1, v2, m0
38400 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xf2,0x01]
38401
38402 v_lshl_add_u32 v5, v1, v2, exec_lo
38403 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfa,0x01]
38404
38405 v_lshl_add_u32 v5, v1, v2, exec_hi
38406 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfe,0x01]
38407
38408 v_lshl_add_u32 v5, v1, v2, 0
38409 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x02,0x02]
38410
38411 v_lshl_add_u32 v5, v1, v2, -1
38412 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x06,0x03]
38413
38414 v_lshl_add_u32 v5, v1, v2, 0.5
38415 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xc2,0x03]
38416
38417 v_lshl_add_u32 v5, v1, v2, -4.0
38418 // CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xde,0x03]
38419
38420 v_add_lshl_u32 v5, v1, v2, v3
38421 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x04]
38422
38423 v_add_lshl_u32 v255, v1, v2, v3
38424 // CHECK: [0xff,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x04]
38425
38426 v_add_lshl_u32 v5, v255, v2, v3
38427 // CHECK: [0x05,0x00,0xfe,0xd1,0xff,0x05,0x0e,0x04]
38428
38429 v_add_lshl_u32 v5, s1, v2, v3
38430 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x04,0x0e,0x04]
38431
38432 v_add_lshl_u32 v5, s101, v2, v3
38433 // CHECK: [0x05,0x00,0xfe,0xd1,0x65,0x04,0x0e,0x04]
38434
38435 v_add_lshl_u32 v5, flat_scratch_lo, v2, v3
38436 // CHECK: [0x05,0x00,0xfe,0xd1,0x66,0x04,0x0e,0x04]
38437
38438 v_add_lshl_u32 v5, flat_scratch_hi, v2, v3
38439 // CHECK: [0x05,0x00,0xfe,0xd1,0x67,0x04,0x0e,0x04]
38440
38441 v_add_lshl_u32 v5, vcc_lo, v2, v3
38442 // CHECK: [0x05,0x00,0xfe,0xd1,0x6a,0x04,0x0e,0x04]
38443
38444 v_add_lshl_u32 v5, vcc_hi, v2, v3
38445 // CHECK: [0x05,0x00,0xfe,0xd1,0x6b,0x04,0x0e,0x04]
38446
38447 v_add_lshl_u32 v5, m0, v2, v3
38448 // CHECK: [0x05,0x00,0xfe,0xd1,0x7c,0x04,0x0e,0x04]
38449
38450 v_add_lshl_u32 v5, exec_lo, v2, v3
38451 // CHECK: [0x05,0x00,0xfe,0xd1,0x7e,0x04,0x0e,0x04]
38452
38453 v_add_lshl_u32 v5, exec_hi, v2, v3
38454 // CHECK: [0x05,0x00,0xfe,0xd1,0x7f,0x04,0x0e,0x04]
38455
38456 v_add_lshl_u32 v5, 0, v2, v3
38457 // CHECK: [0x05,0x00,0xfe,0xd1,0x80,0x04,0x0e,0x04]
38458
38459 v_add_lshl_u32 v5, -1, v2, v3
38460 // CHECK: [0x05,0x00,0xfe,0xd1,0xc1,0x04,0x0e,0x04]
38461
38462 v_add_lshl_u32 v5, 0.5, v2, v3
38463 // CHECK: [0x05,0x00,0xfe,0xd1,0xf0,0x04,0x0e,0x04]
38464
38465 v_add_lshl_u32 v5, -4.0, v2, v3
38466 // CHECK: [0x05,0x00,0xfe,0xd1,0xf7,0x04,0x0e,0x04]
38467
38468 v_add_lshl_u32 v5, v1, v255, v3
38469 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xff,0x0f,0x04]
38470
38471 v_add_lshl_u32 v5, v1, s2, v3
38472 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0c,0x04]
38473
38474 v_add_lshl_u32 v5, v1, s101, v3
38475 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcb,0x0c,0x04]
38476
38477 v_add_lshl_u32 v5, v1, flat_scratch_lo, v3
38478 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcd,0x0c,0x04]
38479
38480 v_add_lshl_u32 v5, v1, flat_scratch_hi, v3
38481 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcf,0x0c,0x04]
38482
38483 v_add_lshl_u32 v5, v1, vcc_lo, v3
38484 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xd5,0x0c,0x04]
38485
38486 v_add_lshl_u32 v5, v1, vcc_hi, v3
38487 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xd7,0x0c,0x04]
38488
38489 v_add_lshl_u32 v5, v1, m0, v3
38490 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xf9,0x0c,0x04]
38491
38492 v_add_lshl_u32 v5, v1, exec_lo, v3
38493 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xfd,0x0c,0x04]
38494
38495 v_add_lshl_u32 v5, v1, exec_hi, v3
38496 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xff,0x0c,0x04]
38497
38498 v_add_lshl_u32 v5, v1, 0, v3
38499 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x01,0x0d,0x04]
38500
38501 v_add_lshl_u32 v5, v1, -1, v3
38502 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x83,0x0d,0x04]
38503
38504 v_add_lshl_u32 v5, v1, 0.5, v3
38505 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xe1,0x0d,0x04]
38506
38507 v_add_lshl_u32 v5, v1, -4.0, v3
38508 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xef,0x0d,0x04]
38509
38510 v_add_lshl_u32 v5, v1, v2, v255
38511 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfe,0x07]
38512
38513 v_add_lshl_u32 v5, v1, v2, s3
38514 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x00]
38515
38516 v_add_lshl_u32 v5, v1, v2, s101
38517 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x96,0x01]
38518
38519 v_add_lshl_u32 v5, v1, v2, flat_scratch_lo
38520 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x9a,0x01]
38521
38522 v_add_lshl_u32 v5, v1, v2, flat_scratch_hi
38523 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x9e,0x01]
38524
38525 v_add_lshl_u32 v5, v1, v2, vcc_lo
38526 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xaa,0x01]
38527
38528 v_add_lshl_u32 v5, v1, v2, vcc_hi
38529 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xae,0x01]
38530
38531 v_add_lshl_u32 v5, v1, v2, m0
38532 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xf2,0x01]
38533
38534 v_add_lshl_u32 v5, v1, v2, exec_lo
38535 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfa,0x01]
38536
38537 v_add_lshl_u32 v5, v1, v2, exec_hi
38538 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfe,0x01]
38539
38540 v_add_lshl_u32 v5, v1, v2, 0
38541 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x02,0x02]
38542
38543 v_add_lshl_u32 v5, v1, v2, -1
38544 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x06,0x03]
38545
38546 v_add_lshl_u32 v5, v1, v2, 0.5
38547 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xc2,0x03]
38548
38549 v_add_lshl_u32 v5, v1, v2, -4.0
38550 // CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xde,0x03]
38551
38552 v_add3_u32 v5, v1, v2, v3
38553 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0e,0x04]
38554
38555 v_add3_u32 v255, v1, v2, v3
38556 // CHECK: [0xff,0x00,0xff,0xd1,0x01,0x05,0x0e,0x04]
38557
38558 v_add3_u32 v5, v255, v2, v3
38559 // CHECK: [0x05,0x00,0xff,0xd1,0xff,0x05,0x0e,0x04]
38560
38561 v_add3_u32 v5, s1, v2, v3
38562 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x04,0x0e,0x04]
38563
38564 v_add3_u32 v5, s101, v2, v3
38565 // CHECK: [0x05,0x00,0xff,0xd1,0x65,0x04,0x0e,0x04]
38566
38567 v_add3_u32 v5, flat_scratch_lo, v2, v3
38568 // CHECK: [0x05,0x00,0xff,0xd1,0x66,0x04,0x0e,0x04]
38569
38570 v_add3_u32 v5, flat_scratch_hi, v2, v3
38571 // CHECK: [0x05,0x00,0xff,0xd1,0x67,0x04,0x0e,0x04]
38572
38573 v_add3_u32 v5, vcc_lo, v2, v3
38574 // CHECK: [0x05,0x00,0xff,0xd1,0x6a,0x04,0x0e,0x04]
38575
38576 v_add3_u32 v5, vcc_hi, v2, v3
38577 // CHECK: [0x05,0x00,0xff,0xd1,0x6b,0x04,0x0e,0x04]
38578
38579 v_add3_u32 v5, m0, v2, v3
38580 // CHECK: [0x05,0x00,0xff,0xd1,0x7c,0x04,0x0e,0x04]
38581
38582 v_add3_u32 v5, exec_lo, v2, v3
38583 // CHECK: [0x05,0x00,0xff,0xd1,0x7e,0x04,0x0e,0x04]
38584
38585 v_add3_u32 v5, exec_hi, v2, v3
38586 // CHECK: [0x05,0x00,0xff,0xd1,0x7f,0x04,0x0e,0x04]
38587
38588 v_add3_u32 v5, 0, v2, v3
38589 // CHECK: [0x05,0x00,0xff,0xd1,0x80,0x04,0x0e,0x04]
38590
38591 v_add3_u32 v5, -1, v2, v3
38592 // CHECK: [0x05,0x00,0xff,0xd1,0xc1,0x04,0x0e,0x04]
38593
38594 v_add3_u32 v5, 0.5, v2, v3
38595 // CHECK: [0x05,0x00,0xff,0xd1,0xf0,0x04,0x0e,0x04]
38596
38597 v_add3_u32 v5, -4.0, v2, v3
38598 // CHECK: [0x05,0x00,0xff,0xd1,0xf7,0x04,0x0e,0x04]
38599
38600 v_add3_u32 v5, v1, v255, v3
38601 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xff,0x0f,0x04]
38602
38603 v_add3_u32 v5, v1, s2, v3
38604 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0c,0x04]
38605
38606 v_add3_u32 v5, v1, s101, v3
38607 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcb,0x0c,0x04]
38608
38609 v_add3_u32 v5, v1, flat_scratch_lo, v3
38610 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcd,0x0c,0x04]
38611
38612 v_add3_u32 v5, v1, flat_scratch_hi, v3
38613 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcf,0x0c,0x04]
38614
38615 v_add3_u32 v5, v1, vcc_lo, v3
38616 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xd5,0x0c,0x04]
38617
38618 v_add3_u32 v5, v1, vcc_hi, v3
38619 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xd7,0x0c,0x04]
38620
38621 v_add3_u32 v5, v1, m0, v3
38622 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xf9,0x0c,0x04]
38623
38624 v_add3_u32 v5, v1, exec_lo, v3
38625 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xfd,0x0c,0x04]
38626
38627 v_add3_u32 v5, v1, exec_hi, v3
38628 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xff,0x0c,0x04]
38629
38630 v_add3_u32 v5, v1, 0, v3
38631 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x01,0x0d,0x04]
38632
38633 v_add3_u32 v5, v1, -1, v3
38634 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x83,0x0d,0x04]
38635
38636 v_add3_u32 v5, v1, 0.5, v3
38637 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xe1,0x0d,0x04]
38638
38639 v_add3_u32 v5, v1, -4.0, v3
38640 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0xef,0x0d,0x04]
38641
38642 v_add3_u32 v5, v1, v2, v255
38643 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfe,0x07]
38644
38645 v_add3_u32 v5, v1, v2, s3
38646 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0e,0x00]
38647
38648 v_add3_u32 v5, v1, v2, s101
38649 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x96,0x01]
38650
38651 v_add3_u32 v5, v1, v2, flat_scratch_lo
38652 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x9a,0x01]
38653
38654 v_add3_u32 v5, v1, v2, flat_scratch_hi
38655 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x9e,0x01]
38656
38657 v_add3_u32 v5, v1, v2, vcc_lo
38658 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xaa,0x01]
38659
38660 v_add3_u32 v5, v1, v2, vcc_hi
38661 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xae,0x01]
38662
38663 v_add3_u32 v5, v1, v2, m0
38664 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xf2,0x01]
38665
38666 v_add3_u32 v5, v1, v2, exec_lo
38667 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfa,0x01]
38668
38669 v_add3_u32 v5, v1, v2, exec_hi
38670 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfe,0x01]
38671
38672 v_add3_u32 v5, v1, v2, 0
38673 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x02,0x02]
38674
38675 v_add3_u32 v5, v1, v2, -1
38676 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x06,0x03]
38677
38678 v_add3_u32 v5, v1, v2, 0.5
38679 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xc2,0x03]
38680
38681 v_add3_u32 v5, v1, v2, -4.0
38682 // CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xde,0x03]
38683
38684 v_lshl_or_b32 v5, v1, v2, v3
38685 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0e,0x04]
38686
38687 v_lshl_or_b32 v255, v1, v2, v3
38688 // CHECK: [0xff,0x00,0x00,0xd2,0x01,0x05,0x0e,0x04]
38689
38690 v_lshl_or_b32 v5, v255, v2, v3
38691 // CHECK: [0x05,0x00,0x00,0xd2,0xff,0x05,0x0e,0x04]
38692
38693 v_lshl_or_b32 v5, s1, v2, v3
38694 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x04,0x0e,0x04]
38695
38696 v_lshl_or_b32 v5, s101, v2, v3
38697 // CHECK: [0x05,0x00,0x00,0xd2,0x65,0x04,0x0e,0x04]
38698
38699 v_lshl_or_b32 v5, flat_scratch_lo, v2, v3
38700 // CHECK: [0x05,0x00,0x00,0xd2,0x66,0x04,0x0e,0x04]
38701
38702 v_lshl_or_b32 v5, flat_scratch_hi, v2, v3
38703 // CHECK: [0x05,0x00,0x00,0xd2,0x67,0x04,0x0e,0x04]
38704
38705 v_lshl_or_b32 v5, vcc_lo, v2, v3
38706 // CHECK: [0x05,0x00,0x00,0xd2,0x6a,0x04,0x0e,0x04]
38707
38708 v_lshl_or_b32 v5, vcc_hi, v2, v3
38709 // CHECK: [0x05,0x00,0x00,0xd2,0x6b,0x04,0x0e,0x04]
38710
38711 v_lshl_or_b32 v5, m0, v2, v3
38712 // CHECK: [0x05,0x00,0x00,0xd2,0x7c,0x04,0x0e,0x04]
38713
38714 v_lshl_or_b32 v5, exec_lo, v2, v3
38715 // CHECK: [0x05,0x00,0x00,0xd2,0x7e,0x04,0x0e,0x04]
38716
38717 v_lshl_or_b32 v5, exec_hi, v2, v3
38718 // CHECK: [0x05,0x00,0x00,0xd2,0x7f,0x04,0x0e,0x04]
38719
38720 v_lshl_or_b32 v5, 0, v2, v3
38721 // CHECK: [0x05,0x00,0x00,0xd2,0x80,0x04,0x0e,0x04]
38722
38723 v_lshl_or_b32 v5, -1, v2, v3
38724 // CHECK: [0x05,0x00,0x00,0xd2,0xc1,0x04,0x0e,0x04]
38725
38726 v_lshl_or_b32 v5, 0.5, v2, v3
38727 // CHECK: [0x05,0x00,0x00,0xd2,0xf0,0x04,0x0e,0x04]
38728
38729 v_lshl_or_b32 v5, -4.0, v2, v3
38730 // CHECK: [0x05,0x00,0x00,0xd2,0xf7,0x04,0x0e,0x04]
38731
38732 v_lshl_or_b32 v5, v1, v255, v3
38733 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x0f,0x04]
38734
38735 v_lshl_or_b32 v5, v1, s2, v3
38736 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0c,0x04]
38737
38738 v_lshl_or_b32 v5, v1, s101, v3
38739 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcb,0x0c,0x04]
38740
38741 v_lshl_or_b32 v5, v1, flat_scratch_lo, v3
38742 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcd,0x0c,0x04]
38743
38744 v_lshl_or_b32 v5, v1, flat_scratch_hi, v3
38745 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcf,0x0c,0x04]
38746
38747 v_lshl_or_b32 v5, v1, vcc_lo, v3
38748 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xd5,0x0c,0x04]
38749
38750 v_lshl_or_b32 v5, v1, vcc_hi, v3
38751 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xd7,0x0c,0x04]
38752
38753 v_lshl_or_b32 v5, v1, m0, v3
38754 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xf9,0x0c,0x04]
38755
38756 v_lshl_or_b32 v5, v1, exec_lo, v3
38757 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xfd,0x0c,0x04]
38758
38759 v_lshl_or_b32 v5, v1, exec_hi, v3
38760 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x0c,0x04]
38761
38762 v_lshl_or_b32 v5, v1, 0, v3
38763 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x01,0x0d,0x04]
38764
38765 v_lshl_or_b32 v5, v1, -1, v3
38766 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x83,0x0d,0x04]
38767
38768 v_lshl_or_b32 v5, v1, 0.5, v3
38769 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xe1,0x0d,0x04]
38770
38771 v_lshl_or_b32 v5, v1, -4.0, v3
38772 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0xef,0x0d,0x04]
38773
38774 v_lshl_or_b32 v5, v1, v2, v255
38775 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfe,0x07]
38776
38777 v_lshl_or_b32 v5, v1, v2, s3
38778 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0e,0x00]
38779
38780 v_lshl_or_b32 v5, v1, v2, s101
38781 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x96,0x01]
38782
38783 v_lshl_or_b32 v5, v1, v2, flat_scratch_lo
38784 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9a,0x01]
38785
38786 v_lshl_or_b32 v5, v1, v2, flat_scratch_hi
38787 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9e,0x01]
38788
38789 v_lshl_or_b32 v5, v1, v2, vcc_lo
38790 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xaa,0x01]
38791
38792 v_lshl_or_b32 v5, v1, v2, vcc_hi
38793 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xae,0x01]
38794
38795 v_lshl_or_b32 v5, v1, v2, m0
38796 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xf2,0x01]
38797
38798 v_lshl_or_b32 v5, v1, v2, exec_lo
38799 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfa,0x01]
38800
38801 v_lshl_or_b32 v5, v1, v2, exec_hi
38802 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfe,0x01]
38803
38804 v_lshl_or_b32 v5, v1, v2, 0
38805 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x02,0x02]
38806
38807 v_lshl_or_b32 v5, v1, v2, -1
38808 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x06,0x03]
38809
38810 v_lshl_or_b32 v5, v1, v2, 0.5
38811 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xc2,0x03]
38812
38813 v_lshl_or_b32 v5, v1, v2, -4.0
38814 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xde,0x03]
38815
38816 v_and_or_b32 v5, v1, v2, v3
38817 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0e,0x04]
38818
38819 v_and_or_b32 v255, v1, v2, v3
38820 // CHECK: [0xff,0x00,0x01,0xd2,0x01,0x05,0x0e,0x04]
38821
38822 v_and_or_b32 v5, v255, v2, v3
38823 // CHECK: [0x05,0x00,0x01,0xd2,0xff,0x05,0x0e,0x04]
38824
38825 v_and_or_b32 v5, s1, v2, v3
38826 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x04,0x0e,0x04]
38827
38828 v_and_or_b32 v5, s101, v2, v3
38829 // CHECK: [0x05,0x00,0x01,0xd2,0x65,0x04,0x0e,0x04]
38830
38831 v_and_or_b32 v5, flat_scratch_lo, v2, v3
38832 // CHECK: [0x05,0x00,0x01,0xd2,0x66,0x04,0x0e,0x04]
38833
38834 v_and_or_b32 v5, flat_scratch_hi, v2, v3
38835 // CHECK: [0x05,0x00,0x01,0xd2,0x67,0x04,0x0e,0x04]
38836
38837 v_and_or_b32 v5, vcc_lo, v2, v3
38838 // CHECK: [0x05,0x00,0x01,0xd2,0x6a,0x04,0x0e,0x04]
38839
38840 v_and_or_b32 v5, vcc_hi, v2, v3
38841 // CHECK: [0x05,0x00,0x01,0xd2,0x6b,0x04,0x0e,0x04]
38842
38843 v_and_or_b32 v5, m0, v2, v3
38844 // CHECK: [0x05,0x00,0x01,0xd2,0x7c,0x04,0x0e,0x04]
38845
38846 v_and_or_b32 v5, exec_lo, v2, v3
38847 // CHECK: [0x05,0x00,0x01,0xd2,0x7e,0x04,0x0e,0x04]
38848
38849 v_and_or_b32 v5, exec_hi, v2, v3
38850 // CHECK: [0x05,0x00,0x01,0xd2,0x7f,0x04,0x0e,0x04]
38851
38852 v_and_or_b32 v5, 0, v2, v3
38853 // CHECK: [0x05,0x00,0x01,0xd2,0x80,0x04,0x0e,0x04]
38854
38855 v_and_or_b32 v5, -1, v2, v3
38856 // CHECK: [0x05,0x00,0x01,0xd2,0xc1,0x04,0x0e,0x04]
38857
38858 v_and_or_b32 v5, 0.5, v2, v3
38859 // CHECK: [0x05,0x00,0x01,0xd2,0xf0,0x04,0x0e,0x04]
38860
38861 v_and_or_b32 v5, -4.0, v2, v3
38862 // CHECK: [0x05,0x00,0x01,0xd2,0xf7,0x04,0x0e,0x04]
38863
38864 v_and_or_b32 v5, v1, v255, v3
38865 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xff,0x0f,0x04]
38866
38867 v_and_or_b32 v5, v1, s2, v3
38868 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0c,0x04]
38869
38870 v_and_or_b32 v5, v1, s101, v3
38871 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcb,0x0c,0x04]
38872
38873 v_and_or_b32 v5, v1, flat_scratch_lo, v3
38874 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcd,0x0c,0x04]
38875
38876 v_and_or_b32 v5, v1, flat_scratch_hi, v3
38877 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcf,0x0c,0x04]
38878
38879 v_and_or_b32 v5, v1, vcc_lo, v3
38880 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xd5,0x0c,0x04]
38881
38882 v_and_or_b32 v5, v1, vcc_hi, v3
38883 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xd7,0x0c,0x04]
38884
38885 v_and_or_b32 v5, v1, m0, v3
38886 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xf9,0x0c,0x04]
38887
38888 v_and_or_b32 v5, v1, exec_lo, v3
38889 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xfd,0x0c,0x04]
38890
38891 v_and_or_b32 v5, v1, exec_hi, v3
38892 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xff,0x0c,0x04]
38893
38894 v_and_or_b32 v5, v1, 0, v3
38895 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x01,0x0d,0x04]
38896
38897 v_and_or_b32 v5, v1, -1, v3
38898 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x83,0x0d,0x04]
38899
38900 v_and_or_b32 v5, v1, 0.5, v3
38901 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xe1,0x0d,0x04]
38902
38903 v_and_or_b32 v5, v1, -4.0, v3
38904 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0xef,0x0d,0x04]
38905
38906 v_and_or_b32 v5, v1, v2, v255
38907 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfe,0x07]
38908
38909 v_and_or_b32 v5, v1, v2, s3
38910 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0e,0x00]
38911
38912 v_and_or_b32 v5, v1, v2, s101
38913 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x96,0x01]
38914
38915 v_and_or_b32 v5, v1, v2, flat_scratch_lo
38916 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x9a,0x01]
38917
38918 v_and_or_b32 v5, v1, v2, flat_scratch_hi
38919 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x9e,0x01]
38920
38921 v_and_or_b32 v5, v1, v2, vcc_lo
38922 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xaa,0x01]
38923
38924 v_and_or_b32 v5, v1, v2, vcc_hi
38925 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xae,0x01]
38926
38927 v_and_or_b32 v5, v1, v2, m0
38928 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xf2,0x01]
38929
38930 v_and_or_b32 v5, v1, v2, exec_lo
38931 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfa,0x01]
38932
38933 v_and_or_b32 v5, v1, v2, exec_hi
38934 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfe,0x01]
38935
38936 v_and_or_b32 v5, v1, v2, 0
38937 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x02,0x02]
38938
38939 v_and_or_b32 v5, v1, v2, -1
38940 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x06,0x03]
38941
38942 v_and_or_b32 v5, v1, v2, 0.5
38943 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xc2,0x03]
38944
38945 v_and_or_b32 v5, v1, v2, -4.0
38946 // CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xde,0x03]
38947
38948 v_or3_b32 v5, v1, v2, v3
38949 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0e,0x04]
38950
38951 v_or3_b32 v255, v1, v2, v3
38952 // CHECK: [0xff,0x00,0x02,0xd2,0x01,0x05,0x0e,0x04]
38953
38954 v_or3_b32 v5, v255, v2, v3
38955 // CHECK: [0x05,0x00,0x02,0xd2,0xff,0x05,0x0e,0x04]
38956
38957 v_or3_b32 v5, s1, v2, v3
38958 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x04,0x0e,0x04]
38959
38960 v_or3_b32 v5, s101, v2, v3
38961 // CHECK: [0x05,0x00,0x02,0xd2,0x65,0x04,0x0e,0x04]
38962
38963 v_or3_b32 v5, flat_scratch_lo, v2, v3
38964 // CHECK: [0x05,0x00,0x02,0xd2,0x66,0x04,0x0e,0x04]
38965
38966 v_or3_b32 v5, flat_scratch_hi, v2, v3
38967 // CHECK: [0x05,0x00,0x02,0xd2,0x67,0x04,0x0e,0x04]
38968
38969 v_or3_b32 v5, vcc_lo, v2, v3
38970 // CHECK: [0x05,0x00,0x02,0xd2,0x6a,0x04,0x0e,0x04]
38971
38972 v_or3_b32 v5, vcc_hi, v2, v3
38973 // CHECK: [0x05,0x00,0x02,0xd2,0x6b,0x04,0x0e,0x04]
38974
38975 v_or3_b32 v5, m0, v2, v3
38976 // CHECK: [0x05,0x00,0x02,0xd2,0x7c,0x04,0x0e,0x04]
38977
38978 v_or3_b32 v5, exec_lo, v2, v3
38979 // CHECK: [0x05,0x00,0x02,0xd2,0x7e,0x04,0x0e,0x04]
38980
38981 v_or3_b32 v5, exec_hi, v2, v3
38982 // CHECK: [0x05,0x00,0x02,0xd2,0x7f,0x04,0x0e,0x04]
38983
38984 v_or3_b32 v5, 0, v2, v3
38985 // CHECK: [0x05,0x00,0x02,0xd2,0x80,0x04,0x0e,0x04]
38986
38987 v_or3_b32 v5, -1, v2, v3
38988 // CHECK: [0x05,0x00,0x02,0xd2,0xc1,0x04,0x0e,0x04]
38989
38990 v_or3_b32 v5, 0.5, v2, v3
38991 // CHECK: [0x05,0x00,0x02,0xd2,0xf0,0x04,0x0e,0x04]
38992
38993 v_or3_b32 v5, -4.0, v2, v3
38994 // CHECK: [0x05,0x00,0x02,0xd2,0xf7,0x04,0x0e,0x04]
38995
38996 v_or3_b32 v5, v1, v255, v3
38997 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xff,0x0f,0x04]
38998
38999 v_or3_b32 v5, v1, s2, v3
39000 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0c,0x04]
39001
39002 v_or3_b32 v5, v1, s101, v3
39003 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcb,0x0c,0x04]
39004
39005 v_or3_b32 v5, v1, flat_scratch_lo, v3
39006 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcd,0x0c,0x04]
39007
39008 v_or3_b32 v5, v1, flat_scratch_hi, v3
39009 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcf,0x0c,0x04]
39010
39011 v_or3_b32 v5, v1, vcc_lo, v3
39012 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xd5,0x0c,0x04]
39013
39014 v_or3_b32 v5, v1, vcc_hi, v3
39015 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xd7,0x0c,0x04]
39016
39017 v_or3_b32 v5, v1, m0, v3
39018 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xf9,0x0c,0x04]
39019
39020 v_or3_b32 v5, v1, exec_lo, v3
39021 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xfd,0x0c,0x04]
39022
39023 v_or3_b32 v5, v1, exec_hi, v3
39024 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xff,0x0c,0x04]
39025
39026 v_or3_b32 v5, v1, 0, v3
39027 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x01,0x0d,0x04]
39028
39029 v_or3_b32 v5, v1, -1, v3
39030 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x83,0x0d,0x04]
39031
39032 v_or3_b32 v5, v1, 0.5, v3
39033 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xe1,0x0d,0x04]
39034
39035 v_or3_b32 v5, v1, -4.0, v3
39036 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0xef,0x0d,0x04]
39037
39038 v_or3_b32 v5, v1, v2, v255
39039 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfe,0x07]
39040
39041 v_or3_b32 v5, v1, v2, s3
39042 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0e,0x00]
39043
39044 v_or3_b32 v5, v1, v2, s101
39045 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x96,0x01]
39046
39047 v_or3_b32 v5, v1, v2, flat_scratch_lo
39048 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x9a,0x01]
39049
39050 v_or3_b32 v5, v1, v2, flat_scratch_hi
39051 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x9e,0x01]
39052
39053 v_or3_b32 v5, v1, v2, vcc_lo
39054 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xaa,0x01]
39055
39056 v_or3_b32 v5, v1, v2, vcc_hi
39057 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xae,0x01]
39058
39059 v_or3_b32 v5, v1, v2, m0
39060 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xf2,0x01]
39061
39062 v_or3_b32 v5, v1, v2, exec_lo
39063 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfa,0x01]
39064
39065 v_or3_b32 v5, v1, v2, exec_hi
39066 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfe,0x01]
39067
39068 v_or3_b32 v5, v1, v2, 0
39069 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x02,0x02]
39070
39071 v_or3_b32 v5, v1, v2, -1
39072 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x06,0x03]
39073
39074 v_or3_b32 v5, v1, v2, 0.5
39075 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xc2,0x03]
39076
39077 v_or3_b32 v5, v1, v2, -4.0
39078 // CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xde,0x03]
39079
39080 v_add_f64 v[5:6], v[1:2], v[2:3]
39081 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
39082
39083 v_add_f64 v[254:255], v[1:2], v[2:3]
39084 // CHECK: [0xfe,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
39085
39086 v_add_f64 v[5:6], v[254:255], v[2:3]
39087 // CHECK: [0x05,0x00,0x80,0xd2,0xfe,0x05,0x02,0x00]
39088
39089 v_add_f64 v[5:6], s[2:3], v[2:3]
39090 // CHECK: [0x05,0x00,0x80,0xd2,0x02,0x04,0x02,0x00]
39091
39092 v_add_f64 v[5:6], s[4:5], v[2:3]
39093 // CHECK: [0x05,0x00,0x80,0xd2,0x04,0x04,0x02,0x00]
39094
39095 v_add_f64 v[5:6], s[100:101], v[2:3]
39096 // CHECK: [0x05,0x00,0x80,0xd2,0x64,0x04,0x02,0x00]
39097
39098 v_add_f64 v[5:6], flat_scratch, v[2:3]
39099 // CHECK: [0x05,0x00,0x80,0xd2,0x66,0x04,0x02,0x00]
39100
39101 v_add_f64 v[5:6], vcc, v[2:3]
39102 // CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x02,0x00]
39103
39104 v_add_f64 v[5:6], exec, v[2:3]
39105 // CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x02,0x00]
39106
39107 v_add_f64 v[5:6], 0, v[2:3]
39108 // CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x02,0x00]
39109
39110 v_add_f64 v[5:6], -1, v[2:3]
39111 // CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x02,0x00]
39112
39113 v_add_f64 v[5:6], 0.5, v[2:3]
39114 // CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x02,0x00]
39115
39116 v_add_f64 v[5:6], -4.0, v[2:3]
39117 // CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x02,0x00]
39118
39119 v_add_f64 v[5:6], v[1:2], v[254:255]
39120 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x03,0x00]
39121
39122 v_add_f64 v[5:6], v[1:2], s[4:5]
39123 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x09,0x00,0x00]
39124
39125 v_add_f64 v[5:6], v[1:2], s[6:7]
39126 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x0d,0x00,0x00]
39127
39128 v_add_f64 v[5:6], v[1:2], s[100:101]
39129 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xc9,0x00,0x00]
39130
39131 v_add_f64 v[5:6], v[1:2], flat_scratch
39132 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcd,0x00,0x00]
39133
39134 v_add_f64 v[5:6], v[1:2], vcc
39135 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x00,0x00]
39136
39137 v_add_f64 v[5:6], v[1:2], exec
39138 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x00,0x00]
39139
39140 v_add_f64 v[5:6], v[1:2], 0
39141 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x01,0x00]
39142
39143 v_add_f64 v[5:6], v[1:2], -1
39144 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x01,0x00]
39145
39146 v_add_f64 v[5:6], v[1:2], 0.5
39147 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x01,0x00]
39148
39149 v_add_f64 v[5:6], v[1:2], -4.0
39150 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x01,0x00]
39151
39152 v_add_f64 v[5:6], -v[1:2], v[2:3]
39153 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x20]
39154
39155 v_add_f64 v[5:6], v[1:2], -v[2:3]
39156 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x40]
39157
39158 v_add_f64 v[5:6], -v[1:2], -v[2:3]
39159 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x60]
39160
39161 v_add_f64 v[5:6], |v[1:2]|, v[2:3]
39162 // CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x02,0x00]
39163
39164 v_add_f64 v[5:6], v[1:2], |v[2:3]|
39165 // CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x02,0x00]
39166
39167 v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
39168 // CHECK: [0x05,0x03,0x80,0xd2,0x01,0x05,0x02,0x00]
39169
39170 v_add_f64 v[5:6], v[1:2], v[2:3] clamp
39171 // CHECK: [0x05,0x80,0x80,0xd2,0x01,0x05,0x02,0x00]
39172
39173 v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
39174 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x08]
39175
39176 v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
39177 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x10]
39178
39179 v_add_f64 v[5:6], v[1:2], v[2:3] div:2
39180 // CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x18]
39181
39182 v_mul_f64 v[5:6], v[1:2], v[2:3]
39183 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
39184
39185 v_mul_f64 v[254:255], v[1:2], v[2:3]
39186 // CHECK: [0xfe,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
39187
39188 v_mul_f64 v[5:6], v[254:255], v[2:3]
39189 // CHECK: [0x05,0x00,0x81,0xd2,0xfe,0x05,0x02,0x00]
39190
39191 v_mul_f64 v[5:6], s[2:3], v[2:3]
39192 // CHECK: [0x05,0x00,0x81,0xd2,0x02,0x04,0x02,0x00]
39193
39194 v_mul_f64 v[5:6], s[4:5], v[2:3]
39195 // CHECK: [0x05,0x00,0x81,0xd2,0x04,0x04,0x02,0x00]
39196
39197 v_mul_f64 v[5:6], s[100:101], v[2:3]
39198 // CHECK: [0x05,0x00,0x81,0xd2,0x64,0x04,0x02,0x00]
39199
39200 v_mul_f64 v[5:6], flat_scratch, v[2:3]
39201 // CHECK: [0x05,0x00,0x81,0xd2,0x66,0x04,0x02,0x00]
39202
39203 v_mul_f64 v[5:6], vcc, v[2:3]
39204 // CHECK: [0x05,0x00,0x81,0xd2,0x6a,0x04,0x02,0x00]
39205
39206 v_mul_f64 v[5:6], exec, v[2:3]
39207 // CHECK: [0x05,0x00,0x81,0xd2,0x7e,0x04,0x02,0x00]
39208
39209 v_mul_f64 v[5:6], 0, v[2:3]
39210 // CHECK: [0x05,0x00,0x81,0xd2,0x80,0x04,0x02,0x00]
39211
39212 v_mul_f64 v[5:6], -1, v[2:3]
39213 // CHECK: [0x05,0x00,0x81,0xd2,0xc1,0x04,0x02,0x00]
39214
39215 v_mul_f64 v[5:6], 0.5, v[2:3]
39216 // CHECK: [0x05,0x00,0x81,0xd2,0xf0,0x04,0x02,0x00]
39217
39218 v_mul_f64 v[5:6], -4.0, v[2:3]
39219 // CHECK: [0x05,0x00,0x81,0xd2,0xf7,0x04,0x02,0x00]
39220
39221 v_mul_f64 v[5:6], v[1:2], v[254:255]
39222 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x03,0x00]
39223
39224 v_mul_f64 v[5:6], v[1:2], s[4:5]
39225 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x09,0x00,0x00]
39226
39227 v_mul_f64 v[5:6], v[1:2], s[6:7]
39228 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x0d,0x00,0x00]
39229
39230 v_mul_f64 v[5:6], v[1:2], s[100:101]
39231 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xc9,0x00,0x00]
39232
39233 v_mul_f64 v[5:6], v[1:2], flat_scratch
39234 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xcd,0x00,0x00]
39235
39236 v_mul_f64 v[5:6], v[1:2], vcc
39237 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd5,0x00,0x00]
39238
39239 v_mul_f64 v[5:6], v[1:2], exec
39240 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x00,0x00]
39241
39242 v_mul_f64 v[5:6], v[1:2], 0
39243 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x01,0x01,0x00]
39244
39245 v_mul_f64 v[5:6], v[1:2], -1
39246 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x83,0x01,0x00]
39247
39248 v_mul_f64 v[5:6], v[1:2], 0.5
39249 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xe1,0x01,0x00]
39250
39251 v_mul_f64 v[5:6], v[1:2], -4.0
39252 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0xef,0x01,0x00]
39253
39254 v_mul_f64 v[5:6], -v[1:2], v[2:3]
39255 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x20]
39256
39257 v_mul_f64 v[5:6], v[1:2], -v[2:3]
39258 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x40]
39259
39260 v_mul_f64 v[5:6], -v[1:2], -v[2:3]
39261 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x60]
39262
39263 v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
39264 // CHECK: [0x05,0x01,0x81,0xd2,0x01,0x05,0x02,0x00]
39265
39266 v_mul_f64 v[5:6], v[1:2], |v[2:3]|
39267 // CHECK: [0x05,0x02,0x81,0xd2,0x01,0x05,0x02,0x00]
39268
39269 v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
39270 // CHECK: [0x05,0x03,0x81,0xd2,0x01,0x05,0x02,0x00]
39271
39272 v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
39273 // CHECK: [0x05,0x80,0x81,0xd2,0x01,0x05,0x02,0x00]
39274
39275 v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
39276 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x08]
39277
39278 v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
39279 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x10]
39280
39281 v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
39282 // CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x18]
39283
39284 v_min_f64 v[5:6], v[1:2], v[2:3]
39285 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
39286
39287 v_min_f64 v[254:255], v[1:2], v[2:3]
39288 // CHECK: [0xfe,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
39289
39290 v_min_f64 v[5:6], v[254:255], v[2:3]
39291 // CHECK: [0x05,0x00,0x82,0xd2,0xfe,0x05,0x02,0x00]
39292
39293 v_min_f64 v[5:6], s[2:3], v[2:3]
39294 // CHECK: [0x05,0x00,0x82,0xd2,0x02,0x04,0x02,0x00]
39295
39296 v_min_f64 v[5:6], s[4:5], v[2:3]
39297 // CHECK: [0x05,0x00,0x82,0xd2,0x04,0x04,0x02,0x00]
39298
39299 v_min_f64 v[5:6], s[100:101], v[2:3]
39300 // CHECK: [0x05,0x00,0x82,0xd2,0x64,0x04,0x02,0x00]
39301
39302 v_min_f64 v[5:6], flat_scratch, v[2:3]
39303 // CHECK: [0x05,0x00,0x82,0xd2,0x66,0x04,0x02,0x00]
39304
39305 v_min_f64 v[5:6], vcc, v[2:3]
39306 // CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x02,0x00]
39307
39308 v_min_f64 v[5:6], exec, v[2:3]
39309 // CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x02,0x00]
39310
39311 v_min_f64 v[5:6], 0, v[2:3]
39312 // CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x02,0x00]
39313
39314 v_min_f64 v[5:6], -1, v[2:3]
39315 // CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x02,0x00]
39316
39317 v_min_f64 v[5:6], 0.5, v[2:3]
39318 // CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x02,0x00]
39319
39320 v_min_f64 v[5:6], -4.0, v[2:3]
39321 // CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x02,0x00]
39322
39323 v_min_f64 v[5:6], v[1:2], v[254:255]
39324 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x03,0x00]
39325
39326 v_min_f64 v[5:6], v[1:2], s[4:5]
39327 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x09,0x00,0x00]
39328
39329 v_min_f64 v[5:6], v[1:2], s[6:7]
39330 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x0d,0x00,0x00]
39331
39332 v_min_f64 v[5:6], v[1:2], s[100:101]
39333 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xc9,0x00,0x00]
39334
39335 v_min_f64 v[5:6], v[1:2], flat_scratch
39336 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcd,0x00,0x00]
39337
39338 v_min_f64 v[5:6], v[1:2], vcc
39339 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x00,0x00]
39340
39341 v_min_f64 v[5:6], v[1:2], exec
39342 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x00,0x00]
39343
39344 v_min_f64 v[5:6], v[1:2], 0
39345 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x01,0x00]
39346
39347 v_min_f64 v[5:6], v[1:2], -1
39348 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x01,0x00]
39349
39350 v_min_f64 v[5:6], v[1:2], 0.5
39351 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x01,0x00]
39352
39353 v_min_f64 v[5:6], v[1:2], -4.0
39354 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x01,0x00]
39355
39356 v_min_f64 v[5:6], -v[1:2], v[2:3]
39357 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x20]
39358
39359 v_min_f64 v[5:6], v[1:2], -v[2:3]
39360 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x40]
39361
39362 v_min_f64 v[5:6], -v[1:2], -v[2:3]
39363 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x60]
39364
39365 v_min_f64 v[5:6], |v[1:2]|, v[2:3]
39366 // CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x02,0x00]
39367
39368 v_min_f64 v[5:6], v[1:2], |v[2:3]|
39369 // CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x02,0x00]
39370
39371 v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
39372 // CHECK: [0x05,0x03,0x82,0xd2,0x01,0x05,0x02,0x00]
39373
39374 v_min_f64 v[5:6], v[1:2], v[2:3] clamp
39375 // CHECK: [0x05,0x80,0x82,0xd2,0x01,0x05,0x02,0x00]
39376
39377 v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
39378 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x08]
39379
39380 v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
39381 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x10]
39382
39383 v_min_f64 v[5:6], v[1:2], v[2:3] div:2
39384 // CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x18]
39385
39386 v_max_f64 v[5:6], v[1:2], v[2:3]
39387 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
39388
39389 v_max_f64 v[254:255], v[1:2], v[2:3]
39390 // CHECK: [0xfe,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
39391
39392 v_max_f64 v[5:6], v[254:255], v[2:3]
39393 // CHECK: [0x05,0x00,0x83,0xd2,0xfe,0x05,0x02,0x00]
39394
39395 v_max_f64 v[5:6], s[2:3], v[2:3]
39396 // CHECK: [0x05,0x00,0x83,0xd2,0x02,0x04,0x02,0x00]
39397
39398 v_max_f64 v[5:6], s[4:5], v[2:3]
39399 // CHECK: [0x05,0x00,0x83,0xd2,0x04,0x04,0x02,0x00]
39400
39401 v_max_f64 v[5:6], s[100:101], v[2:3]
39402 // CHECK: [0x05,0x00,0x83,0xd2,0x64,0x04,0x02,0x00]
39403
39404 v_max_f64 v[5:6], flat_scratch, v[2:3]
39405 // CHECK: [0x05,0x00,0x83,0xd2,0x66,0x04,0x02,0x00]
39406
39407 v_max_f64 v[5:6], vcc, v[2:3]
39408 // CHECK: [0x05,0x00,0x83,0xd2,0x6a,0x04,0x02,0x00]
39409
39410 v_max_f64 v[5:6], exec, v[2:3]
39411 // CHECK: [0x05,0x00,0x83,0xd2,0x7e,0x04,0x02,0x00]
39412
39413 v_max_f64 v[5:6], 0, v[2:3]
39414 // CHECK: [0x05,0x00,0x83,0xd2,0x80,0x04,0x02,0x00]
39415
39416 v_max_f64 v[5:6], -1, v[2:3]
39417 // CHECK: [0x05,0x00,0x83,0xd2,0xc1,0x04,0x02,0x00]
39418
39419 v_max_f64 v[5:6], 0.5, v[2:3]
39420 // CHECK: [0x05,0x00,0x83,0xd2,0xf0,0x04,0x02,0x00]
39421
39422 v_max_f64 v[5:6], -4.0, v[2:3]
39423 // CHECK: [0x05,0x00,0x83,0xd2,0xf7,0x04,0x02,0x00]
39424
39425 v_max_f64 v[5:6], v[1:2], v[254:255]
39426 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x03,0x00]
39427
39428 v_max_f64 v[5:6], v[1:2], s[4:5]
39429 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x09,0x00,0x00]
39430
39431 v_max_f64 v[5:6], v[1:2], s[6:7]
39432 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x0d,0x00,0x00]
39433
39434 v_max_f64 v[5:6], v[1:2], s[100:101]
39435 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xc9,0x00,0x00]
39436
39437 v_max_f64 v[5:6], v[1:2], flat_scratch
39438 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xcd,0x00,0x00]
39439
39440 v_max_f64 v[5:6], v[1:2], vcc
39441 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd5,0x00,0x00]
39442
39443 v_max_f64 v[5:6], v[1:2], exec
39444 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x00,0x00]
39445
39446 v_max_f64 v[5:6], v[1:2], 0
39447 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x01,0x01,0x00]
39448
39449 v_max_f64 v[5:6], v[1:2], -1
39450 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x83,0x01,0x00]
39451
39452 v_max_f64 v[5:6], v[1:2], 0.5
39453 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xe1,0x01,0x00]
39454
39455 v_max_f64 v[5:6], v[1:2], -4.0
39456 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0xef,0x01,0x00]
39457
39458 v_max_f64 v[5:6], -v[1:2], v[2:3]
39459 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x20]
39460
39461 v_max_f64 v[5:6], v[1:2], -v[2:3]
39462 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x40]
39463
39464 v_max_f64 v[5:6], -v[1:2], -v[2:3]
39465 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x60]
39466
39467 v_max_f64 v[5:6], |v[1:2]|, v[2:3]
39468 // CHECK: [0x05,0x01,0x83,0xd2,0x01,0x05,0x02,0x00]
39469
39470 v_max_f64 v[5:6], v[1:2], |v[2:3]|
39471 // CHECK: [0x05,0x02,0x83,0xd2,0x01,0x05,0x02,0x00]
39472
39473 v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
39474 // CHECK: [0x05,0x03,0x83,0xd2,0x01,0x05,0x02,0x00]
39475
39476 v_max_f64 v[5:6], v[1:2], v[2:3] clamp
39477 // CHECK: [0x05,0x80,0x83,0xd2,0x01,0x05,0x02,0x00]
39478
39479 v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
39480 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x08]
39481
39482 v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
39483 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x10]
39484
39485 v_max_f64 v[5:6], v[1:2], v[2:3] div:2
39486 // CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x18]
39487
39488 v_ldexp_f64 v[5:6], v[1:2], v2
39489 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
39490
39491 v_ldexp_f64 v[254:255], v[1:2], v2
39492 // CHECK: [0xfe,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
39493
39494 v_ldexp_f64 v[5:6], v[254:255], v2
39495 // CHECK: [0x05,0x00,0x84,0xd2,0xfe,0x05,0x02,0x00]
39496
39497 v_ldexp_f64 v[5:6], s[2:3], v2
39498 // CHECK: [0x05,0x00,0x84,0xd2,0x02,0x04,0x02,0x00]
39499
39500 v_ldexp_f64 v[5:6], s[4:5], v2
39501 // CHECK: [0x05,0x00,0x84,0xd2,0x04,0x04,0x02,0x00]
39502
39503 v_ldexp_f64 v[5:6], s[100:101], v2
39504 // CHECK: [0x05,0x00,0x84,0xd2,0x64,0x04,0x02,0x00]
39505
39506 v_ldexp_f64 v[5:6], flat_scratch, v2
39507 // CHECK: [0x05,0x00,0x84,0xd2,0x66,0x04,0x02,0x00]
39508
39509 v_ldexp_f64 v[5:6], vcc, v2
39510 // CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x02,0x00]
39511
39512 v_ldexp_f64 v[5:6], exec, v2
39513 // CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x02,0x00]
39514
39515 v_ldexp_f64 v[5:6], 0, v2
39516 // CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x02,0x00]
39517
39518 v_ldexp_f64 v[5:6], -1, v2
39519 // CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x02,0x00]
39520
39521 v_ldexp_f64 v[5:6], 0.5, v2
39522 // CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x02,0x00]
39523
39524 v_ldexp_f64 v[5:6], -4.0, v2
39525 // CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x02,0x00]
39526
39527 v_ldexp_f64 v[5:6], v[1:2], v255
39528 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x03,0x00]
39529
39530 v_ldexp_f64 v[5:6], v[1:2], s2
39531 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x00,0x00]
39532
39533 v_ldexp_f64 v[5:6], v[1:2], s101
39534 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcb,0x00,0x00]
39535
39536 v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
39537 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcd,0x00,0x00]
39538
39539 v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
39540 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x00,0x00]
39541
39542 v_ldexp_f64 v[5:6], v[1:2], vcc_lo
39543 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x00,0x00]
39544
39545 v_ldexp_f64 v[5:6], v[1:2], vcc_hi
39546 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x00,0x00]
39547
39548 v_ldexp_f64 v[5:6], v[1:2], m0
39549 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x00,0x00]
39550
39551 v_ldexp_f64 v[5:6], v[1:2], exec_lo
39552 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x00,0x00]
39553
39554 v_ldexp_f64 v[5:6], v[1:2], exec_hi
39555 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x00,0x00]
39556
39557 v_ldexp_f64 v[5:6], v[1:2], 0
39558 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x01,0x00]
39559
39560 v_ldexp_f64 v[5:6], v[1:2], -1
39561 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x01,0x00]
39562
39563 v_ldexp_f64 v[5:6], v[1:2], 0.5
39564 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x01,0x00]
39565
39566 v_ldexp_f64 v[5:6], v[1:2], -4.0
39567 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x01,0x00]
39568
39569 v_ldexp_f64 v[5:6], -v[1:2], v2
39570 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x20]
39571
39572 v_ldexp_f64 v[5:6], |v[1:2]|, v2
39573 // CHECK: [0x05,0x01,0x84,0xd2,0x01,0x05,0x02,0x00]
39574
39575 v_ldexp_f64 v[5:6], v[1:2], v2 clamp
39576 // CHECK: [0x05,0x80,0x84,0xd2,0x01,0x05,0x02,0x00]
39577
39578 v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
39579 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x08]
39580
39581 v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
39582 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x10]
39583
39584 v_ldexp_f64 v[5:6], v[1:2], v2 div:2
39585 // CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x18]
39586
39587 v_mul_lo_u32 v5, v1, v2
39588 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
39589
39590 v_mul_lo_u32 v255, v1, v2
39591 // CHECK: [0xff,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
39592
39593 v_mul_lo_u32 v5, v255, v2
39594 // CHECK: [0x05,0x00,0x85,0xd2,0xff,0x05,0x02,0x00]
39595
39596 v_mul_lo_u32 v5, s1, v2
39597 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0x04,0x02,0x00]
39598
39599 v_mul_lo_u32 v5, s101, v2
39600 // CHECK: [0x05,0x00,0x85,0xd2,0x65,0x04,0x02,0x00]
39601
39602 v_mul_lo_u32 v5, flat_scratch_lo, v2
39603 // CHECK: [0x05,0x00,0x85,0xd2,0x66,0x04,0x02,0x00]
39604
39605 v_mul_lo_u32 v5, flat_scratch_hi, v2
39606 // CHECK: [0x05,0x00,0x85,0xd2,0x67,0x04,0x02,0x00]
39607
39608 v_mul_lo_u32 v5, vcc_lo, v2
39609 // CHECK: [0x05,0x00,0x85,0xd2,0x6a,0x04,0x02,0x00]
39610
39611 v_mul_lo_u32 v5, vcc_hi, v2
39612 // CHECK: [0x05,0x00,0x85,0xd2,0x6b,0x04,0x02,0x00]
39613
39614 v_mul_lo_u32 v5, m0, v2
39615 // CHECK: [0x05,0x00,0x85,0xd2,0x7c,0x04,0x02,0x00]
39616
39617 v_mul_lo_u32 v5, exec_lo, v2
39618 // CHECK: [0x05,0x00,0x85,0xd2,0x7e,0x04,0x02,0x00]
39619
39620 v_mul_lo_u32 v5, exec_hi, v2
39621 // CHECK: [0x05,0x00,0x85,0xd2,0x7f,0x04,0x02,0x00]
39622
39623 v_mul_lo_u32 v5, 0, v2
39624 // CHECK: [0x05,0x00,0x85,0xd2,0x80,0x04,0x02,0x00]
39625
39626 v_mul_lo_u32 v5, -1, v2
39627 // CHECK: [0x05,0x00,0x85,0xd2,0xc1,0x04,0x02,0x00]
39628
39629 v_mul_lo_u32 v5, 0.5, v2
39630 // CHECK: [0x05,0x00,0x85,0xd2,0xf0,0x04,0x02,0x00]
39631
39632 v_mul_lo_u32 v5, -4.0, v2
39633 // CHECK: [0x05,0x00,0x85,0xd2,0xf7,0x04,0x02,0x00]
39634
39635 v_mul_lo_u32 v5, v1, v255
39636 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x03,0x00]
39637
39638 v_mul_lo_u32 v5, v1, s2
39639 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x00,0x00]
39640
39641 v_mul_lo_u32 v5, v1, s101
39642 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcb,0x00,0x00]
39643
39644 v_mul_lo_u32 v5, v1, flat_scratch_lo
39645 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcd,0x00,0x00]
39646
39647 v_mul_lo_u32 v5, v1, flat_scratch_hi
39648 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcf,0x00,0x00]
39649
39650 v_mul_lo_u32 v5, v1, vcc_lo
39651 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd5,0x00,0x00]
39652
39653 v_mul_lo_u32 v5, v1, vcc_hi
39654 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd7,0x00,0x00]
39655
39656 v_mul_lo_u32 v5, v1, m0
39657 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x00,0x00]
39658
39659 v_mul_lo_u32 v5, v1, exec_lo
39660 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfd,0x00,0x00]
39661
39662 v_mul_lo_u32 v5, v1, exec_hi
39663 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x00,0x00]
39664
39665 v_mul_lo_u32 v5, v1, 0
39666 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0x01,0x01,0x00]
39667
39668 v_mul_lo_u32 v5, v1, -1
39669 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0x83,0x01,0x00]
39670
39671 v_mul_lo_u32 v5, v1, 0.5
39672 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xe1,0x01,0x00]
39673
39674 v_mul_lo_u32 v5, v1, -4.0
39675 // CHECK: [0x05,0x00,0x85,0xd2,0x01,0xef,0x01,0x00]
39676
39677 v_mul_hi_u32 v5, v1, v2
39678 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
39679
39680 v_mul_hi_u32 v255, v1, v2
39681 // CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
39682
39683 v_mul_hi_u32 v5, v255, v2
39684 // CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x02,0x00]
39685
39686 v_mul_hi_u32 v5, s1, v2
39687 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x02,0x00]
39688
39689 v_mul_hi_u32 v5, s101, v2
39690 // CHECK: [0x05,0x00,0x86,0xd2,0x65,0x04,0x02,0x00]
39691
39692 v_mul_hi_u32 v5, flat_scratch_lo, v2
39693 // CHECK: [0x05,0x00,0x86,0xd2,0x66,0x04,0x02,0x00]
39694
39695 v_mul_hi_u32 v5, flat_scratch_hi, v2
39696 // CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x02,0x00]
39697
39698 v_mul_hi_u32 v5, vcc_lo, v2
39699 // CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x02,0x00]
39700
39701 v_mul_hi_u32 v5, vcc_hi, v2
39702 // CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x02,0x00]
39703
39704 v_mul_hi_u32 v5, m0, v2
39705 // CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x02,0x00]
39706
39707 v_mul_hi_u32 v5, exec_lo, v2
39708 // CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x02,0x00]
39709
39710 v_mul_hi_u32 v5, exec_hi, v2
39711 // CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x02,0x00]
39712
39713 v_mul_hi_u32 v5, 0, v2
39714 // CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x02,0x00]
39715
39716 v_mul_hi_u32 v5, -1, v2
39717 // CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x02,0x00]
39718
39719 v_mul_hi_u32 v5, 0.5, v2
39720 // CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x02,0x00]
39721
39722 v_mul_hi_u32 v5, -4.0, v2
39723 // CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x02,0x00]
39724
39725 v_mul_hi_u32 v5, v1, v255
39726 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x03,0x00]
39727
39728 v_mul_hi_u32 v5, v1, s2
39729 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x00,0x00]
39730
39731 v_mul_hi_u32 v5, v1, s101
39732 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcb,0x00,0x00]
39733
39734 v_mul_hi_u32 v5, v1, flat_scratch_lo
39735 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcd,0x00,0x00]
39736
39737 v_mul_hi_u32 v5, v1, flat_scratch_hi
39738 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x00,0x00]
39739
39740 v_mul_hi_u32 v5, v1, vcc_lo
39741 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x00,0x00]
39742
39743 v_mul_hi_u32 v5, v1, vcc_hi
39744 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x00,0x00]
39745
39746 v_mul_hi_u32 v5, v1, m0
39747 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x00,0x00]
39748
39749 v_mul_hi_u32 v5, v1, exec_lo
39750 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x00,0x00]
39751
39752 v_mul_hi_u32 v5, v1, exec_hi
39753 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x00,0x00]
39754
39755 v_mul_hi_u32 v5, v1, 0
39756 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x01,0x00]
39757
39758 v_mul_hi_u32 v5, v1, -1
39759 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x01,0x00]
39760
39761 v_mul_hi_u32 v5, v1, 0.5
39762 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x01,0x00]
39763
39764 v_mul_hi_u32 v5, v1, -4.0
39765 // CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x01,0x00]
39766
39767 v_mul_hi_i32 v5, v1, v2
39768 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
39769
39770 v_mul_hi_i32 v255, v1, v2
39771 // CHECK: [0xff,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
39772
39773 v_mul_hi_i32 v5, v255, v2
39774 // CHECK: [0x05,0x00,0x87,0xd2,0xff,0x05,0x02,0x00]
39775
39776 v_mul_hi_i32 v5, s1, v2
39777 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0x04,0x02,0x00]
39778
39779 v_mul_hi_i32 v5, s101, v2
39780 // CHECK: [0x05,0x00,0x87,0xd2,0x65,0x04,0x02,0x00]
39781
39782 v_mul_hi_i32 v5, flat_scratch_lo, v2
39783 // CHECK: [0x05,0x00,0x87,0xd2,0x66,0x04,0x02,0x00]
39784
39785 v_mul_hi_i32 v5, flat_scratch_hi, v2
39786 // CHECK: [0x05,0x00,0x87,0xd2,0x67,0x04,0x02,0x00]
39787
39788 v_mul_hi_i32 v5, vcc_lo, v2
39789 // CHECK: [0x05,0x00,0x87,0xd2,0x6a,0x04,0x02,0x00]
39790
39791 v_mul_hi_i32 v5, vcc_hi, v2
39792 // CHECK: [0x05,0x00,0x87,0xd2,0x6b,0x04,0x02,0x00]
39793
39794 v_mul_hi_i32 v5, m0, v2
39795 // CHECK: [0x05,0x00,0x87,0xd2,0x7c,0x04,0x02,0x00]
39796
39797 v_mul_hi_i32 v5, exec_lo, v2
39798 // CHECK: [0x05,0x00,0x87,0xd2,0x7e,0x04,0x02,0x00]
39799
39800 v_mul_hi_i32 v5, exec_hi, v2
39801 // CHECK: [0x05,0x00,0x87,0xd2,0x7f,0x04,0x02,0x00]
39802
39803 v_mul_hi_i32 v5, 0, v2
39804 // CHECK: [0x05,0x00,0x87,0xd2,0x80,0x04,0x02,0x00]
39805
39806 v_mul_hi_i32 v5, -1, v2
39807 // CHECK: [0x05,0x00,0x87,0xd2,0xc1,0x04,0x02,0x00]
39808
39809 v_mul_hi_i32 v5, 0.5, v2
39810 // CHECK: [0x05,0x00,0x87,0xd2,0xf0,0x04,0x02,0x00]
39811
39812 v_mul_hi_i32 v5, -4.0, v2
39813 // CHECK: [0x05,0x00,0x87,0xd2,0xf7,0x04,0x02,0x00]
39814
39815 v_mul_hi_i32 v5, v1, v255
39816 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x03,0x00]
39817
39818 v_mul_hi_i32 v5, v1, s2
39819 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x00,0x00]
39820
39821 v_mul_hi_i32 v5, v1, s101
39822 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcb,0x00,0x00]
39823
39824 v_mul_hi_i32 v5, v1, flat_scratch_lo
39825 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcd,0x00,0x00]
39826
39827 v_mul_hi_i32 v5, v1, flat_scratch_hi
39828 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcf,0x00,0x00]
39829
39830 v_mul_hi_i32 v5, v1, vcc_lo
39831 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd5,0x00,0x00]
39832
39833 v_mul_hi_i32 v5, v1, vcc_hi
39834 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd7,0x00,0x00]
39835
39836 v_mul_hi_i32 v5, v1, m0
39837 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x00,0x00]
39838
39839 v_mul_hi_i32 v5, v1, exec_lo
39840 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfd,0x00,0x00]
39841
39842 v_mul_hi_i32 v5, v1, exec_hi
39843 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x00,0x00]
39844
39845 v_mul_hi_i32 v5, v1, 0
39846 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0x01,0x01,0x00]
39847
39848 v_mul_hi_i32 v5, v1, -1
39849 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0x83,0x01,0x00]
39850
39851 v_mul_hi_i32 v5, v1, 0.5
39852 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xe1,0x01,0x00]
39853
39854 v_mul_hi_i32 v5, v1, -4.0
39855 // CHECK: [0x05,0x00,0x87,0xd2,0x01,0xef,0x01,0x00]
39856
39857 v_ldexp_f32 v5, v1, v2
39858 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
39859
39860 v_ldexp_f32 v255, v1, v2
39861 // CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
39862
39863 v_ldexp_f32 v5, v255, v2
39864 // CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x02,0x00]
39865
39866 v_ldexp_f32 v5, s1, v2
39867 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x02,0x00]
39868
39869 v_ldexp_f32 v5, s101, v2
39870 // CHECK: [0x05,0x00,0x88,0xd2,0x65,0x04,0x02,0x00]
39871
39872 v_ldexp_f32 v5, flat_scratch_lo, v2
39873 // CHECK: [0x05,0x00,0x88,0xd2,0x66,0x04,0x02,0x00]
39874
39875 v_ldexp_f32 v5, flat_scratch_hi, v2
39876 // CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x02,0x00]
39877
39878 v_ldexp_f32 v5, vcc_lo, v2
39879 // CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x02,0x00]
39880
39881 v_ldexp_f32 v5, vcc_hi, v2
39882 // CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x02,0x00]
39883
39884 v_ldexp_f32 v5, m0, v2
39885 // CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x02,0x00]
39886
39887 v_ldexp_f32 v5, exec_lo, v2
39888 // CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x02,0x00]
39889
39890 v_ldexp_f32 v5, exec_hi, v2
39891 // CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x02,0x00]
39892
39893 v_ldexp_f32 v5, 0, v2
39894 // CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x02,0x00]
39895
39896 v_ldexp_f32 v5, -1, v2
39897 // CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x02,0x00]
39898
39899 v_ldexp_f32 v5, 0.5, v2
39900 // CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x02,0x00]
39901
39902 v_ldexp_f32 v5, -4.0, v2
39903 // CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x02,0x00]
39904
39905 v_ldexp_f32 v5, v1, v255
39906 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x03,0x00]
39907
39908 v_ldexp_f32 v5, v1, s2
39909 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x00,0x00]
39910
39911 v_ldexp_f32 v5, v1, s101
39912 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcb,0x00,0x00]
39913
39914 v_ldexp_f32 v5, v1, flat_scratch_lo
39915 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcd,0x00,0x00]
39916
39917 v_ldexp_f32 v5, v1, flat_scratch_hi
39918 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x00,0x00]
39919
39920 v_ldexp_f32 v5, v1, vcc_lo
39921 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x00,0x00]
39922
39923 v_ldexp_f32 v5, v1, vcc_hi
39924 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x00,0x00]
39925
39926 v_ldexp_f32 v5, v1, m0
39927 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x00,0x00]
39928
39929 v_ldexp_f32 v5, v1, exec_lo
39930 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x00,0x00]
39931
39932 v_ldexp_f32 v5, v1, exec_hi
39933 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x00,0x00]
39934
39935 v_ldexp_f32 v5, v1, 0
39936 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x01,0x00]
39937
39938 v_ldexp_f32 v5, v1, -1
39939 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x01,0x00]
39940
39941 v_ldexp_f32 v5, v1, 0.5
39942 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x01,0x00]
39943
39944 v_ldexp_f32 v5, v1, -4.0
39945 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x01,0x00]
39946
39947 v_ldexp_f32 v5, -v1, v2
39948 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x20]
39949
39950 v_ldexp_f32 v5, |v1|, v2
39951 // CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x02,0x00]
39952
39953 v_ldexp_f32 v5, v1, v2 clamp
39954 // CHECK: [0x05,0x80,0x88,0xd2,0x01,0x05,0x02,0x00]
39955
39956 v_ldexp_f32 v5, v1, v2 mul:2
39957 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x08]
39958
39959 v_ldexp_f32 v5, v1, v2 mul:4
39960 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x10]
39961
39962 v_ldexp_f32 v5, v1, v2 div:2
39963 // CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x18]
39964
39965 v_readlane_b32 s5, v1, s2
39966 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
39967
39968 v_readlane_b32 s101, v1, s2
39969 // CHECK: [0x65,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
39970
39971 v_readlane_b32 flat_scratch_lo, v1, s2
39972 // CHECK: [0x66,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
39973
39974 v_readlane_b32 flat_scratch_hi, v1, s2
39975 // CHECK: [0x67,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
39976
39977 v_readlane_b32 s5, v255, s2
39978 // CHECK: [0x05,0x00,0x89,0xd2,0xff,0x05,0x00,0x00]
39979
39980 v_readlane_b32 s5, v1, s101
39981 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcb,0x00,0x00]
39982
39983 v_readlane_b32 s5, v1, flat_scratch_lo
39984 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcd,0x00,0x00]
39985
39986 v_readlane_b32 s5, v1, flat_scratch_hi
39987 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcf,0x00,0x00]
39988
39989 v_readlane_b32 s5, v1, vcc_lo
39990 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd5,0x00,0x00]
39991
39992 v_readlane_b32 s5, v1, vcc_hi
39993 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd7,0x00,0x00]
39994
39995 v_readlane_b32 s5, v1, m0
39996 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf9,0x00,0x00]
39997
39998 v_readlane_b32 s5, v1, 0
39999 // CHECK: [0x05,0x00,0x89,0xd2,0x01,0x01,0x01,0x00]
40000
40001 v_writelane_b32 v5, 0, s2
40002 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
40003
40004 v_writelane_b32 v255, 0, s2
40005 // CHECK: [0xff,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
40006
40007 v_writelane_b32 v5, -1, s2
40008 // CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x00,0x00]
40009
40010 v_writelane_b32 v5, 0.5, s2
40011 // CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x00,0x00]
40012
40013 v_writelane_b32 v5, -4.0, s2
40014 // CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x00,0x00]
40015
40016 v_writelane_b32 v5, 0, s101
40017 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xca,0x00,0x00]
40018
40019 v_writelane_b32 v5, 0, flat_scratch_lo
40020 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xcc,0x00,0x00]
40021
40022 v_writelane_b32 v5, 0, flat_scratch_hi
40023 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xce,0x00,0x00]
40024
40025 v_writelane_b32 v5, 0, vcc_lo
40026 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd4,0x00,0x00]
40027
40028 v_writelane_b32 v5, 0, vcc_hi
40029 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd6,0x00,0x00]
40030
40031 v_writelane_b32 v5, 0, m0
40032 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf8,0x00,0x00]
40033
40034 v_writelane_b32 v5, 0, 0
40035 // CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x00,0x01,0x00]
40036
40037 v_bcnt_u32_b32 v5, v1, v2
40038 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
40039
40040 v_bcnt_u32_b32 v255, v1, v2
40041 // CHECK: [0xff,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
40042
40043 v_bcnt_u32_b32 v5, v255, v2
40044 // CHECK: [0x05,0x00,0x8b,0xd2,0xff,0x05,0x02,0x00]
40045
40046 v_bcnt_u32_b32 v5, s1, v2
40047 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x04,0x02,0x00]
40048
40049 v_bcnt_u32_b32 v5, s101, v2
40050 // CHECK: [0x05,0x00,0x8b,0xd2,0x65,0x04,0x02,0x00]
40051
40052 v_bcnt_u32_b32 v5, flat_scratch_lo, v2
40053 // CHECK: [0x05,0x00,0x8b,0xd2,0x66,0x04,0x02,0x00]
40054
40055 v_bcnt_u32_b32 v5, flat_scratch_hi, v2
40056 // CHECK: [0x05,0x00,0x8b,0xd2,0x67,0x04,0x02,0x00]
40057
40058 v_bcnt_u32_b32 v5, vcc_lo, v2
40059 // CHECK: [0x05,0x00,0x8b,0xd2,0x6a,0x04,0x02,0x00]
40060
40061 v_bcnt_u32_b32 v5, vcc_hi, v2
40062 // CHECK: [0x05,0x00,0x8b,0xd2,0x6b,0x04,0x02,0x00]
40063
40064 v_bcnt_u32_b32 v5, m0, v2
40065 // CHECK: [0x05,0x00,0x8b,0xd2,0x7c,0x04,0x02,0x00]
40066
40067 v_bcnt_u32_b32 v5, exec_lo, v2
40068 // CHECK: [0x05,0x00,0x8b,0xd2,0x7e,0x04,0x02,0x00]
40069
40070 v_bcnt_u32_b32 v5, exec_hi, v2
40071 // CHECK: [0x05,0x00,0x8b,0xd2,0x7f,0x04,0x02,0x00]
40072
40073 v_bcnt_u32_b32 v5, 0, v2
40074 // CHECK: [0x05,0x00,0x8b,0xd2,0x80,0x04,0x02,0x00]
40075
40076 v_bcnt_u32_b32 v5, -1, v2
40077 // CHECK: [0x05,0x00,0x8b,0xd2,0xc1,0x04,0x02,0x00]
40078
40079 v_bcnt_u32_b32 v5, 0.5, v2
40080 // CHECK: [0x05,0x00,0x8b,0xd2,0xf0,0x04,0x02,0x00]
40081
40082 v_bcnt_u32_b32 v5, -4.0, v2
40083 // CHECK: [0x05,0x00,0x8b,0xd2,0xf7,0x04,0x02,0x00]
40084
40085 v_bcnt_u32_b32 v5, v1, v255
40086 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x03,0x00]
40087
40088 v_bcnt_u32_b32 v5, v1, s2
40089 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x00,0x00]
40090
40091 v_bcnt_u32_b32 v5, v1, s101
40092 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcb,0x00,0x00]
40093
40094 v_bcnt_u32_b32 v5, v1, flat_scratch_lo
40095 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcd,0x00,0x00]
40096
40097 v_bcnt_u32_b32 v5, v1, flat_scratch_hi
40098 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcf,0x00,0x00]
40099
40100 v_bcnt_u32_b32 v5, v1, vcc_lo
40101 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd5,0x00,0x00]
40102
40103 v_bcnt_u32_b32 v5, v1, vcc_hi
40104 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd7,0x00,0x00]
40105
40106 v_bcnt_u32_b32 v5, v1, m0
40107 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x00,0x00]
40108
40109 v_bcnt_u32_b32 v5, v1, exec_lo
40110 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfd,0x00,0x00]
40111
40112 v_bcnt_u32_b32 v5, v1, exec_hi
40113 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x00,0x00]
40114
40115 v_bcnt_u32_b32 v5, v1, 0
40116 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x01,0x01,0x00]
40117
40118 v_bcnt_u32_b32 v5, v1, -1
40119 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x83,0x01,0x00]
40120
40121 v_bcnt_u32_b32 v5, v1, 0.5
40122 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xe1,0x01,0x00]
40123
40124 v_bcnt_u32_b32 v5, v1, -4.0
40125 // CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xef,0x01,0x00]
40126
40127 v_mbcnt_lo_u32_b32 v5, v1, v2
40128 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
40129
40130 v_mbcnt_lo_u32_b32 v255, v1, v2
40131 // CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
40132
40133 v_mbcnt_lo_u32_b32 v5, v255, v2
40134 // CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x02,0x00]
40135
40136 v_mbcnt_lo_u32_b32 v5, s1, v2
40137 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x02,0x00]
40138
40139 v_mbcnt_lo_u32_b32 v5, s101, v2
40140 // CHECK: [0x05,0x00,0x8c,0xd2,0x65,0x04,0x02,0x00]
40141
40142 v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
40143 // CHECK: [0x05,0x00,0x8c,0xd2,0x66,0x04,0x02,0x00]
40144
40145 v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
40146 // CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x02,0x00]
40147
40148 v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
40149 // CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x02,0x00]
40150
40151 v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
40152 // CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x02,0x00]
40153
40154 v_mbcnt_lo_u32_b32 v5, m0, v2
40155 // CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x02,0x00]
40156
40157 v_mbcnt_lo_u32_b32 v5, exec_lo, v2
40158 // CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x02,0x00]
40159
40160 v_mbcnt_lo_u32_b32 v5, exec_hi, v2
40161 // CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x02,0x00]
40162
40163 v_mbcnt_lo_u32_b32 v5, 0, v2
40164 // CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x02,0x00]
40165
40166 v_mbcnt_lo_u32_b32 v5, -1, v2
40167 // CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x02,0x00]
40168
40169 v_mbcnt_lo_u32_b32 v5, 0.5, v2
40170 // CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x02,0x00]
40171
40172 v_mbcnt_lo_u32_b32 v5, -4.0, v2
40173 // CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x02,0x00]
40174
40175 v_mbcnt_lo_u32_b32 v5, v1, v255
40176 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x03,0x00]
40177
40178 v_mbcnt_lo_u32_b32 v5, v1, s2
40179 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x00,0x00]
40180
40181 v_mbcnt_lo_u32_b32 v5, v1, s101
40182 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcb,0x00,0x00]
40183
40184 v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_lo
40185 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcd,0x00,0x00]
40186
40187 v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_hi
40188 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x00,0x00]
40189
40190 v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
40191 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x00,0x00]
40192
40193 v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
40194 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x00,0x00]
40195
40196 v_mbcnt_lo_u32_b32 v5, v1, m0
40197 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x00,0x00]
40198
40199 v_mbcnt_lo_u32_b32 v5, v1, exec_lo
40200 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x00,0x00]
40201
40202 v_mbcnt_lo_u32_b32 v5, v1, exec_hi
40203 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x00,0x00]
40204
40205 v_mbcnt_lo_u32_b32 v5, v1, 0
40206 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x01,0x00]
40207
40208 v_mbcnt_lo_u32_b32 v5, v1, -1
40209 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x01,0x00]
40210
40211 v_mbcnt_lo_u32_b32 v5, v1, 0.5
40212 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x01,0x00]
40213
40214 v_mbcnt_lo_u32_b32 v5, v1, -4.0
40215 // CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x01,0x00]
40216
40217 v_mbcnt_hi_u32_b32 v5, v1, v2
40218 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
40219
40220 v_mbcnt_hi_u32_b32 v255, v1, v2
40221 // CHECK: [0xff,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
40222
40223 v_mbcnt_hi_u32_b32 v5, v255, v2
40224 // CHECK: [0x05,0x00,0x8d,0xd2,0xff,0x05,0x02,0x00]
40225
40226 v_mbcnt_hi_u32_b32 v5, s1, v2
40227 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x04,0x02,0x00]
40228
40229 v_mbcnt_hi_u32_b32 v5, s101, v2
40230 // CHECK: [0x05,0x00,0x8d,0xd2,0x65,0x04,0x02,0x00]
40231
40232 v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
40233 // CHECK: [0x05,0x00,0x8d,0xd2,0x66,0x04,0x02,0x00]
40234
40235 v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
40236 // CHECK: [0x05,0x00,0x8d,0xd2,0x67,0x04,0x02,0x00]
40237
40238 v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
40239 // CHECK: [0x05,0x00,0x8d,0xd2,0x6a,0x04,0x02,0x00]
40240
40241 v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
40242 // CHECK: [0x05,0x00,0x8d,0xd2,0x6b,0x04,0x02,0x00]
40243
40244 v_mbcnt_hi_u32_b32 v5, m0, v2
40245 // CHECK: [0x05,0x00,0x8d,0xd2,0x7c,0x04,0x02,0x00]
40246
40247 v_mbcnt_hi_u32_b32 v5, exec_lo, v2
40248 // CHECK: [0x05,0x00,0x8d,0xd2,0x7e,0x04,0x02,0x00]
40249
40250 v_mbcnt_hi_u32_b32 v5, exec_hi, v2
40251 // CHECK: [0x05,0x00,0x8d,0xd2,0x7f,0x04,0x02,0x00]
40252
40253 v_mbcnt_hi_u32_b32 v5, 0, v2
40254 // CHECK: [0x05,0x00,0x8d,0xd2,0x80,0x04,0x02,0x00]
40255
40256 v_mbcnt_hi_u32_b32 v5, -1, v2
40257 // CHECK: [0x05,0x00,0x8d,0xd2,0xc1,0x04,0x02,0x00]
40258
40259 v_mbcnt_hi_u32_b32 v5, 0.5, v2
40260 // CHECK: [0x05,0x00,0x8d,0xd2,0xf0,0x04,0x02,0x00]
40261
40262 v_mbcnt_hi_u32_b32 v5, -4.0, v2
40263 // CHECK: [0x05,0x00,0x8d,0xd2,0xf7,0x04,0x02,0x00]
40264
40265 v_mbcnt_hi_u32_b32 v5, v1, v255
40266 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x03,0x00]
40267
40268 v_mbcnt_hi_u32_b32 v5, v1, s2
40269 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x00,0x00]
40270
40271 v_mbcnt_hi_u32_b32 v5, v1, s101
40272 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcb,0x00,0x00]
40273
40274 v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_lo
40275 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcd,0x00,0x00]
40276
40277 v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_hi
40278 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcf,0x00,0x00]
40279
40280 v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
40281 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd5,0x00,0x00]
40282
40283 v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
40284 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd7,0x00,0x00]
40285
40286 v_mbcnt_hi_u32_b32 v5, v1, m0
40287 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x00,0x00]
40288
40289 v_mbcnt_hi_u32_b32 v5, v1, exec_lo
40290 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfd,0x00,0x00]
40291
40292 v_mbcnt_hi_u32_b32 v5, v1, exec_hi
40293 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x00,0x00]
40294
40295 v_mbcnt_hi_u32_b32 v5, v1, 0
40296 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x01,0x01,0x00]
40297
40298 v_mbcnt_hi_u32_b32 v5, v1, -1
40299 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x83,0x01,0x00]
40300
40301 v_mbcnt_hi_u32_b32 v5, v1, 0.5
40302 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xe1,0x01,0x00]
40303
40304 v_mbcnt_hi_u32_b32 v5, v1, -4.0
40305 // CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xef,0x01,0x00]
40306
40307 v_lshlrev_b64 v[5:6], v1, v[2:3]
40308 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
40309
40310 v_lshlrev_b64 v[254:255], v1, v[2:3]
40311 // CHECK: [0xfe,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
40312
40313 v_lshlrev_b64 v[5:6], v255, v[2:3]
40314 // CHECK: [0x05,0x00,0x8f,0xd2,0xff,0x05,0x02,0x00]
40315
40316 v_lshlrev_b64 v[5:6], s1, v[2:3]
40317 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x04,0x02,0x00]
40318
40319 v_lshlrev_b64 v[5:6], s101, v[2:3]
40320 // CHECK: [0x05,0x00,0x8f,0xd2,0x65,0x04,0x02,0x00]
40321
40322 v_lshlrev_b64 v[5:6], flat_scratch_lo, v[2:3]
40323 // CHECK: [0x05,0x00,0x8f,0xd2,0x66,0x04,0x02,0x00]
40324
40325 v_lshlrev_b64 v[5:6], flat_scratch_hi, v[2:3]
40326 // CHECK: [0x05,0x00,0x8f,0xd2,0x67,0x04,0x02,0x00]
40327
40328 v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
40329 // CHECK: [0x05,0x00,0x8f,0xd2,0x6a,0x04,0x02,0x00]
40330
40331 v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
40332 // CHECK: [0x05,0x00,0x8f,0xd2,0x6b,0x04,0x02,0x00]
40333
40334 v_lshlrev_b64 v[5:6], m0, v[2:3]
40335 // CHECK: [0x05,0x00,0x8f,0xd2,0x7c,0x04,0x02,0x00]
40336
40337 v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
40338 // CHECK: [0x05,0x00,0x8f,0xd2,0x7e,0x04,0x02,0x00]
40339
40340 v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
40341 // CHECK: [0x05,0x00,0x8f,0xd2,0x7f,0x04,0x02,0x00]
40342
40343 v_lshlrev_b64 v[5:6], 0, v[2:3]
40344 // CHECK: [0x05,0x00,0x8f,0xd2,0x80,0x04,0x02,0x00]
40345
40346 v_lshlrev_b64 v[5:6], -1, v[2:3]
40347 // CHECK: [0x05,0x00,0x8f,0xd2,0xc1,0x04,0x02,0x00]
40348
40349 v_lshlrev_b64 v[5:6], 0.5, v[2:3]
40350 // CHECK: [0x05,0x00,0x8f,0xd2,0xf0,0x04,0x02,0x00]
40351
40352 v_lshlrev_b64 v[5:6], -4.0, v[2:3]
40353 // CHECK: [0x05,0x00,0x8f,0xd2,0xf7,0x04,0x02,0x00]
40354
40355 v_lshlrev_b64 v[5:6], v1, v[254:255]
40356 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x03,0x00]
40357
40358 v_lshlrev_b64 v[5:6], v1, s[4:5]
40359 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x09,0x00,0x00]
40360
40361 v_lshlrev_b64 v[5:6], v1, s[6:7]
40362 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x0d,0x00,0x00]
40363
40364 v_lshlrev_b64 v[5:6], v1, s[100:101]
40365 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xc9,0x00,0x00]
40366
40367 v_lshlrev_b64 v[5:6], v1, flat_scratch
40368 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xcd,0x00,0x00]
40369
40370 v_lshlrev_b64 v[5:6], v1, vcc
40371 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd5,0x00,0x00]
40372
40373 v_lshlrev_b64 v[5:6], v1, exec
40374 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x00,0x00]
40375
40376 v_lshlrev_b64 v[5:6], v1, 0
40377 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x01,0x01,0x00]
40378
40379 v_lshlrev_b64 v[5:6], v1, -1
40380 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x83,0x01,0x00]
40381
40382 v_lshlrev_b64 v[5:6], v1, 0.5
40383 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xe1,0x01,0x00]
40384
40385 v_lshlrev_b64 v[5:6], v1, -4.0
40386 // CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xef,0x01,0x00]
40387
40388 v_lshrrev_b64 v[5:6], v1, v[2:3]
40389 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
40390
40391 v_lshrrev_b64 v[254:255], v1, v[2:3]
40392 // CHECK: [0xfe,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
40393
40394 v_lshrrev_b64 v[5:6], v255, v[2:3]
40395 // CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x02,0x00]
40396
40397 v_lshrrev_b64 v[5:6], s1, v[2:3]
40398 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x02,0x00]
40399
40400 v_lshrrev_b64 v[5:6], s101, v[2:3]
40401 // CHECK: [0x05,0x00,0x90,0xd2,0x65,0x04,0x02,0x00]
40402
40403 v_lshrrev_b64 v[5:6], flat_scratch_lo, v[2:3]
40404 // CHECK: [0x05,0x00,0x90,0xd2,0x66,0x04,0x02,0x00]
40405
40406 v_lshrrev_b64 v[5:6], flat_scratch_hi, v[2:3]
40407 // CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x02,0x00]
40408
40409 v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
40410 // CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x02,0x00]
40411
40412 v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
40413 // CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x02,0x00]
40414
40415 v_lshrrev_b64 v[5:6], m0, v[2:3]
40416 // CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x02,0x00]
40417
40418 v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
40419 // CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x02,0x00]
40420
40421 v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
40422 // CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x02,0x00]
40423
40424 v_lshrrev_b64 v[5:6], 0, v[2:3]
40425 // CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x02,0x00]
40426
40427 v_lshrrev_b64 v[5:6], -1, v[2:3]
40428 // CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x02,0x00]
40429
40430 v_lshrrev_b64 v[5:6], 0.5, v[2:3]
40431 // CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x02,0x00]
40432
40433 v_lshrrev_b64 v[5:6], -4.0, v[2:3]
40434 // CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x02,0x00]
40435
40436 v_lshrrev_b64 v[5:6], v1, v[254:255]
40437 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x03,0x00]
40438
40439 v_lshrrev_b64 v[5:6], v1, s[4:5]
40440 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0x09,0x00,0x00]
40441
40442 v_lshrrev_b64 v[5:6], v1, s[6:7]
40443 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0x0d,0x00,0x00]
40444
40445 v_lshrrev_b64 v[5:6], v1, s[100:101]
40446 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xc9,0x00,0x00]
40447
40448 v_lshrrev_b64 v[5:6], v1, flat_scratch
40449 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcd,0x00,0x00]
40450
40451 v_lshrrev_b64 v[5:6], v1, vcc
40452 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x00,0x00]
40453
40454 v_lshrrev_b64 v[5:6], v1, exec
40455 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x00,0x00]
40456
40457 v_lshrrev_b64 v[5:6], v1, 0
40458 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x01,0x00]
40459
40460 v_lshrrev_b64 v[5:6], v1, -1
40461 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x01,0x00]
40462
40463 v_lshrrev_b64 v[5:6], v1, 0.5
40464 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x01,0x00]
40465
40466 v_lshrrev_b64 v[5:6], v1, -4.0
40467 // CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x01,0x00]
40468
40469 v_ashrrev_i64 v[5:6], v1, v[2:3]
40470 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
40471
40472 v_ashrrev_i64 v[254:255], v1, v[2:3]
40473 // CHECK: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
40474
40475 v_ashrrev_i64 v[5:6], v255, v[2:3]
40476 // CHECK: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x00]
40477
40478 v_ashrrev_i64 v[5:6], s1, v[2:3]
40479 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x00]
40480
40481 v_ashrrev_i64 v[5:6], s101, v[2:3]
40482 // CHECK: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x00]
40483
40484 v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3]
40485 // CHECK: [0x05,0x00,0x91,0xd2,0x66,0x04,0x02,0x00]
40486
40487 v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3]
40488 // CHECK: [0x05,0x00,0x91,0xd2,0x67,0x04,0x02,0x00]
40489
40490 v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
40491 // CHECK: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x00]
40492
40493 v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
40494 // CHECK: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x00]
40495
40496 v_ashrrev_i64 v[5:6], m0, v[2:3]
40497 // CHECK: [0x05,0x00,0x91,0xd2,0x7c,0x04,0x02,0x00]
40498
40499 v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
40500 // CHECK: [0x05,0x00,0x91,0xd2,0x7e,0x04,0x02,0x00]
40501
40502 v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
40503 // CHECK: [0x05,0x00,0x91,0xd2,0x7f,0x04,0x02,0x00]
40504
40505 v_ashrrev_i64 v[5:6], 0, v[2:3]
40506 // CHECK: [0x05,0x00,0x91,0xd2,0x80,0x04,0x02,0x00]
40507
40508 v_ashrrev_i64 v[5:6], -1, v[2:3]
40509 // CHECK: [0x05,0x00,0x91,0xd2,0xc1,0x04,0x02,0x00]
40510
40511 v_ashrrev_i64 v[5:6], 0.5, v[2:3]
40512 // CHECK: [0x05,0x00,0x91,0xd2,0xf0,0x04,0x02,0x00]
40513
40514 v_ashrrev_i64 v[5:6], -4.0, v[2:3]
40515 // CHECK: [0x05,0x00,0x91,0xd2,0xf7,0x04,0x02,0x00]
40516
40517 v_ashrrev_i64 v[5:6], v1, v[254:255]
40518 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x03,0x00]
40519
40520 v_ashrrev_i64 v[5:6], v1, s[4:5]
40521 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0x09,0x00,0x00]
40522
40523 v_ashrrev_i64 v[5:6], v1, s[6:7]
40524 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0x0d,0x00,0x00]
40525
40526 v_ashrrev_i64 v[5:6], v1, s[100:101]
40527 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xc9,0x00,0x00]
40528
40529 v_ashrrev_i64 v[5:6], v1, flat_scratch
40530 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xcd,0x00,0x00]
40531
40532 v_ashrrev_i64 v[5:6], v1, vcc
40533 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd5,0x00,0x00]
40534
40535 v_ashrrev_i64 v[5:6], v1, exec
40536 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x00,0x00]
40537
40538 v_ashrrev_i64 v[5:6], v1, 0
40539 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0x01,0x01,0x00]
40540
40541 v_ashrrev_i64 v[5:6], v1, -1
40542 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0x83,0x01,0x00]
40543
40544 v_ashrrev_i64 v[5:6], v1, 0.5
40545 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xe1,0x01,0x00]
40546
40547 v_ashrrev_i64 v[5:6], v1, -4.0
40548 // CHECK: [0x05,0x00,0x91,0xd2,0x01,0xef,0x01,0x00]
40549
40550 v_trig_preop_f64 v[5:6], v[1:2], v2
40551 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
40552
40553 v_trig_preop_f64 v[254:255], v[1:2], v2
40554 // CHECK: [0xfe,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
40555
40556 v_trig_preop_f64 v[5:6], v[254:255], v2
40557 // CHECK: [0x05,0x00,0x92,0xd2,0xfe,0x05,0x02,0x00]
40558
40559 v_trig_preop_f64 v[5:6], s[2:3], v2
40560 // CHECK: [0x05,0x00,0x92,0xd2,0x02,0x04,0x02,0x00]
40561
40562 v_trig_preop_f64 v[5:6], s[4:5], v2
40563 // CHECK: [0x05,0x00,0x92,0xd2,0x04,0x04,0x02,0x00]
40564
40565 v_trig_preop_f64 v[5:6], s[100:101], v2
40566 // CHECK: [0x05,0x00,0x92,0xd2,0x64,0x04,0x02,0x00]
40567
40568 v_trig_preop_f64 v[5:6], flat_scratch, v2
40569 // CHECK: [0x05,0x00,0x92,0xd2,0x66,0x04,0x02,0x00]
40570
40571 v_trig_preop_f64 v[5:6], vcc, v2
40572 // CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x02,0x00]
40573
40574 v_trig_preop_f64 v[5:6], exec, v2
40575 // CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x02,0x00]
40576
40577 v_trig_preop_f64 v[5:6], 0, v2
40578 // CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x02,0x00]
40579
40580 v_trig_preop_f64 v[5:6], -1, v2
40581 // CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x02,0x00]
40582
40583 v_trig_preop_f64 v[5:6], 0.5, v2
40584 // CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x02,0x00]
40585
40586 v_trig_preop_f64 v[5:6], -4.0, v2
40587 // CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x02,0x00]
40588
40589 v_trig_preop_f64 v[5:6], v[1:2], v255
40590 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x03,0x00]
40591
40592 v_trig_preop_f64 v[5:6], v[1:2], s2
40593 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x00,0x00]
40594
40595 v_trig_preop_f64 v[5:6], v[1:2], s101
40596 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcb,0x00,0x00]
40597
40598 v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
40599 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcd,0x00,0x00]
40600
40601 v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
40602 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x00,0x00]
40603
40604 v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
40605 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x00,0x00]
40606
40607 v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
40608 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x00,0x00]
40609
40610 v_trig_preop_f64 v[5:6], v[1:2], m0
40611 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x00,0x00]
40612
40613 v_trig_preop_f64 v[5:6], v[1:2], exec_lo
40614 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x00,0x00]
40615
40616 v_trig_preop_f64 v[5:6], v[1:2], exec_hi
40617 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x00,0x00]
40618
40619 v_trig_preop_f64 v[5:6], v[1:2], 0
40620 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x01,0x00]
40621
40622 v_trig_preop_f64 v[5:6], v[1:2], -1
40623 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x01,0x00]
40624
40625 v_trig_preop_f64 v[5:6], v[1:2], 0.5
40626 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x01,0x00]
40627
40628 v_trig_preop_f64 v[5:6], v[1:2], -4.0
40629 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x01,0x00]
40630
40631 v_trig_preop_f64 v[5:6], -v[1:2], v2
40632 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x20]
40633
40634 v_trig_preop_f64 v[5:6], |v[1:2]|, v2
40635 // CHECK: [0x05,0x01,0x92,0xd2,0x01,0x05,0x02,0x00]
40636
40637 v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
40638 // CHECK: [0x05,0x80,0x92,0xd2,0x01,0x05,0x02,0x00]
40639
40640 v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
40641 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x08]
40642
40643 v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
40644 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x10]
40645
40646 v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
40647 // CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x18]
40648
40649 v_bfm_b32 v5, v1, v2
40650 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
40651
40652 v_bfm_b32 v255, v1, v2
40653 // CHECK: [0xff,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
40654
40655 v_bfm_b32 v5, v255, v2
40656 // CHECK: [0x05,0x00,0x93,0xd2,0xff,0x05,0x02,0x00]
40657
40658 v_bfm_b32 v5, s1, v2
40659 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0x04,0x02,0x00]
40660
40661 v_bfm_b32 v5, s101, v2
40662 // CHECK: [0x05,0x00,0x93,0xd2,0x65,0x04,0x02,0x00]
40663
40664 v_bfm_b32 v5, flat_scratch_lo, v2
40665 // CHECK: [0x05,0x00,0x93,0xd2,0x66,0x04,0x02,0x00]
40666
40667 v_bfm_b32 v5, flat_scratch_hi, v2
40668 // CHECK: [0x05,0x00,0x93,0xd2,0x67,0x04,0x02,0x00]
40669
40670 v_bfm_b32 v5, vcc_lo, v2
40671 // CHECK: [0x05,0x00,0x93,0xd2,0x6a,0x04,0x02,0x00]
40672
40673 v_bfm_b32 v5, vcc_hi, v2
40674 // CHECK: [0x05,0x00,0x93,0xd2,0x6b,0x04,0x02,0x00]
40675
40676 v_bfm_b32 v5, m0, v2
40677 // CHECK: [0x05,0x00,0x93,0xd2,0x7c,0x04,0x02,0x00]
40678
40679 v_bfm_b32 v5, exec_lo, v2
40680 // CHECK: [0x05,0x00,0x93,0xd2,0x7e,0x04,0x02,0x00]
40681
40682 v_bfm_b32 v5, exec_hi, v2
40683 // CHECK: [0x05,0x00,0x93,0xd2,0x7f,0x04,0x02,0x00]
40684
40685 v_bfm_b32 v5, 0, v2
40686 // CHECK: [0x05,0x00,0x93,0xd2,0x80,0x04,0x02,0x00]
40687
40688 v_bfm_b32 v5, -1, v2
40689 // CHECK: [0x05,0x00,0x93,0xd2,0xc1,0x04,0x02,0x00]
40690
40691 v_bfm_b32 v5, 0.5, v2
40692 // CHECK: [0x05,0x00,0x93,0xd2,0xf0,0x04,0x02,0x00]
40693
40694 v_bfm_b32 v5, -4.0, v2
40695 // CHECK: [0x05,0x00,0x93,0xd2,0xf7,0x04,0x02,0x00]
40696
40697 v_bfm_b32 v5, v1, v255
40698 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x03,0x00]
40699
40700 v_bfm_b32 v5, v1, s2
40701 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x00,0x00]
40702
40703 v_bfm_b32 v5, v1, s101
40704 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcb,0x00,0x00]
40705
40706 v_bfm_b32 v5, v1, flat_scratch_lo
40707 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcd,0x00,0x00]
40708
40709 v_bfm_b32 v5, v1, flat_scratch_hi
40710 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcf,0x00,0x00]
40711
40712 v_bfm_b32 v5, v1, vcc_lo
40713 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd5,0x00,0x00]
40714
40715 v_bfm_b32 v5, v1, vcc_hi
40716 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd7,0x00,0x00]
40717
40718 v_bfm_b32 v5, v1, m0
40719 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x00,0x00]
40720
40721 v_bfm_b32 v5, v1, exec_lo
40722 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfd,0x00,0x00]
40723
40724 v_bfm_b32 v5, v1, exec_hi
40725 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x00,0x00]
40726
40727 v_bfm_b32 v5, v1, 0
40728 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0x01,0x01,0x00]
40729
40730 v_bfm_b32 v5, v1, -1
40731 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0x83,0x01,0x00]
40732
40733 v_bfm_b32 v5, v1, 0.5
40734 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xe1,0x01,0x00]
40735
40736 v_bfm_b32 v5, v1, -4.0
40737 // CHECK: [0x05,0x00,0x93,0xd2,0x01,0xef,0x01,0x00]
40738
40739 v_cvt_pknorm_i16_f32 v5, v1, v2
40740 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
40741
40742 v_cvt_pknorm_i16_f32 v255, v1, v2
40743 // CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
40744
40745 v_cvt_pknorm_i16_f32 v5, v255, v2
40746 // CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x02,0x00]
40747
40748 v_cvt_pknorm_i16_f32 v5, s1, v2
40749 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x02,0x00]
40750
40751 v_cvt_pknorm_i16_f32 v5, s101, v2
40752 // CHECK: [0x05,0x00,0x94,0xd2,0x65,0x04,0x02,0x00]
40753
40754 v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
40755 // CHECK: [0x05,0x00,0x94,0xd2,0x66,0x04,0x02,0x00]
40756
40757 v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
40758 // CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x02,0x00]
40759
40760 v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
40761 // CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x02,0x00]
40762
40763 v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
40764 // CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x02,0x00]
40765
40766 v_cvt_pknorm_i16_f32 v5, m0, v2
40767 // CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x02,0x00]
40768
40769 v_cvt_pknorm_i16_f32 v5, exec_lo, v2
40770 // CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x02,0x00]
40771
40772 v_cvt_pknorm_i16_f32 v5, exec_hi, v2
40773 // CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x02,0x00]
40774
40775 v_cvt_pknorm_i16_f32 v5, 0, v2
40776 // CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x02,0x00]
40777
40778 v_cvt_pknorm_i16_f32 v5, -1, v2
40779 // CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x02,0x00]
40780
40781 v_cvt_pknorm_i16_f32 v5, 0.5, v2
40782 // CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x02,0x00]
40783
40784 v_cvt_pknorm_i16_f32 v5, -4.0, v2
40785 // CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x02,0x00]
40786
40787 v_cvt_pknorm_i16_f32 v5, v1, v255
40788 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x03,0x00]
40789
40790 v_cvt_pknorm_i16_f32 v5, v1, s2
40791 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x00,0x00]
40792
40793 v_cvt_pknorm_i16_f32 v5, v1, s101
40794 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcb,0x00,0x00]
40795
40796 v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_lo
40797 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcd,0x00,0x00]
40798
40799 v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_hi
40800 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x00,0x00]
40801
40802 v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
40803 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x00,0x00]
40804
40805 v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
40806 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x00,0x00]
40807
40808 v_cvt_pknorm_i16_f32 v5, v1, m0
40809 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x00,0x00]
40810
40811 v_cvt_pknorm_i16_f32 v5, v1, exec_lo
40812 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x00,0x00]
40813
40814 v_cvt_pknorm_i16_f32 v5, v1, exec_hi
40815 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x00,0x00]
40816
40817 v_cvt_pknorm_i16_f32 v5, v1, 0
40818 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x01,0x00]
40819
40820 v_cvt_pknorm_i16_f32 v5, v1, -1
40821 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x01,0x00]
40822
40823 v_cvt_pknorm_i16_f32 v5, v1, 0.5
40824 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x01,0x00]
40825
40826 v_cvt_pknorm_i16_f32 v5, v1, -4.0
40827 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x01,0x00]
40828
40829 v_cvt_pknorm_i16_f32 v5, -v1, v2
40830 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x20]
40831
40832 v_cvt_pknorm_i16_f32 v5, v1, -v2
40833 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x40]
40834
40835 v_cvt_pknorm_i16_f32 v5, -v1, -v2
40836 // CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x60]
40837
40838 v_cvt_pknorm_i16_f32 v5, |v1|, v2
40839 // CHECK: [0x05,0x01,0x94,0xd2,0x01,0x05,0x02,0x00]
40840
40841 v_cvt_pknorm_i16_f32 v5, v1, |v2|
40842 // CHECK: [0x05,0x02,0x94,0xd2,0x01,0x05,0x02,0x00]
40843
40844 v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
40845 // CHECK: [0x05,0x03,0x94,0xd2,0x01,0x05,0x02,0x00]
40846
40847 v_cvt_pknorm_i16_f32 v5, v1, v2 clamp
40848 // CHECK: [0x05,0x80,0x94,0xd2,0x01,0x05,0x02,0x00]
40849
40850 v_cvt_pknorm_u16_f32 v5, v1, v2
40851 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
40852
40853 v_cvt_pknorm_u16_f32 v255, v1, v2
40854 // CHECK: [0xff,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
40855
40856 v_cvt_pknorm_u16_f32 v5, v255, v2
40857 // CHECK: [0x05,0x00,0x95,0xd2,0xff,0x05,0x02,0x00]
40858
40859 v_cvt_pknorm_u16_f32 v5, s1, v2
40860 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x04,0x02,0x00]
40861
40862 v_cvt_pknorm_u16_f32 v5, s101, v2
40863 // CHECK: [0x05,0x00,0x95,0xd2,0x65,0x04,0x02,0x00]
40864
40865 v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
40866 // CHECK: [0x05,0x00,0x95,0xd2,0x66,0x04,0x02,0x00]
40867
40868 v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
40869 // CHECK: [0x05,0x00,0x95,0xd2,0x67,0x04,0x02,0x00]
40870
40871 v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
40872 // CHECK: [0x05,0x00,0x95,0xd2,0x6a,0x04,0x02,0x00]
40873
40874 v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
40875 // CHECK: [0x05,0x00,0x95,0xd2,0x6b,0x04,0x02,0x00]
40876
40877 v_cvt_pknorm_u16_f32 v5, m0, v2
40878 // CHECK: [0x05,0x00,0x95,0xd2,0x7c,0x04,0x02,0x00]
40879
40880 v_cvt_pknorm_u16_f32 v5, exec_lo, v2
40881 // CHECK: [0x05,0x00,0x95,0xd2,0x7e,0x04,0x02,0x00]
40882
40883 v_cvt_pknorm_u16_f32 v5, exec_hi, v2
40884 // CHECK: [0x05,0x00,0x95,0xd2,0x7f,0x04,0x02,0x00]
40885
40886 v_cvt_pknorm_u16_f32 v5, 0, v2
40887 // CHECK: [0x05,0x00,0x95,0xd2,0x80,0x04,0x02,0x00]
40888
40889 v_cvt_pknorm_u16_f32 v5, -1, v2
40890 // CHECK: [0x05,0x00,0x95,0xd2,0xc1,0x04,0x02,0x00]
40891
40892 v_cvt_pknorm_u16_f32 v5, 0.5, v2
40893 // CHECK: [0x05,0x00,0x95,0xd2,0xf0,0x04,0x02,0x00]
40894
40895 v_cvt_pknorm_u16_f32 v5, -4.0, v2
40896 // CHECK: [0x05,0x00,0x95,0xd2,0xf7,0x04,0x02,0x00]
40897
40898 v_cvt_pknorm_u16_f32 v5, v1, v255
40899 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x03,0x00]
40900
40901 v_cvt_pknorm_u16_f32 v5, v1, s2
40902 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x00,0x00]
40903
40904 v_cvt_pknorm_u16_f32 v5, v1, s101
40905 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcb,0x00,0x00]
40906
40907 v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_lo
40908 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcd,0x00,0x00]
40909
40910 v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_hi
40911 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcf,0x00,0x00]
40912
40913 v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
40914 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd5,0x00,0x00]
40915
40916 v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
40917 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd7,0x00,0x00]
40918
40919 v_cvt_pknorm_u16_f32 v5, v1, m0
40920 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x00,0x00]
40921
40922 v_cvt_pknorm_u16_f32 v5, v1, exec_lo
40923 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfd,0x00,0x00]
40924
40925 v_cvt_pknorm_u16_f32 v5, v1, exec_hi
40926 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x00,0x00]
40927
40928 v_cvt_pknorm_u16_f32 v5, v1, 0
40929 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x01,0x01,0x00]
40930
40931 v_cvt_pknorm_u16_f32 v5, v1, -1
40932 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x83,0x01,0x00]
40933
40934 v_cvt_pknorm_u16_f32 v5, v1, 0.5
40935 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xe1,0x01,0x00]
40936
40937 v_cvt_pknorm_u16_f32 v5, v1, -4.0
40938 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0xef,0x01,0x00]
40939
40940 v_cvt_pknorm_u16_f32 v5, -v1, v2
40941 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x20]
40942
40943 v_cvt_pknorm_u16_f32 v5, v1, -v2
40944 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x40]
40945
40946 v_cvt_pknorm_u16_f32 v5, -v1, -v2
40947 // CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x60]
40948
40949 v_cvt_pknorm_u16_f32 v5, |v1|, v2
40950 // CHECK: [0x05,0x01,0x95,0xd2,0x01,0x05,0x02,0x00]
40951
40952 v_cvt_pknorm_u16_f32 v5, v1, |v2|
40953 // CHECK: [0x05,0x02,0x95,0xd2,0x01,0x05,0x02,0x00]
40954
40955 v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
40956 // CHECK: [0x05,0x03,0x95,0xd2,0x01,0x05,0x02,0x00]
40957
40958 v_cvt_pknorm_u16_f32 v5, v1, v2 clamp
40959 // CHECK: [0x05,0x80,0x95,0xd2,0x01,0x05,0x02,0x00]
40960
40961 v_cvt_pkrtz_f16_f32 v5, v1, v2
40962 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
40963
40964 v_cvt_pkrtz_f16_f32 v255, v1, v2
40965 // CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
40966
40967 v_cvt_pkrtz_f16_f32 v5, v255, v2
40968 // CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x02,0x00]
40969
40970 v_cvt_pkrtz_f16_f32 v5, s1, v2
40971 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x02,0x00]
40972
40973 v_cvt_pkrtz_f16_f32 v5, s101, v2
40974 // CHECK: [0x05,0x00,0x96,0xd2,0x65,0x04,0x02,0x00]
40975
40976 v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
40977 // CHECK: [0x05,0x00,0x96,0xd2,0x66,0x04,0x02,0x00]
40978
40979 v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
40980 // CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x02,0x00]
40981
40982 v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
40983 // CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x02,0x00]
40984
40985 v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
40986 // CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x02,0x00]
40987
40988 v_cvt_pkrtz_f16_f32 v5, m0, v2
40989 // CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x02,0x00]
40990
40991 v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
40992 // CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x02,0x00]
40993
40994 v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
40995 // CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x02,0x00]
40996
40997 v_cvt_pkrtz_f16_f32 v5, 0, v2
40998 // CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x02,0x00]
40999
41000 v_cvt_pkrtz_f16_f32 v5, -1, v2
41001 // CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x02,0x00]
41002
41003 v_cvt_pkrtz_f16_f32 v5, 0.5, v2
41004 // CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x02,0x00]
41005
41006 v_cvt_pkrtz_f16_f32 v5, -4.0, v2
41007 // CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x02,0x00]
41008
41009 v_cvt_pkrtz_f16_f32 v5, v1, v255
41010 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x03,0x00]
41011
41012 v_cvt_pkrtz_f16_f32 v5, v1, s2
41013 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x00,0x00]
41014
41015 v_cvt_pkrtz_f16_f32 v5, v1, s101
41016 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcb,0x00,0x00]
41017
41018 v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_lo
41019 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcd,0x00,0x00]
41020
41021 v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_hi
41022 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x00,0x00]
41023
41024 v_cvt_pkrtz_f16_f32 v5, v1, vcc_lo
41025 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x00,0x00]
41026
41027 v_cvt_pkrtz_f16_f32 v5, v1, vcc_hi
41028 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x00,0x00]
41029
41030 v_cvt_pkrtz_f16_f32 v5, v1, m0
41031 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x00,0x00]
41032
41033 v_cvt_pkrtz_f16_f32 v5, v1, exec_lo
41034 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x00,0x00]
41035
41036 v_cvt_pkrtz_f16_f32 v5, v1, exec_hi
41037 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x00,0x00]
41038
41039 v_cvt_pkrtz_f16_f32 v5, v1, 0
41040 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x01,0x00]
41041
41042 v_cvt_pkrtz_f16_f32 v5, v1, -1
41043 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x01,0x00]
41044
41045 v_cvt_pkrtz_f16_f32 v5, v1, 0.5
41046 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x01,0x00]
41047
41048 v_cvt_pkrtz_f16_f32 v5, v1, -4.0
41049 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x01,0x00]
41050
41051 v_cvt_pkrtz_f16_f32 v5, -v1, v2
41052 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x20]
41053
41054 v_cvt_pkrtz_f16_f32 v5, v1, -v2
41055 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x40]
41056
41057 v_cvt_pkrtz_f16_f32 v5, -v1, -v2
41058 // CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x60]
41059
41060 v_cvt_pkrtz_f16_f32 v5, |v1|, v2
41061 // CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x02,0x00]
41062
41063 v_cvt_pkrtz_f16_f32 v5, v1, |v2|
41064 // CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x02,0x00]
41065
41